1. Introduction
In recent years, analog circuit design has received much attention, particularly those with Very Large Scale of Integration (VLSI), because optimization is a process that involves many conflicting constraints and a wide range of parameters [
1]. For small circuits, the equations can be stated by hand, as in the design of passive filters [
2]. However, developing more robust Computer-Aided Design (CAD) and Electronic Design Automation (EDA) tools is necessary to increase productivity and quality and minimize design costs [
3].
The design of analog circuits comprises three major stages: selecting a topology, sizing components, and layout extraction [
4]. In the case of sizing, it is possible to use the experience when the circuits are small, but manual circuit-sizing in analog design is a time-consuming process [
5]. When the circuit grows, it is impossible to size the components solely by experience; thus, mathematical tools are necessary to optimize the circuits [
6].
The complexity when manually implementing an analog project is usually weeks or months. CAD and EDA tools are used to improve the design process; today’s analog design environment is made of CAD tools for editing, evaluation, and design verification of analog integrated circuits, for example, HSPICE, SMASH, and CADENCE. Circuit simulators do not allow the use of methods such as quadratic or geometric programming, which exploit particular characteristics of the models. As a result, stochastic heuristic optimization techniques are used instead [
7], such as in [
8].
Many optimization techniques and tools for automation design have been developed over time [
9,
10]. Also, the fuzzy logic has been used for the circuit design as in [
11,
12], or in [
13], where a multi-objective design is presented, while in [
14], a tool for analog synthesis is introduced. In [
15], a Neuro-Fuzzy method for analog circuit design is presented; it is of easy implementation, natural understanding, and better performance than static methods of fuzzy optimization; however, it still needs the human experience in the particular circuit to be designed. In [
16], the application of an innovative algorithm of the type Customized Genetic Algorithm (CAG) is reported. Its purpose is to improve the optimization process of analog Complementary Metal-Oxide-Semiconductor (CMOS) ICs. A framework for facilitating the design of analog amplifiers is presented in [
17].
More recently, evolutionary algorithms have been successfully applied to component value selection for analog active filters [
18,
19], facility location problem [
20], truss structures [
21], and to the analog integrated circuits design as in [
22], where the sizing is achieved using a Particle Swarm Optimization (PSO) algorithm implemented in MATLAB R2008a and the results verified at the end with SPICE. In [
23], a CMOS differential amplifier and a two stages CMOS op-amp are optimized to occupy the minimal possible area by the circuits and to improve their performances using the gravitational search algorithm in combination with the particle swarm optimization (GSA-PSO). The design is formulated as an optimization problem with a single objective function, although certain manual tuning is necessary to resolve conflicts with either design or performance parameters when using this method. In the work [
24], a crazy PSO (CRPSO) is applied to improve the premature convergence to a local minimum of the PSO; the application optimizes the minimization of the total Metal-Oxide-Semiconductor (MOS) area of two amplifier configurations, a two-stage P-Channel MOS (PMOS) type operational amplifier, and an N-Channel MOS (NMOS) cascade code amplifier.
Heuristic techniques are necessary to solve problems with many design constraints [
25]. Although they do not guarantee finding the optimal solution exactly, they provide an acceptable approximation to it in an acceptable computation time [
26]. Therefore, another challenge for sizing high-performance analog circuits with tight specifications is the need for a powerful enough optimization kernel for EDA tools to handle tighter specifications and improve optimization capability [
27]. Different optimization kernels are currently used for EDA tools; among them, we can mention the kernels based on GA [
28], PSO [
29], Ant Colony Optimization (ACO) in [
30], Simulated Annealing (SA) in [
31], GSA in [
23], Non-dominated Sorting Genetic Algorithm-II (NSGA-II) in [
32] and NSGA-II, Multi-Objective Particle Swarm Optimization (MOPSO), and Multi-Objective Simulated Annealing (MOSA) in [
33].
Most heuristic methods used in the optimization kernels of the EDA tools are based on multi-objective optimization techniques [
7,
32] or use a restriction approach with a single objective and static penalty functions [
34]. Penalty functions penalize non-feasible solutions by adding a specific value to the objective function as an amount proportional to the violation of the restriction. Thus, the optimization problem is transformed into a restrictionless optimization problem. The main problem with this methodology is choosing the appropriate penalty factor for a particular problem; it is often a complicated task, but if an adequate factor is selected, a premature convergence can occur or solutions outside the feasible region can be obtained [
35]. Another approach currently used in problems with restrictions is self-adaptive penalty functions, which significantly improve the results [
36]. Unfortunately, many last-generation restricted optimization methods have yet to be introduced into EDA tools. Therefore, advanced restricted optimization methods should be applied to circuit dimensioning tools to address this challenge.
In recent years, algorithms inspired by cellular automata neighborhoods to perform a local search, such as Cellular-PSO (CPSO) [
37], CPSO-DE [
38], Continuous-state Cellular Automata Algorithm (CCAA) [
39], and Majority-minority Cellular Automata Algorithm (MmCAA) [
40], have shown excellent performance in solving global optimization problems, demonstrating a good balance between exploration and exploitation, as well as a good speed of convergence. Among them, the CPSO-DE has proven to be an excellent design method for identifying adaptive IIR systems due to the use of a differential evolution rule for the neighborhoods of cellular automata of the PSO that improves the balance between exploration and exploitation than the original version of the CPSO.
According to the previous observations, this document introduces the hybrid continuous optimization algorithm called CPSO-DE that incorporates local-search neighborhoods to improve PSO exploitation capabilities with DE exploitability. The algorithm was tested on established benchmark functions of Congress on Evolutionary Computation (CEC 2005) [
41] against 7 recently published algorithms for global optimization, yielded satisfactory results.
Additionally, Deb’s rules were incorporated into the algorithm to address constrained optimization [
42,
43]; this algorithm is called Ts-CPD applied in a single design objective problem, for the sizing of analog circuits to improve their performance. The approach is used as the optimization core of an EDA tool to size CMOS analog circuits efficiently. In particular, we focus on diminishing the total component area as the objective. At the same time, other specifications, such as dc gain, bandwidth and power dissipation, are treated as constraints that guarantee good overall performance. The circuits chosen for testing our method are well known, which allows a comparison of results with other proposals. We implemented the optimization in Matlab while the circuit simulation was done in Ngspice. Both optimization and simulation parts are linked.
We compare our proposal with previously published works, including PSO variants such as Particle Swarm Optimization (PSO) [
22], Genetic Algorithm (GA) [
44], Harmony Search (HS) [
45], Differential Evolution (DE) [
45], Artificial Bee Colony (ABC) [
45], Gravitational Search Algorithm PSO (GSA-PSO) [
23], Geometric Programming (GP) [
46] and Aging Leader and Challenger PSO (ALC-PSO) [
1]. The results show that Ts-CPSO can find a better circuit design solution than the above-listed approaches. In addition, it shows a rapid convergence in all the studied cases.
Overall, the proposed CPSO-DE algorithm is easy to understand, performs exceptionally well for continuous optimization, and is modified with Deb’s rules to define the Ts-CPD algorithm in order to tackle problems with multiple constraints, as demonstrated in the area optimization of CMOS analog circuits.
The rest of the paper is organized as follows:
Section 2 gives a review of CPSO-DE, while the hybridization of CPSO-DE with constrained optimization is explained in
Section 3.
Section 4 describes three circuits in terms of their design variables and constraints.
Section 5 validates the proposed Ts-CPD through three cases of study, contrasting the findings against results from previous works. Finally, this article is concluded in
Section 6.
3. Tournament-Selection CPD
The use of local search strategies inspired by cellular automata neighborhoods in heuristic algorithms has been shown to be effective, more specifically, in the use of adaptive IIR filters through the hybridization of the CPSO and DE algorithms that use a rule based on the use of neighborhoods. However, the CPSO-DE algorithm for the problem with restrictions on the sizing of CMOS circuits has not yet been reported in the literature, hence the motivation for this work.
In this section, we explain the parts that comprise the proposed Ts-CPD algorithm. First, we describe the optimization problem to be solved, which contemplates restrictions. Next, we explain how the initial values are selected, for our algorithm, using tournament selection (Ts), which is a variant of what Deb proposed [
42]. We conclude this section by explaining the implementation of the Deb rule in the CPSO-DE, to build the new Ts-CPD algorithm.
3.1. The Circuit Design Problem
Many optimization problems in science and engineering implicate some constraints that the optimal solution must satisfy. For example, in a generic circuit, the optimization problem consists of finding optimal values of the design parameters. Then, a circuit design problem is usually written as a nonlinear programming (NLP) problem of the following type:
In the above NLP problem, f is the cost function that maps the input space into the output one, n = k + m. There are two types of constraints,
inequality constraints that have to be major or minor than certain , and the
equality constraints , that has to be equal to the restriction . The ith variable varies in the range .
The
k independent variables and
m dependent ones determine the circuit design represented in a single vector as,
The design variables and constraints for specific circuits studied in this paper are given in the
Section 4.
3.2. Tournament-Selection
As in the cost function f(X) of the optimization problem expressed in (
11), the restrictions are not considered; we need a method that allows us to assess their contribution. In [
42], Deb proposes a constraint handling method so that while the cost function is minimized, the constraints in the search for the minimum are considered. We will use Deb’s method in this work, as explained below.
Let’s say that the CPSO-DE algorithm has encountered two solutions for the problem (
11),
and
, according to the constrained optimization, solution
is considered better if [
43]:
both solutions are feasible, but cost cost; or,
is feasible but is not; or,
both solutions are unfeasible, but has less overall constraint violations than .
These rules, implemented as Algorithm 1, are advantageous in finding a better solution for the circuit design, as will be shown in
Section 5.
Algorithm 1 Tournament-Selection |
- 1:
if is feasible and is feasible then - 2:
if then - 3:
return - 4:
else - 5:
return - 6:
end if - 7:
else if constraints violation constraints violation then - 8:
return - 9:
else - 10:
return - 11:
end if
|
3.3. Ts-CPD Algorithm
This work proposes a new methodology that combines the CPSO-DE algorithm and Deb’s rules for the problem of sizing CMOS analog circuits with constraints. The proposed algorithm, Ts-CPD, incorporates the tournament selection (see Algorithm 1) in the
function. In this method, a new transition rule is proposed for Ts-CPD, which is applied to the trial vectors to update the state of the current smart-cell:
The transition rule in (
13) means that each cell in the neighborhood (including the same smart-cell) competes in a paired tournament (according to Deb criteria), and the winner is chosen to update the state of the smart-cell.
The proposed Ts-CPD method is described in Algorithm 2. First, the algorithm sets the control parameters
Q,
l,
T,
,
y
. Next, the state
and velocity
are randomly initialized for each smart-cell. Then, each cell is evaluated, and its number of violated constraints is quantified. In line 9, Algorithm 1 is used to identify the best global position. The process halts according to the stopping criteria of iteration and convergence, according to line 10. Then, the cell state is updated using (
6) and (
7) in line 12. Later, the neighborhood of size
l is generated for each smart-cell, using the DE method. Each neighbor is defined by the mutation and crossover rules in lines 14 and 15 using (
8) and (
9), respectively. The new transition rule inspired by Deb’s rules and CA behavior, defined in (
13), is applied in line 16 to determine the new cell state. Finally, the best local and global positions are updated in lines 18 and 19, respectively, using Algorithm 1. The process is repeated by each smart-cell and neighbor.
Algorithm 2 Ts-CPD |
- 1:
//** Initialization - 2:
Set the control parameters: Q, l, T, , , ; - 3:
for to Q do - 4:
Initialize randomly; - 5:
Initialize randomly; - 6:
; - 7:
end for - 8:
Evaluate each cell ; - 9:
Identify the best global position : using Algorithm 1; //*** Loop - 10:
while stopping criterion is not satisfied do - 11:
for to Q do - 12:
Update cell state: using Equations ( 6) and ( 7); //***Generate l neighbors using DE method - 13:
for to l do - 14:
Mutation rule: using Equation ( 8); - 15:
Crossover rule: using Equation ( 9); - 16:
New transition rule: using Equation ( 13); - 17:
end for - 18:
Identify the best local position : using Algorithm 1; - 19:
end for - 20:
Identify the best global position : using Algorithm 1; - 21:
end while
|
3.4. Performance of the Ts-CPD Algorithm
To test the effectiveness of the Ts-CPD algorithm (without Deb’s rules), we compared it to seven recently published algorithms, namely Archimedes Optimization Algorithm (AOA) [
56], Harris Hawks Optimization (HHO) [
57], Weighted Superposition Attraction (WSA) [
58], CCAA [
39], MmCAA [
40], Reversible Elementary Cellular Automata (RECAA) [
59], and Political Optimizer (PO) [
60]. 25 benchmark functions were used from CEC 2005 benchmark functions [
41], which included five unimodal functions (
), seven multimodal functions (
), two expanded multimodal functions (
), and 11 hybrid composition multimodal functions (
). We obtained the codes and parameters for these algorithms from the references cited in this study. This ensured that we used the same implementations as the original authors, making the comparison more objective. All parameter settings are given in
Table 1.
Table 2 and
Table 3 present the average values and standard deviations of the objective function values obtained by each algorithm. We ran each algorithm independently 30 times. In unimodal problems, the Ts-CPD algorithm showed excellent performance, ranking first among the eight algorithms in terms of average value. Moreover, it surpassed other algorithms in three cases based on standard deviation, highlighting its proficiency in information exploitation.
For the 20 multimodal and hybrid problems, Ts-CPD exhibited the highest average values in 12 instances. It also demonstrated its ability to explore and exploit simultaneously while maintaining robustness, achieving the best standard deviation values in four cases.
Table 4 presents the results of the Wilcoxon rank-sum statistical test which compares Ts-CPD with other methods for each benchmark function. The symbol + indicates a better result that is statistically significant, ≈ indicates no significant difference, and − indicates a worse statistically significant result. The Avg column presents the average rank obtained by each algorithm when optimizing the benchmark functions. The Rank column shows the order in which each algorithm is ranked based on its average. Ts-CDP obtained the best rank, followed by RECAA. In all cases, Ts-CPD obtained a more significant difference in terms of the number of functions with a better significant result in this experiment. In addition,
Figure 3 shows some examples of the convergence curves for different test functions in 30 dimensions.
3.5. Complexity Analysis of the Ts-CPD Algorithm
Most evolutionary algorithms imply a complexity of the following three main parts [
60,
61]:
Initialization of population, generally bounded by where U is the population size and D the dimensionality of the problem.
Fitness evaluation is bounded in general by where is the cost of evaluating the objective function.
Optimization loop, generally bounded by , here T is the total iteration number of the loop.
The complexity analysis of the Ts-CPD algorithm takes into account these three parts:
Initialization of population is bounded by , similar to other algorithms (lines 3–7 in Algorithm 2).
Fitness evaluation is bounded by in line 8. Notice that Algorithm 1 is linear with regard to when using Deb criteria. The best global position is calculated in in line 9.
For the optimization loop, smart-cells are updated with complexity (line 12); mutation and crossover have complexity (lines 14 and 15), and the new transition rule is in line 16. The best local position in line 18 is calculated in , and the best global position is in line 20. Therefore, the complexity of the optimization loop asymptotically tends to , which is also equivalent to the other algorithms.
The complexity analysis concludes that the Ts-CPD algorithm is asymptotically equivalent to the other state-of-the-art methods when is similar to U.
4. The Proposed Tool for Analog IC Sizing
The EDA tool proposed for the designer of analog circuits through the Ts-CPD algorithm allows obtaining a minimum area of the components used while complying with the design specifications. It is handy for designing the frequency response of circuits, such as bandwidth, phase margin, Common Mode Rejection Ratio (CMRR), or Power Supply Rejection Ratio (PSRR); only the slew rate can be designed in the time domain. For this purpose, before beginning the design, the designer must introduce the specifications (restrictions) of the circuit and the acceptable ranges and values for the parameters according to the technology used. The parameters to choose are the width and length of the CMOS transistors, capacitance and resistance (if any) values, bias current, and voltage sources.
The tool consists of two main modules: the optimization and synthesis processes. The optimization process contains the Ts-CPD algorithm comprising the CPSO-DE and the Deb rule, with a new transition rule given by (
13); this module is implemented in Matlab. The synthesis process uses the specialized Ngspice v26 software, which allows analog circuit simulations without mathematical equations. Instead, the standard configurations necessary to evaluate the performance of circuits are implemented in a netlist format. Both modules, the optimization and synthesis processes, are linked, allowing an automatic circuit design. The flow chart for our EDA tool, using Ts-CPD, is shown in
Figure 4.
The following subsection describes three case studies, in terms of their variables and constraints, that will be used to verify the efficiency of the EDA tool.
4.1. Cases of Study
To test our algorithm and tool, we chose three case studies, a “CMOS Differential Amplifier”, a “CMOS two-stage operational amplifier”, and a “CMOS folded cascode operational transconductance amplifier”. These cases were chosen because they have already been studied previously, and therefore, it is possible to compare the results of our algorithm against previous results, which is very interesting. In this sense, case 1 has 5 independent variables and 11 restrictions to meet, case 2 has 5 independent variables and 11 restrictions, while case 3, the most complete, has 9 independent variables and 13 restrictions to meet at the same time.
4.1.1. Case 1: CMOS Differential Amplifier
Figure 5 shows our first case of study, a CMOS differential amplifier, where,
W is the width and
L is the length of the CMOS transistor. First,
must be equally sized than
; thus, the following equality restrictions must be satisfied:
Secondly, s of the current source,
and
, must be equally sized, too, thus
We let both
and
be independent variables, and our algorithm selects their values while
. That is because the sizes of all s are within a specific range imposed by the technology used for this design:
In our case, was fixed to 4 m for a better comparison with other works, and was fixed to m to have a value large enough. For this example, there are 5 independent variables (, , , and ) and 2 dependent ones ( and ). On the other hand, the design specifications to be met will be treated as constraints. For this case, there are 11 constraints: load capacitance, slew rate, power dissipation, phase margin, cut-off frequency, DC gain, (min), (max), Common Mode Rejection Ratio (CMRR), Positive Power Supply Rejection Ratio (PSRR+) and Negative Power Supply Rejection Ratio (PSRR−).
4.1.2. Case 2: CMOS Two-Stage Operational Amplifier
Figure 6 shows our second case of study, a CMOS two-stage operational amplifier consisting of 8 s. The first amplification stage, differential input, has the stipulation that
must be equally sized as
, so that Equations (
15) and (
14) are still valid, and we add,
Also, to avoid an output offset at the second amplification stage, the following restriction is imposed:
Similarly, as in (
16), sizes of the CMOS two-stage operational amplifier are in a specific range, but now
. Also, the compensation capacitance is within a range of values, between
and
, which the designer selects:
The and values are fed to the Ts-CPD algorithm through a file in our EDA tool. We choose pF, because lower values than that are challenging to achieve and pF to avoid using significant areas, but these values are easily changed.
On the other hand, bias current
also is within a range o values:
It is clear from Equations (
15), (
14) and (
17) that, for the purpose of design,
and
can be handled as independent variables, while
and
as can be handled as dependent ones.
is deduced from (
18), thus,
is also a dependent variable;
and
are considered independent variables whose values are bounded by (
19) and (
20), respectively. Therefore, this example has 5 independent variables,
and
, whose values are selected by our algorithm and 5 dependent variables
and
, whose impact over cost function and restrictions is evaluated by our algorithm to determine new values for independent variables, in an iterative process.
In this paper, the length of s is considered constant. However, when lengths are considered variables, the minimum and maximum values must be established, as for widths in Equation (
16). For this case, there are 11 constraints: load capacitance, slew rate, power dissipation, phase margin, unity gain bandwidth, DC gain,
(min),
(max), CMRR, PSRR+, and PSRR−.
4.1.3. Case 3: CMOS Foilded Cascode Operational Transconductance Amplifier
A third case of study is the Folded Cascode Operational Transconductance Amplifier (FCOTA) shown in
Figure 7. The transistors
and
are equally sized; thus, Equation (
15) is also valid. We considered the transistor widths
and
independent variables and
and
dependent ones, as follows:
In addition,
,
,
and
are considered independent variables while
,
,
,
, and
are considered dependent variables, as follows:
Table 5.
Design criteria for CMOS differential amplifier (Case 1) and results obtained with several evolutionary algorithms. The best values are in bold.
Table 5.
Design criteria for CMOS differential amplifier (Case 1) and results obtained with several evolutionary algorithms. The best values are in bold.
Design Criteria | Specs. | Ts-CPD | MOL [62] | SOA [63] | PSO [22] | HS [45] | DE [45] | ABC [45] | GA [44] |
---|
Load capacitance (pF) | ≥2 | 2.1 | 5 | 3.5 | 5 | 5 | 5 | 5 | 2 |
Slew rate (V/s) | ≥10 | 24.3 | 10 | 12.28 | 22.4 | 14.916 | 18.451 | 15.67 | 3.2 |
Power dissipation (W) | ≤2000 | 1075 | 863 | 117 | 1260 | 886 | 990 | 830 | 31 |
Phase margin () | >45 | 86.1 | 89 | 83.73 | 83.8 | 89.1 | 88.81 | 91.248 | 72 |
Cut-off frequency (KHz) | ≥100 | 100.5 | - | 104.8 | 100 | 114 | 129.7 | 112.367 | - |
Unity gain bandwidth (MHz) | ≥1 | 10 | 17.87 | 12.5 | 12.3 | - | - | - | 3.8 |
DC gain (dB) | ≥40 | 40.3 | 30 | 44.02 | 42 | 40.98 | 41.23 | 42.045 | 60 |
(min) (V) | ≥−1.5 | −0.8 | −0.5 | −0.37 | −0.8 | −0.7 | −0.92 | −0.97 | −1.3 |
(max) (V) | ≤2 | 1.1 | 0.7 | 1.57 | 1.4 | 1.2 | 1.15 | 1.2 | 1.9 |
CMRR (dB) | >40 | 81.0 | 59 | 83.17 | 84.2 | 78.5 | 78.39 | 79.67 | - |
PSRR+ (dB) | >40 | 41.2 | 41 | 60.59 | 40.1 | 42.93 | 43.14 | 43.857 | - |
PSRR− (dB) | >40 | 78.1 | 68 | 108.6 | 68 | 67.64 | 68.175 | 68.423 | - |
Total component area () | <300 | 109 | 235 | 236 | 296 | - | - | - | 6500 |
(MHz·pF)/(W·mm) | | 179 | 457 | 318 | 165 | - | - | - | 40 |
The values of the bias current
are bounded by (
20) and properly selected by our algorithm. For design, we considered
as an independent variable. Thus, our algorithm also selects its value within
, while
is considered a dependent variable, with
. This way, there are 9 independent variables (
,
,
,
,
,
,
,
and
) and 9 dependent variables (
,
,
,
,
,
,
,
and
). The constraints for this case are 13: load capacitance, slew rate, power dissipation, phase margin, unity gain bandwidth, DC gain,
(min),
(max),
(min),
(max), CMRR, PSRR+ and PSRR−.
5. Numerical Results and Discussion
In order to test our proposed tool, three examples of design are shown in this section. First, the optimization is implemented in MATLAB R2014b, while the simulation of circuits is implemented in the NGSPICE r26 simulator; both are linked, so the design process is completely automated. On the other hand, the model of NMOS and PMOS transistors for 0.35 m technology was downloaded from the MOL database. Finally, the transistor lengths were set to fixed values close to those in the literature for comparison purposes.
Our design objective is to minimize the area of analog circuits. However, designing an amplifier is always a trade-off, so we introduce the Area Figure of Merit for small-signal
that considers silicon area to assess the designed circuits’ overall performance [
64]:
where
is the unity gain frequency,
is the load capacitance,
is the power consumption at quiescent, and Area is the component (transistors) area.
5.1. Numerical Results for CMOS Differential Amplifier (Case 1)
As a first example, the differential amplifier of
Figure 5 is designed. We aim to minimize the total component area, which is our cost function, below
m
while restrictions are still met. As shown in
Table 5, the power dissipation is specified to be <
W, DC gain ≥40 dB, slew rate
V/
s and the cut-off frequency
KHz. Other specifications are CMRR, PSRR+, PSRR−, and the Input Common-Mode Range (ICMR), all to be >40 dB, and finally
V and
V. The circuit’s load determines load capacitance, but the specification to be satisfied is
pF; we choose 2.1 pF. The AFOM
is also shown.
For the optimization purpose, some variables are set to a fixed value, and the micro-channel lengths were set to m, m, and voltage sources were set to V. On the other hand, and are treated as independent variables with restrictions, i.e., they can run within a specific range of values in our algorithm.
The numerical results for the differential amplifier of
Figure 5 are shown in
Table 5; it presents a comparison of Ts-CPD with several methods: Many Optimizing Liaisons (MOLs) [
62], Seeker Optimization Algorithm (SOA) [
63], PSO [
22], Harmony Search (HS) [
45], DE [
45], Artificial Bee Colony (ABC) [
45], and GA [
44]. The Ts-CPD obtains the lower total component area for methods that report this design objective and obtains the higher slew rate and PSRR−; other specifications are also accomplished. Here, the MOLs algorithm has the higher AFOM
value.
Table 6 shows the result of the designed differential amplifier for three evolutionary algorithms.
In order to explore the performance of the differential amplifier designed, we show the DC gain and phase margin in
Figure 8a; The CMRR, PSRR+, and PSRR− in
Figure 8b; Slew rate in
Figure 8c; and the ICMR in
Figure 8d, which is used for the graphical determination of
(min) and
(max). These graphics demonstrate that the designed circuit behaves well and is accomplished with all the constraints (Specifications).
Figure 9a shows the convergence of our algorithm for this circuit design, which has an excellent profile. Our algorithm’s behavior was also tested with 50 runs; the corresponding Box and Whisker plot is shown in
Figure 9b. The median is 1.4168 ×
, which is still below the results reported for other algorithms; see
Table 5.
5.2. Numerical Results for CMOS Two-Stage Operational Amplifier (Case 2)
As a second example, we designed the two-stage operational amplifier in
Figure 6. Again, the aim is to minimize the total component area as much as possible while constraints are still met. The total component area is specified to be <300
m
, and in this case, the DC gain
dB, unity gain bandwidth
MHz, phase margin
, slew rate
V/
s and load capacitance
pF. In other set of specifications, CMRR
dB, PSRR
dB, PSRR
dB,
V and
V. At the end, the AFOM
is shown.
The microchannel lengths of all MOS transistors have been set to a fixed value,
m, while voltage sources are set to
V. Here,
and
are independent variables. Thus, our algorithm determines its values in concordance with (
19) and (
20), respectively.
Table 7 shows the complete set of restrictions and design objective for the CMOS operational amplifier of
Figure 6, as well as the comparison of methods Ts-CPD, GSA-PSO [
23], PSO, and Geometric Programming (GP) [
46]. As expected, the Ts-CPD has the lower component area and the highest slew rate and PSRR−. The AFOM
, on the other hand, is higher for our algorithm. The design parameters of the optimized circuit are shown in
Table 8.
The performance of the CMOS two-stage operational amplifier can be evaluated through the gain and phase plot in
Figure 10a; the CMRR, PSRR+, and PSRR− plots in
Figure 10b; the ICMR in
Figure 10c; and the slew rate in
Figure 10d. These plots also demonstrate the excellent performance of the designed circuit.
On the other hand, we evaluated the performance of our algorithm with the convergence profile in
Figure 11a, and the Box and Whisker plot of
Figure 11b. After 16 iterations, the Ts-CPD reached convergence; see
Figure 11a. We executed 50 trial runs for the circuit design;
Figure 11b shows the corresponding Box and Whisker plot for the total MOS area of transistors. The best value is 4.557
, but the median (6.1738
) is also lower than others reported for this circuit, as can be seen in
Table 7.
5.3. Numerical Results for CMOS Folded Cascode Operational Transconductance Amplifier (Case 3)
Our third example is the folded cascode operational amplifier shown in
Figure 7. The total component area specified is
m
(our design objective). At the same time, specified constraints are gain
dB, unity bandwidth
MHz, phase margin
, slew rate
V
and load capacitance
pF (we chose exactly 10.0 pF). More constraints are CMRR, PSRR+, PSRR− all three
dB,
,
, and finally
and
. And at the end, the AFOM
is shown.
For all MOS transistors, the lengths have been set to a fixed value, m, and the voltage sources are set to V. Besides the transistor widths (), , and are also variables.
Table 9 shows the numerical results for the FCOTA of
Figure 7 and a comparison of methods Ts-CPD and PSO with Aging Leader and Challengers (ALC-PSO) [
1]. Our proposal, Ts-CPD, has the lower total component area (our design objective) and the highest Unity gain bandwidth, phase margin, CMRR, and PSRR−, while other constraints are also met. Additionally, the AFOM
is greater for our algorithm. The parameters of the optimized circuit for the two proposals are shown in
Table 10.
The excellent performance of the CMOS folded cascode operational transconductance amplifier is demonstrated through the plots of gain and phase in
Figure 12a; CMRR, PSRR+, and PSRR− in
Figure 12b; the slew rate in
Figure 12c; and the ICMR,
Figure 12d.
The Ts-CPD performance is evaluated with the convergence profile shown in
Figure 13a and the Box and Whisker plot of
Figure 13b. As can be seen in
Figure 13a, the Ts-CPD converges very quickly for this circuit design in just 5 iterations.
Figure 13b shows the Box and Whisker plot for 50 trial runs for the total MOS area of transistors. The median is 5.9674
, and the solutions are very clustered towards this value.
6. Conclusions
The Ts-CPSO algorithm that was proposed and implemented improves the CPSO by incorporating a way of evaluating the performance of constraints, through the optimization-with-constraints method, with a new rule we proposed. This algorithm has the advantage of not only minimizing the objective function but also ensuring that the constraints are met and then generating the new parameter values. Then the Ts-CPSO algorithm is incorporated into our EDA tool for the optimal sizing of analog circuits, which does not require mathematical equations since the optimization is linked to a simulator that provides the circuit’s behavior.
The Ts-CPD algorithm, as part of our EDA tool, was tested with three cases of study in a 0.35 μm CMOS technology, a differential amplifier, a two-stage operational amplifier, and a folded cascode operational transconductance amplifier. It was proposed as a design objective to reduce the total area occupied by the transistors while complying with some established constraints. In all cases, our tool found a better solution, for the objective, than previously reported tools, while the constraints were kept within the desired limits.
In future work, we are going to implement a multi-objective algorithm, which we will add as the kernel of our EDA tool. We will also do design tests with analog circuits with more transistors and large-scale analog circuits, such as the Analog-to-Digital Converter (ADC), considering the Layout design. As another potential future project, a framework incorporating multiple algorithms for optimizing various analog circuits can be developed. This framework would allow users to customize each algorithm’s parameters to enhance its performance, compare the different methods with convergence plots and identify the optimal design. It would be interesting to conduct a future study comparing Ts-CPD with other algorithms that are known for their success in solving CEC test problems and real-world applications. Some of these algorithms include Adaptive Differential Evolution with Optional External Archive (JADE), Success-History Based Adaptive Differential Evolution (SHADE), Self-adaptive Differential Evolution with Lévy-flight (LSHADE) and Improving Multi-objective Differential Evolutionary (IMODE).