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Architectural and Integration Options for 3D NAND Flash Memories
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Computers 2017, 6(4), 28; doi:10.3390/computers6040028

3D NAND Flash Based on Planar Cells

Macronix, Via Val Passiria 8, Milan 20100, Italy
Received: 28 July 2017 / Revised: 17 September 2017 / Accepted: 27 September 2017 / Published: 24 October 2017
(This article belongs to the Special Issue 3D Flash Memories)
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Abstract

In this article, the transition from 2D NAND to 3D NAND is first addressed, and the various 3D NAND architectures are compared. The article carries out a comparison of 3D NAND architectures that are based on a “punch-and-plug” process—with gate-all-around (GAA) cell devices—against architectures that are based on planar cell devices. The differences and similarities between the two classes of architectures are highlighted. The differences between architectures using floating-gate (FG) and charge-trap (CT) devices are also considered. Although the current production of 3D NAND is based on GAA cell devices, it is suggested that architectures with planar cell devices could also be viable for mass production. View Full-Text
Keywords: NAND flash; 3D NAND flash NAND flash; 3D NAND flash
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This is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. (CC BY 4.0).

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Silvagni, A. 3D NAND Flash Based on Planar Cells. Computers 2017, 6, 28.

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