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Materials 2017, 10(10), 1220; doi:10.3390/ma10101220

Effect of Wafer Level Underfill on the Microbump Reliability of Ultrathin-Chip Stacking Type 3D-IC Assembly during Thermal Cycling Tests

Department of Power Mechanical Engineering, National Tsing Hua University, No. 101, Section 2, Kuang-Fu Road, Hsinchu 30013, Taiwan
Received: 28 August 2017 / Revised: 19 October 2017 / Accepted: 23 October 2017 / Published: 24 October 2017
(This article belongs to the Special Issue Selected Papers from IMETI2016)
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Abstract

The microbump (μ-bump) reliability of 3D integrated circuit (3D-IC) packaging must be enhanced, in consideration of the multi-chip assembly, during temperature cycling tests (TCT). This research proposes vehicle fabrications, experimental implements, and a nonlinear finite element analysis to systematically investigate the assembled packaging architecture that stacks four thin chips through the wafer level underfill (WLUF) process. The assembly of μ-bump interconnects by daisy chain design shows good quality. Results of both TCT data and the simulation indicate that μ-bumps with residual SnAg solders can reach more than 1200 fatigue life cycles. Moreover, several important design factors in the present 3D-IC package influence μ-bump reliability. Analytical results show that the μ-bump’s thermo-mechanical reliability can be improved by setting proper chip thickness, along with a WLUF that has a low elastic modulus and a small coefficient of thermal expansion. View Full-Text
Keywords: 3D integrated circuits; microbump reliability; wafer level underfill; temperature cycling test; finite element analysis 3D integrated circuits; microbump reliability; wafer level underfill; temperature cycling test; finite element analysis
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Lee, C.-C. Effect of Wafer Level Underfill on the Microbump Reliability of Ultrathin-Chip Stacking Type 3D-IC Assembly during Thermal Cycling Tests. Materials 2017, 10, 1220.

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