Integrated Three-Voltage-Booster DC-DC Converter to Achieve High Voltage Gain with Leakage-Energy Recycling for PV or Fuel-Cell Power Systems

Abstract

In this paper, an integrated three-voltage-booster DC-DC (direct current to direct current) converter is proposed to achieve high voltage gain for renewable-energy generation systems. The proposed converter integrates three voltage-boosters into one power stage, which is composed of an active switch, a coupled-inductor, five diodes, and five capacitors. As compared with conventional high step-up converters, it has a lower component count. In addition, the features of leakage-energy recycling and switching loss reduction can be accomplished for conversion efficiency improvement. While the active switch is turned off, the converter can inherently clamp the voltage across power switch and suppress voltage spikes. Moreover, the reverse-recovery currents of all diodes can be alleviated by leakage inductance. A 200 W prototype operating at 100 kHz switching frequency with 36 V input and 400 V output is implemented to verify the theoretical analysis and to demonstrate the feasibility of the proposed high step-up DC-DC converter.

1. Introduction

In recent years, owing to the shortage of fossil fuels and the serious problems of environmental pollution, discovering and developing alternative energy resources has become more and more important. To alleviate the problems of rising global temperatures and the serious emission of greenhouse gases, green energy sources such as photovoltaic (PV) power, wind energy, or fuel cells have been the center of attention [1,2]. Generally, a grid-tied renewable-energy system needs a DC bus voltage falling in the range from 380 to 420 V, as shown in Figure 1. Unfortunately, the terminal voltages of PV module, fuel cells, or battery set are less than 45 V. That is, these green-energy generation units require a high step-up converter to serve as a voltage boosting interface between the generation unit and the utility.

Figure 1. A block diagram to illustrate the grid-tied green-energy power system.

Figure 1. A block diagram to illustrate the grid-tied green-energy power system.

Conventional boost converters can achieve high voltage gains by means of extreme duty ratio operation [3,4,5,6]. However, this will result in large current ripple, significant conduction loss, and heavy current stress on power devices. That is, converter efficiency drops dramatically. In order to resolve this problem, converters with transformers, such as flyback, forward, and push-pull units, are considered [7,8,9,10]. Even though those converters can step up input voltage by adopting high turns-ratio transformers, efficiency is degraded heavily due to the copper loss of windings. Besides, high voltage spikes caused from leakage inductance will be imposed on semiconductor devices. To improve this shortcoming, snubber circuits or active clamp circuits are used but then the cost is increased. In [11,12,13,14], transformerless high step-up converters are proposed to mitigate the aforementioned drawbacks. Those converters have the features of simple structure, high voltage gain, and low cost, nevertheless, the problem of voltage gain inflexibility still exists. In the most current trend, switched capacitor and coupled inductor techniques are adopted to design high step-up converters [15,16,17,18,19]. Those high step-up converters have their own advantages and disadvantages, and result in a compromise between power component count, voltage gain, current stress, voltage stress, and power rating. This paper proposes a novel high step-up converter, which incorporates three voltage boosters and then integrates them into one stage. That is, only one active switch is used. As a result, low component count, concise structure, high voltage gain, easy control circuit design, and high efficiency are its inherent features. Figure 2 depicts the configuration of the power stage.

Figure 2. Power circuit of the proposed high step-up converter.

Figure 2. Power circuit of the proposed high step-up converter.

This paper is organized as follows: the operation principle of the proposed converter is described in Section 2. Section 3 deals with steady-state analysis and performance comparison, while practical measurements are given in Section 4. Finally, the conclusions are described in Section 5.

2. Operation Principle of the Proposed Converter

For the description of the operation principle, Figure 3 shows the definition of circuit variables, voltage polarity, and current direction. In Figure 3, the notations V_in and I_in denote the DC input voltage and current, respectively; L_m is the magnetizing inductance of the coupled inductor, while L_k stands for the associated leakage inductance; S represents the active power switch; C₁ and C₄ are switched capacitors; C₂ and C₃ are boosting capacitors; D₁, D₂, D₃, and D₄ are rectifier diodes; D_o denotes output diode; V_o and I_o are described as output voltage and current, respectively, while R is the output load. In addition, the turns ratio N_s/N_p is defined as n.

Figure 3. Definition of voltage polarity and current direction.

Figure 3. Definition of voltage polarity and current direction.

Assume that the converter is operated in continuous conduction mode (CCM). The operation principle can be divided into six stages over one switching period. Figure 4 shows the corresponding equivalent circuits of the six stages and Figure 5 depicts the associated conceptual waveforms. The operation principle is described in the following paragraphs stage by stage:

• Stage 1 [t₀~t₁]: At time t = t₀, switch S is turned on. Diodes D₁, D₂ and D₄ are reversely biased, but D₃ and D_o are forward biased. In this time interval, the current of leakage-inductor i_Lk increases linearly and steeply. The energy stored in magnetizing-inductor L_m is released to the output via D_o and boosts capacitor C₂ via D₃. Meanwhile, the current following through D_o, i_Do, is decreasing. Until the current i_Do drops to zero, this operation stage ends. There is no reverse-recovery loss on diode D_o. Figure 4a shows the equivalent circuit of this stage.
• Stage 2 [t₁~t₂]: This stage begins at time t = t₁, of which equivalent circuit is shown in Figure 4b. Switch S remains closed. Diodes D₁, D₃ and D_o are reversely biased, but D₂ and D₄ are forward biased. In this time interval, the magnetizing-inductor L_m and leakage-inductor L_k absorb energy from the DC source V_in. The switched capacitor C₁ is charged by the secondary of the coupled inductor and capacitor C₃, while the other switched capacitor C₄ is by the secondary of the coupled inductor and capacitor C₂. During this stage, only the output capacitor C_o provides energy to the load R. When switch S is turned off, operation of this converter enters into the next stage.
• Stage 3 [t₂~t₃]: Switch S is turned off at t = t₂. During this stage, diodes D₁, D₂ and D₄ are in on-state, but diodes D₃ and D_o are reversely biased. In this time interval, the energy of leakage-inductor L_k releases to the parasitic capacitor of switch S and thus, switch voltage increases. When the voltage across the parasitic capacitor is higher than that of boosting capacitor C₃, diode D₁ becomes forward and this operation stage is completed. Figure 4c illustrates the corresponding equivalent of Stage 3.
• Stage 4 [t₃~t₄]: Switch S is still kept in off-state over the period of Stage 4. Diodes D₂, D₃ and D_o are reversely biased, but diodes D₁, and D₄ are in forward bias, as shown in Figure 4d. The boosting capacitor C₃ is charged by magnetizing-inductor L_m and leakage-inductor L_k. That is, leakage energy of L_k is recycled to C₃ and the voltage across active switch is clamped by C₃, which suppresses voltage spike effectively. At the moment the voltage polarity of magnetizing-inductor L_m changes, this stage is finished.
• Stage 5 [t₄~t₅]: The equivalent circuit is illustrated in Figure 4e. Switch S remains off. The status of diodes D₁, D₃ and D_o are on but D₂ and D₄ off. In this time interval, the energy of magnetizing-inductor L_m is dumped to ideal transformer, output terminal, and capacitor C₃ simultaneously. The secondary side of coupled inductor charges the boosting capacitor C₂ via diode D₃. At the same time, the output voltage is stacked by input voltage V_in, coupled inductor, and capacitors C₁ and C₄.
• Stage 6 [t₅~t₆]: This stage begins as C₃ stops charging. The diode D₁ becomes reversely biased. The corresponding equivalent circuit is shown in Figure 4f. The energy stored in L_m keeps dumping energy to C₂ via ideal transformer. When power switch is turned on again, this stage ends and converter operation over one switching cycle is completed.

Figure 4. Equivalent circuits of the proposed converter. (a) Stage 1; (b) Stage 2; (c) Stage 3; (d) Stage 4; (e) Stage 5; and (f) Stage 6.

Figure 4. Equivalent circuits of the proposed converter. (a) Stage 1; (b) Stage 2; (c) Stage 3; (d) Stage 4; (e) Stage 5; and (f) Stage 6.

Figure 5. Conceptual key waveforms of the proposed converter.

Figure 5. Conceptual key waveforms of the proposed converter.

3. Steady-State Analysis of the Proposed Converter

To simplify the circuit analysis, the transient state of the circuit is ignored. In addition, some assumptions are made as follows:

(1)

The values of all capacitors are large enough so that voltages across all capacitors are considered as constant;

(2)

All semiconductor components in the power circuit are ideal;

(3)

The magnetizing inductance is much greater than leakage inductance. The influence of the leakage inductance can be neglected. That is, the coupling coefficient of coupled inductor k is equal to unity;

(4)

Equivalent series resistance of coupled inductor is ignored;

(5)

The active switch is closed for DT_s and open for (1-D)T_s;

(6)

The converter is operated in CCM. According to the preceding assumptions, Figure 4b is referred while switch S closed and Figure 4e is referred while switch S open.

3.1. Derivation of Voltage Gain

To derive the voltage gain of V_o to V_in, the voltages of V_C1, V_C2, V_C3, and V_C4 have to be calculated in advance. When active switch S is turned on, referring to Figure 4b and neglecting L_k, the voltage across the secondary winding of the coupled inductor, v_L2(on), is:

$$v_{L2(on)}=n{V}_{in}$$

(1)

Therefore, the magnitudes of the voltages V_C1 and V_C4 can be expressed as:

$$V_{C1}=n{V}_{in}+V_{C3}$$

(2)

and:

$$V_{C4}=n{V}_{in}+V_{C2}$$

(3)

respectively. With respect to V_C2 and V_C3, the state of switch off is contacted and the equivalent circuit shown in Figure 4e is referred. Similarly, according to the assumptions, the leakage inductance L_k in Figure 4e is also neglected. The circuit behaviors that input voltage forwards energy to the capacitors C₂ and C₃ are similar to those of flyback and boost converters, respectively. Therefore, the voltages V_C2 and V_C3 can be expressed as:

$$V_{C2}=\frac{nD}{1-D}{V}_{in}$$

(4)

and:

$$V_{C3}=\frac{1}{1-D}{V}_{in}$$

(5)

Substituting Equations (4) and (5) into Equations (2) and (3), in turn, yields:

$$V_{C1}=\frac{1+n-nD}{1-D}{V}_{in}$$

(6)

and:

$$V_{C4}=\frac{n}{1-D}{V}_{in}$$

(7)

From Figure 4e, it can be found that the output voltage is the sum of V_in, V_C1, V_C4, and the voltages across N_p and N_s. Thus, the following relationship holds:

$$V_o=2V_{in}\left(\frac{1}{1-D}+n+\frac{nD}{1-D}\right)$$

(8)

Rearranging Equation (8), one can find the voltage gain of the proposed high step-up converter:

$$M_{CCM}=\frac{V_o}{V_{in}}=\frac{2(1+n)}{1-D}$$

(9)

To further understand the voltage gain performance of the proposed converter, Figure 6 shows the voltage gain versus duty cycle under various turns ratios n. It indicates that when the duty cycle D equals 0.5, the converter achieves an output voltage sixteen times of the input voltage under the turns ratio of 3. As compared with other high step-up converters in the literature [19,20,21], the proposed converter has a higher voltage gain than that of the conventional converters if n = 1.5, which is shown in Figure 7.

Figure 6. Illustration of voltage gain versus duty cycle under different turns ratios.

Figure 6. Illustration of voltage gain versus duty cycle under different turns ratios.

Figure 7. Voltage gain comparison among the proposed converter and conventional converters in [19,20,21].

Figure 7. Voltage gain comparison among the proposed converter and conventional converters in [19,20,21].

3.2. Voltage Stress of Power Device

Voltage stress of power devices is an important parameter for choosing power semiconductor devices. A power semiconductor device with lower voltage stress will inherently have a lower on-state resistance or forward voltage, which dominates converter efficiency. The voltage stresses across D₁, D₃ and D_o are determined as active switch is closed. On the contrary, the voltage stresses of S, D₂ and D₄ are determined as active switch is open. When the switch is in an on-state, referring to Figure 4b the voltages across D₁ and D₃ are equal to V_C3 and V_C4, respectively. Therefore, the voltage stresses V_D1,stress and V_D3,stress can be estimated as:

$$V_{D1,stress}=\frac{1}{1-D}{V}_{in}$$

(10)

and:

$$V_{D3,stress}=\frac{n}{1-D}{V}_{in}$$

(11)

Meanwhile, the output diode endures a voltage equal to V_o−V_C3 + V_C4, that is:

$$V_{Do,stress}=\frac{1+n}{1-D}{V}_{in}$$

(12)

After switch S is turned off, the voltage of diode D₂ will be clamped to V_C1−v_L2, as shown in Figure 4e. From Equation (6), the sustained voltage V_D2,stress is:

$$V_{D2,stress}=\frac{1+n}{1-D}{V}_{in}$$

(13)

In addition, during off-time interval, the blocking voltages of S and D₄ are V_C3 and V_C4, respectively, so that:

$$V_{D4,stress}=\frac{n}{1-D}{V}_{in}$$

(14)

and:

$$V_{ds,stress}=\frac{1}{1-D}{V}_{in}$$

(15)

3.3. Current on Power Devices

Since leakage inductance is neglected, the equivalent circuits of Stage 2 and Stage 5, as shown in Figure 4b,e are considered for switch on and off, respectively. Based on the amp-second balance theorem, the following relationship is suitable for any capacitor in the converter:

$$I_{C,on-state}{T}_{on-state}+I_{C,off-state}{T}_{off-state}=0$$

(16)

In Equation (16). I_C,on-state and T_on-state stand for capacitor current and time period during on-state, while I_C,off-state and T_off-state are for off-state. The ratio of output current to input current is reciprocal to that of output voltage to input voltage. From Equation (9), one can find:

$$\frac{I_o}{I_{in}}=\frac{1-D}{2(1+n)}$$

(17)

The currents of diodes D₁, D₃ and D_o can be estimated as the switch is open. Referring to Figure 4e and deriving with Equations (16) and (17), one can obtain the average current following through D₁, D₃ and D_o:

$$I_{D1}=I_{D3}=I_{Do}=\frac{1}{1-D}{I}_o=\frac{1}{2(1+n)}{I}_{in}$$

(18)

With a similar derivation procedure, while the switch is closed and Figure 4b is referred, the average currents of D₂ and D₄ can be found as:

$$I_{D2}=I_{D4}=\frac{I_o}{D}=\frac{1-D}{2(1+n)D}{I}_{in}$$

(19)

Owing to capacitors C₂ and C₃ discharging toward C₁ and C₄ during on-state interval, the average current of switch S, I_ds, is expressed as:

$$I_{ds}=I_{Lm}+(1+n)I_{D2}+n{I}_{D4}$$

(20)

Equation (20) reveals that the I_Lm has to be known in advance for the determination of I_ds. From Kirchhoff’s current law (KCL), the input current is the sum of magnetizing current and the current following through ideal transformer. That is:

$$I_{Lm}=[I_{in}-n(I_{D2}+I_{D4})]D\text{+[(}{I}_{in}+n(I_{D3}\text{+}{I}_{Do}\text{)](}1-D\text{)}=I_{in}=\frac{2(1+n)}{1-D}{I}_o$$

(21)

Substituting Equations (18), (19) and (21) into Equation (20), the average current of power switch S can be readily obtained as:

$$I_{ds}=\frac{1+2n+D}{(1-D)D}{I}_o=\frac{1+2n+D}{2(1+n)D}{I}_{in}$$

(22)

3.4. Design of Energy Storage Component

To ensure that the proposed converter can operate in CCM, the minimum magnetizing inductance has to be calculated. Over whole switch-on period, the net change in magnetizing current, Δi_Lm, can be expressed as:

$$\mathrm{\Delta }{i}_{Lm}=\frac{V_{in}}{L_m}D{T}_s$$

(23)

The boundary conduction mode (BCM) occurs when:

$$I_{Lm}-\frac{1}{2}\mathrm{\Delta }{i}_{Lm}=0$$

(24)

Substituting Equations (9), (17), (21) and (23) into Equation (24) one can then obtain the minimum value of magnetizing inductance for CCM operation, L_m,min, as follows:

$$L_{m,\min }=\frac{V_{in}}{2I_{Lm}}D{T}_s=\frac{{(1-D)}^{2}D{R}_o}{8f{(1+n)}^2}$$

(25)

Figure 8 illustrates the relationship between L_m and duty cycle under the conditions that turns ratio n = 1.5, switching frequency f_s = 100 kHz, and the load resistance R_o = 3.2 kΩ.

Figure 8. Illustrating the relationship between magnetizing inductance L_m and duty ratio D.

Figure 8. Illustrating the relationship between magnetizing inductance L_m and duty ratio D.

Even though a larger capacitance can result in a lower voltage ripple, it increases cost. Adopting an appropriate capacitance for the converter is necessary. The capacitance is found by:

$$C=\frac{\mathrm{\Delta }q}{\mathrm{\Delta }{v}_C}$$

(26)

where Δq is the change in charge and Δv_C is the accompanied voltage variation. During the time interval when S is off, capacitors C₂ and C₃ are charged by the currents of I_D3 and I_D1, respectively. Accordingly, from Equations (18) and (26), the following relationships hold:

$$C_2=\frac{I_{D3}}{\mathrm{\Delta }{v}_{C2}}(1-D)T_s=\frac{I_o{T}_s}{\mathrm{\Delta }{v}_{C2}}=\frac{I_o}{\mathrm{\Delta }{v}_{C2}f}$$

(27)

and:

$$C_3=\frac{I_{D1}}{\mathrm{\Delta }{v}_{C3}}(1-D)T_s=\frac{I_o{T}_s}{\mathrm{\Delta }{v}_{C3}}=\frac{I_o}{\mathrm{\Delta }{v}_{C3}f}$$

(28)

Opposite to the charge behavior of C₂ and C₃, both capacitors C₁ and C₄ discharge with the current I_DO. Also, one can find C₁ and C₄ from Equations (18) and (26) with the same procedure as for C₂ and C₃, and then have:

$$C_1=\frac{I_{Do}}{\mathrm{\Delta }{v}_{C1}}(1-D)T_s=\frac{I_o{T}_s}{\mathrm{\Delta }{v}_{C1}}=\frac{I_o}{\mathrm{\Delta }{v}_{C1}f}$$

(29)

and:

$$C_4=\frac{I_{Do}}{\mathrm{\Delta }{v}_{C4}}(1-D)T_s=\frac{I_o{T}_s}{\mathrm{\Delta }{v}_{C4}}=\frac{I_o}{\mathrm{\Delta }{v}_{C4}f}$$

(30)

With regard to C_o, the switch off interval is also considered. The magnitude of capacitor current I_Co is the difference between load current I_o and output diode current I_Do. Therefore, C_o can be computed by:

$$C_o=\frac{(I_{Do}-I_o)}{\mathrm{\Delta }{v}_{Co}}(1-D)T_s=\frac{I_{o}D{T}_s}{\mathrm{\Delta }{v}_{Co}}=\frac{I_{o}D}{\mathrm{\Delta }{v}_{Co}f}$$

(31)

3.5. Performance Comparison

Performance comparison of the proposed converter with other high step-up converters is summarized in Table 1. The proposed converter has a lower power component count. That is, it is cost-effective. In addition, higher voltage gain can be achieved. If the duty ratio is 0.5 and turns ratio is 1, the proposed converter has a voltage gain of 8 and the other two high step-up converters in [19,20,21] are 6, 7 and 5 in turn. Even though the converter can accomplish higher voltage gain, its voltage stress across power switch is the lowest. This reveals that a power switch with low on-state resistance can be adopted in the converter for power loss reduction. From Table 1, it also can be seen that the switching loss of the converter is small, because the switch voltage in off-time interval is clamped to V_C3.

Table 1. Performance comparison of the proposed converter with other high step-up converters.

High step-up converters	Converter introduced in [19]	Converter introduced in [20]	Converter introduced in [21]	Proposed converter
Voltage gain	$\frac{2+n+(n-1)D}{1-D}$	$\frac{1+2n+nD}{1-D}$	$n_2+\frac{1+(n_2+n_3)D}{1-D}$	$\frac{2(1+n)}{1-D}$
Diodes	3	6	5	5
Capacitors	3	6	5	5
windings	2	2	3	2
Voltage stress on switch	$\frac{V_o}{2+n+(n-1)D}$	$\frac{V_o}{1+2n+nD}$	$\frac{V_o}{1+n_2+n_{3}D}$	$\frac{V_o}{2(1+n)}$
Conduction loss	small	middle	small	small
Switching loss	small	middle	middle	small

Table 1. Performance comparison of the proposed converter with other high step-up converters.

High step-up converters	Converter introduced in [19]	Converter introduced in [20]	Converter introduced in [21]	Proposed converter
Voltage gain	$\frac{2+n+(n-1)D}{1-D}$	$\frac{1+2n+nD}{1-D}$	$n_2+\frac{1+(n_2+n_3)D}{1-D}$	$\frac{2(1+n)}{1-D}$
Diodes	3	6	5	5
Capacitors	3	6	5	5
windings	2	2	3	2
Voltage stress on switch	$\frac{V_o}{2+n+(n-1)D}$	$\frac{V_o}{1+2n+nD}$	$\frac{V_o}{1+n_2+n_{3}D}$	$\frac{V_o}{2(1+n)}$
Conduction loss	small	middle	small	small
Switching loss	small	middle	middle	small

4. Experimental Results

To verify the proposed converter, a prototype is built, with the specifications and parameters listed in Table 2. In the prototype, semiconductor devices will dominate circuit losses. Their details are discussed. The power MOSFET, IRFSL4615PbF, is selected to serve as active switch for controlling the current flow, of which maximum on-state resistance R_DS(on) is only 42 mΩ. BYW29E-200 is employed as diode D₁, of which the forward voltage is 0.895 V and the reverse recovery time is 25 ns. With regard to diodes D₂, D₃, D₄, and D_o, the ultrafast rectifier 8ETH03PbF is considered, which has 1.25 V forward voltage and 35 ns reverse recovery time. Figure 9a shows the measured voltage waveforms of the power switch and associated control gate signal. The switch blocks a voltage of 75 V, which meets the theoretical analysis in Section 3. Figure 9b is the diode currents of i_D2 and i_D4, while i_D0 and i_D3 are shown in Figure 9c. From Figure 9b,c it is proven that D₂ and D₄ are forward biased when the switch is closed but D₃ and D_o are forward biased while the switch is open. Figure 9e depicts the waveforms of i_D1 and the control gate signal, which illustrate that there is no reverse recovery current problem in diode D₁. Voltages across C₃ and C_o are shown in Figure 9e in which output voltage and V_C3 are kept at 400 V and 72 V, respectively. This is consistent with Equations (5) and (9). To examine the converter transient response, load changes from half load to full load and from full load to half load are carried out. Figure 9f is the corresponding measurement, from which it can be observed that the proposed converter performs fast response and can provide a constant high voltage even if under step load change. Figure 10 is the measured efficiency of the prototype. The maximum efficiency is up to 97.1% and an efficiency of 94.9% is achieved at full load.

Figure 9. Experimental results at 200 W: (a) Power switch voltage waveforms (v_gs: 10 V/div; v_ds: 50 V/div; time: 2 μs/div); (b) Diode currents i_D2 and i_D4, (v_gs: 10 V/div; i_D2: 2 A/div; i_D4: 2 A/div; time: 2 μs/div); (c) Diode currents i_D3 and i_Do, (v_gs: 10 V/div; i_D3: 2 A/div; i_Do: 2 A/div; time: 2 μs/div); (d) Diode current i_D1, (v_gs: 10 V/div; i_D1: 2 A/div; time: 2 μs/div); (e) Waveforms of V_o and V_C3, (V_o: 100 V/div; V_C3: 50 V/div; time: 2 μs/div); and (f) Step change between half load and full load, (V_o: 200 V/div; P_o: 200 W/div; I_o: 500 mA/div; time: 1 s/div).

Figure 9. Experimental results at 200 W: (a) Power switch voltage waveforms (v_gs: 10 V/div; v_ds: 50 V/div; time: 2 μs/div); (b) Diode currents i_D2 and i_D4, (v_gs: 10 V/div; i_D2: 2 A/div; i_D4: 2 A/div; time: 2 μs/div); (c) Diode currents i_D3 and i_Do, (v_gs: 10 V/div; i_D3: 2 A/div; i_Do: 2 A/div; time: 2 μs/div); (d) Diode current i_D1, (v_gs: 10 V/div; i_D1: 2 A/div; time: 2 μs/div); (e) Waveforms of V_o and V_C3, (V_o: 100 V/div; V_C3: 50 V/div; time: 2 μs/div); and (f) Step change between half load and full load, (V_o: 200 V/div; P_o: 200 W/div; I_o: 500 mA/div; time: 1 s/div).

Table 2. Specifications of the prototype.

Symbols	Values & Types
Vin (Input voltage)	36 V
Vo (Output voltage)	400 V
Po (Rated power)	200 W
fs (Switching frequency)	100 kHz
Lm (Magnetizing inductance)	55 μH
Lk (Leakage inductance)	1.03 μH
n (Transformer turns ratio)	1:1.6
C1 and C4 (Capacitance)	33 μF
C2 and C3 (Capacitance)	22 μF
Co (Capacitance)	82 μF
S (Active switch)	IRFSL4615PbF (150 V/33 A)
D1 (Diode)	BYW29E-200 (200 V/8 A)
D2, D3, D4, and Do (Diodes)	8ETH03PBF (300 V/8 A)

Table 2. Specifications of the prototype.

Symbols	Values & Types
Vin (Input voltage)	36 V
Vo (Output voltage)	400 V
Po (Rated power)	200 W
fs (Switching frequency)	100 kHz
Lm (Magnetizing inductance)	55 μH
Lk (Leakage inductance)	1.03 μH
n (Transformer turns ratio)	1:1.6
C1 and C4 (Capacitance)	33 μF
C2 and C3 (Capacitance)	22 μF
Co (Capacitance)	82 μF
S (Active switch)	IRFSL4615PbF (150 V/33 A)
D1 (Diode)	BYW29E-200 (200 V/8 A)
D2, D3, D4, and Do (Diodes)	8ETH03PBF (300 V/8 A)

Figure 10. Measured efficiency of the proposed converter.

Figure 10. Measured efficiency of the proposed converter.

5. Conclusions

This paper proposes a DC-DC high step-up converter for renewable-energy generation systems. The proposed converter can achieve higher voltage gain though it needs fewer power components. The energy stored in the leakage inductor can be recycled and the voltage power switch can be clamped to a low voltage so as to improve converter efficiency and suppress voltage spikes. Accordingly, low on-state power switches and Schottky diodes can be employed. Finally, a prototype is built to validate the converter. Practical measurements have demonstrated the feasibility and correctness of the proposed high step-up converter.