Wide Load Range Capacitor Clamped ZVZCS Half Bridge Three-Level DC-DC Converter with Two Unsymmetrical Bi-directional Switches

Abstract

This paper presents a zero-voltage and zero-current switching (ZVZCS) capacitor-clamped half bridge (HB) three-level dc-dc converter (TLDC), which is well fit for high input voltage dc-dc industrial applications. The maximum voltage stress of the primary switches is limited by the flying capacitor and input capacitors, which is very close to V_in/2. Two unsymmetrical bidirectional switches are used to replace two of the primary switches in a conventional capacitor-clamped HB TLDC, which ensure ZVZCS of the main switches in wide load range. The reverse direction MOSFETs in the unsymmetrical bidirectional switches have low on-state resistance and are controlled with soft-switching mode irrelevant to the load current. Therefore, the additional power loss can be omitted. The current of the flying capacitor is greatly reduced due to ZVZCS operation, which would result in a smaller volume flying capacitor and high system reliability. Furthermore, the current imbalance problem of the power devices is also well solved. The circuit, basic operation principles and some important technical analyses are discussed in this paper, and experimental results from a 1-kW prototype are provided to evaluate the proposed converter.

1. Introduction

Three-level (TL) dc-dc converters (TLDCs) can be widely used in plenty of existing and upcoming industrial applications, e.g., dc-dc converters for distributed power systems, micro-grids, renewable energy power systems, and electric vehicles [1,2,3,4]. The most outstanding attribute of TLDC is reduced voltage stress of the primary switches, and both dynamic and static voltages on the main switches can be confined below V_in/2 by the clamping devices, such as clamping diodes or capacitors. After diode-clamped TLDC was proposed in 1992, several good studies on this topic have been carried out, which are new topologies, wide load range soft-switching techniques, reduced volume of passive components methods, and new control strategies [5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21]. Several TLDCs were proposed in Reference [5], and most existing TLDCs are invented based on these topologies. A secondary active reset zero-voltage and zero-current switching (ZVZCS) TLDC was reported in Reference [6], wherein an extra capacitor is added to the primary side to realize a phase-shift (PS) switching scheme. In Reference [6], the extra capacitor provides a zero-voltage switching (ZVS) quasi-resonant path for the outer switches and a secondary clamping circuit is adopted to provide zero-current switching (ZCS) for the inner switches. In Reference [7], a passive snubber is series-connected with the primary coil of the transformer to generate reset voltage of the primary current, and two diodes are used to prevent a negative primary current during the free-wheeling stages. Some other new TLDCs were reported in References [8,9,10,11,12,13,14], which have different attractive characteristics. To reduce the volume of the passive filter, lots of TLDCs with TL secondary-rectified voltage waveforms were proposed. In Reference [15], a hybrid TLDC was proposed, which can generate TL secondary waveform before the output filter. A hybrid ZVZCS TLDC was proposed in Reference [16], which can achieve TL secondary rectified waveform as well as a wide soft switching load range. A ZVZCS TLDC with no primary clamping devices was proposed in Reference [17], which has a simpler primary structure. A TLDC with four switches was proposed, which has the minimum primary switches to generate a TL secondary-rectified waveform [18]. Other TLDCs with reduced volume of the output filter were reported in References [19,20]. To improve the reliability of TLDCs, some detailed analyses about current imbalanced problems of the primary components are investigated [21,22,23]. All mentioned references have made TLDCs more applicable.

Figure 1a shows a capacitor-clamped half bridge (HB)TLDC, and the four switches in Figure 1a are switched in the asymmetrical PWM (APWM) method to achieve balanced voltage on the input and flying capacitors. As depicted in Figure 1a, only one flying capacitor is parallel connected with HB cells, which would minimize the space of the circuit loop among C_in1, C_in2, and Q₁ to Q₄ in a real product. Hence, the parasitic inductance caused by this circuit loop would be small, which suppresses the voltage spike on the primary switches at turn-off instants. The voltage stress of the main switches is restricted by C_s, and this capacitor would absorb more energy stored in the parasitic inductances of the primary circuit. Therefore, all the primary switches can be well confined in the safe operation area (SOA). In addition, widely-used two-level HB power modules can be adopted in the proposed converter, which makes this topology more convenient for industrial users.

However, some drawbacks of the converter in Figure 1a should be overcome. First, as illustrated in Figure 1b, i_Q1 and i_Q2 are imbalanced due to an asymmetrical switching sequence, which causes some design obstacles for the power devices. Furthermore, with a decrease of the duty ratio, the imbalanced degree of the current distribution among Q₁ to Q₄ is more serious, which would affect the reliability of the converter. Second, the current distribution of C_in1 and C_in2 is also imbalanced, and the RMS value of i_Cin2 is clearly higher than that of i_Cin1 under a small duty ratio. High current stress leads high operation temperature, and it is well known that the life expectancy of film or an AL electrolytic capacitor is inversely proportional to the operation temperature. Therefore, the reliability of the converter would also be reduced. Third, i_p flows through C_s during the freewheeling stages, which would cause thermal problems of C_s. In addition, a large value capacitance of C_s is required to minimize the voltage ripple on it, which increases the volume of C_s. Finally, Q₁ and Q₃ cannot achieve zero-voltage switching in a wide load range due to less energy reserved in L_lk. New capacitor-clamped TLDC without the above-mentioned drawbacks is an interesting problem.

This paper proposes a novel ZVZCS capacitor-clamped HB TLDC, which overcomes all abovementioned shortcomings. In addition, all above features can be achieved with a simple switching sequence. The outline of this paper is concluded as follows. In part 1, the circuit is described, and detailed analysis about the operation principle is presented. Some technique aspects are analyzed in part 2. In part 3, experimental results are provided and analyzed, and some brief conclusions are given in the final part.

2. Circuits and Principle of Operation

Figure 2 shows the proposed ZVZCS HB TLDC, and two unsymmetrical bi-directional switches are replaced by Q₂ and Q₄ in Figure 1a. The unsymmetrical bi-directional switches can conduct a bi-directional current with the same value and sustain different bi-directional voltage. After introducing the unsymmetrical bi-directional switches, the currents of S₂ and S₄ can be controlled as a positive value, negative value or zero freely. Consequently, the converter with APWM switching scheme can also achieve ZVZCS operation. The remaining circuit is identical to that of the converter in Figure 1a, which is not described in detail.

Figure 3 shows the waveforms of the proposed converter, and identical circuits over one-half switching period are given in Figure 4. To simplify the analysis, some assumptions are given: all components have ideal characteristics; C_in1 and C_in2 are the input capacitors with a certain value, which could reset i_p properly during the operation as well as transfer energy to the load; S_k is replaced by Q_kP and Q_kR in Figure 3 and Figure 4; Δv_Cin2 = V_in/2 − v_Cin2; the current ripple of L_o is neglected, and i_Lo is represented by I_o.

Mode 1 [Figure 4a, before t₀]: Q₁ and Q_2P are on; energy is transferred from the primary side to the load; Q_2R and Q_4R are also on, D_o1 and D_o4 are conducted. v_Cin2 increases with the rate of

$$\frac{d{v}_{\mathrm{Cin}2}}{dt}=\frac{{\mathrm{I}}_{\mathrm{o}}-k_{\mathrm{T}}\left|i_{\mathrm{in}}\right|}{k_{\mathrm{T}}{\mathrm{C}}_{\mathrm{in}1}}-\frac{\left|i_{\mathrm{in}}\right|}{{\mathrm{C}}_{\mathrm{in}2}}$$

(1)

During this stage, v_p = V_in/2 − Δv_Cin2; v_re = (V_in − 2Δv_Cin2)/2k_T; i_p = I_o/k_T; i_Cin1 = I_o/k_T − |i_in|, i_Cin2 = −|i_in|; v_Q3 = v_Q4P = V_in/2. Although Q_4R is on, i_Q4R is zero owing to Q_4P is off.

Mode 2 [Figure 4b, t₀–t₁]: At t₀, Q₁ is off, and v_Q1 cannot change sharply due to C₁; v_Cin2 increases, and reaches V_Cin2max at the end of this mode. i_p = I_o/k_T, and charges C₁ and discharges C_4P through C_s. This stage continues until v_C1 = V_in/2 and v_C4P = 0. i_Cin1 = −|i_in|, i_Cin2 = −I_o/k_T − |i_in|. v_Q3 is v_Cs, which is identical to V_in/2. v_Q1 and v_Q4P are smaller than V_in/2.

Mode 3 [Figure 4c, t₁–t₃]: At t₁, D_4P conducts naturally and I_o is free-wheeled through secondary rectifier diodes. After t₁, Q_4P should be triggered on to ensure zero-voltage operation, and as proved in Figure 3, Q_4P is on with zero-voltage at t₂. Q_2R is also turned off at t₂. As D_2R conducts naturally, Q_2R can achieve zero-voltage turn-off. v_Cin2 is V_Cin2MAX, and V_Cin2MAX − V_in/2 is fully applied to L_lk to reset i_p, and i_p is

$$i_{\mathrm{p}}\left(t\right)=\frac{{\mathrm{I}}_{\mathrm{o}}}{k_{\mathrm{T}}}-\frac{{\mathrm{V}}_{\mathrm{Cin}2\mathrm{MAX}}-\frac{{\mathrm{V}}_{\mathrm{in}}}{2}}{{\mathrm{L}}_{\mathrm{lk}}}\left(t-t_1\right)$$

(2)

When i_p is zero, this mode is finished, and the time is

$${\mathrm{T}}_{31}=\frac{{\mathrm{I}}_{\mathrm{o}}{\mathrm{L}}_{\mathrm{lk}}}{k_{\mathrm{T}}\left({\mathrm{V}}_{\mathrm{Cin}2\mathrm{MAX}}-\frac{{\mathrm{V}}_{\mathrm{in}}}{2}\right)}$$

(3)

i_Cin1 is −|i_in| and i_Cin2 is −I_o/k_T − |i_in|; v_Q3 = v_Q1 = V_in/2.

Mode 4 [Figure 4d, t₃−t₄]: At t₃, i_p is zero, and i_p cannot change the conducting direction because of D_2R. After t₃, Q_2P can achieve zero-current turned off. During this mode, v_Cin2 in V_Cin2max. i_Cin1 = i_Cin2 = −|i_in|; v_Q3 = V_in/2 + Δv_Cin2, and v_Q1 = V_in/2 − Δv_Cin2.

Mode 5 [Figure 4e, t₄−t₅]: At t₅, Q_2P is turned off with ZCS. i_Cin1 = i_Cin2 = −|i_in|; v_Q1 = v_Q2 = (V_in/2 − |Δv_Cin2|)/2, and v_Q3 = V_in/2 + Δv_Cin2.

Mode 6 [Figure 4f, t₅–t₆]: At t₅, Q₃ is on, and Q₃ can achieve ZCS due to the low increasing rate of i_p; Q_2R is also turn-on with ZCS owing to Q_2P is off. Q_4P has been turned on at t₂; i_p increases linearly at the rate of

$$i_{\mathrm{p}}\left(t\right)=-\frac{{\mathrm{V}}_{\mathrm{CBLMAX}}}{{\mathrm{L}}_{\mathrm{lk}}}\left(t-t_5\right)$$

(4)

At the end of this interval, i_p is −I_o/k_T, and the interval is

$${\mathrm{T}}_{56}=\frac{{\mathrm{L}}_{\mathrm{lk}}{\mathrm{I}}_{\mathrm{o}}}{k_{\mathrm{T}}{\mathrm{V}}_{\mathrm{CBLMAX}}}$$

(5)

At t₆, i_p is −I_o/k_T. The proposed converter goes into the second half switching cycle and primarily powers the load. v_p = −V_in/2 + Δv_Cin2; v_re = −(V_in − 2Δv_Cin2)/2k_T; i_p = −I_o/k_T; i_Cin1 = −|i_in|, i_Cin2 = I_o/k_T − |i_in|.

3. Technical Analysis

3.1. Soft Switching of Q_2P and Q_4P

3.1.1. Turn-on Instants

Q_2P and Q_4P can achieve zero-voltage turn-on easily because large equivalent primary inductor can provide enough energy to discharge or charge the parasitic output capacitances of Q₁, Q₃, Q_2P and Q_4P. For example, to ensure ZVS of Q_4P, the energy stored in the output inductor and the leakage inductor of the transformer should be

$$\frac{1}{2}{\mathrm{L}}_{\mathrm{r}}{\left(\frac{{\mathrm{I}}_{\mathrm{o}}}{k_{\mathrm{T}}}\right)}^2\ge \frac{1}{2}{(\mathrm{C}}_1{+\mathrm{C}}_{4\mathrm{P}}){\left(\frac{{\mathrm{V}}_{\mathrm{in}}}{2}\right)}^2$$

(6)

where L_r is the equivalent primary inductor at this instant, and the minimum load current to achieve ZVS is

$${\mathrm{I}}_{\mathrm{o},\min }\ge \frac{{\mathrm{V}}_{\mathrm{in}}}{{2k}_{\mathrm{T}}}\sqrt{\frac{{(\mathrm{C}}_1{+\mathrm{C}}_{4\mathrm{P}})}{{\mathrm{L}}_{\mathrm{r}}}}$$

(7)

3.1.2. Turn-off Instants

Q_2P and Q_4P are triggered off after i_p is reduced to zero. Hence, Q_2P and Q_4P can ensure ZCS in a wide load range. The reset time of i_p is determined by (3), and T_reset is the minimum time delay of the driving signals of Q_2P and Q_4P. Therefore, to keep a safe zero-current turn-off, T_reset should be larger than the reset time of i_p, and C_in2 should be designed with following equation [17]

$${\mathrm{C}}_{\mathrm{in}2}\le \frac{\left({\mathrm{T}}_{\mathrm{s}}-2{\mathrm{T}}_{\mathrm{reset}}\right){\mathrm{T}}_{\mathrm{reset}}}{4{\mathrm{L}}_{\mathrm{lk}}}$$

(8)

Reduced C_in2 could cause a large value of reset voltage of i_p, which can ensure safe ZCS operation. However, it may cause high OFF voltage on D_o1 to D_o4, Q_2R, Q_4R, and Q₃. Hence, there should be a trade-off between the ZCS condition and the OFF voltages on D_o1 to D_o4, Q_2R, Q_4R, and Q₃.

3.2. Soft Switching of Q₁ and Q₃

3.2.1. Turn-on Instants

When Q₁ and Q₃ are on, i_p is still zero, and i_p cannot vary sharply due to the fact that L_lk limits the increasing rate. Consequently, Q₁ and Q₃ can obtain quasi ZCS turn-on. To reduce the switching-on loss further, low driving resistors are preferred for Q₁ and Q₃.

3.2.2. Turn-off Instants

When Q₁ and Q₃ are off, v_Q1 and v_Q3 varies with low slope because C₁ and C₃. Consequently, Q₁ and Q₃ can obtain quasi ZVS operation. To minimize the power loss further, extra output capacitors of Q₁ and Q₃ could be added.

3.3. Soft Switching of Q_2R and Q_4R

The identical circuit of Q_2R during the turn-off interval is shown in Figure 4c. As illustrated in Figure 3, D_2R is already conducted before t₂, and Q_2R is gated off at t₂. Hence, Q_2R can be switched off with zero-voltage properly. The identical circuit of Q_2R during the turn-on period is shown in Figure 4e. As depicted in Figure 3, Q_2P is already off before t₅ and Q_2R is gated on at t₅. Therefore, the turn-on power loss of Q_2R is zero. The soft switching condition of Q_4R is similar to that of Q_2R, and detailed analysis is not presented in this paper.

3.4. Voltage Balance of the Primary Capacitors

3.4.1. Input Capacitors

With identical capacitance and symmetrical circuit structure, the initial voltage of C_in1 and C_in2 is V_in/2. v_Cin1 and v_Cin2 can be stable, owing to the fact that charging and discharging currents of these capacitors are balanced over one switching period. Corresponding waveforms are given in Figure 3, and identical circuits can be referenced in Figure 4. As the positive and negative pulses of the currents flowing through C_in1 and C_in2 are balanced over one switching period, the mid-point voltage of C_in1 and C_in2 can be stable over one switching period.

3.4.2. Flying Capacitors

The initial voltage of C_s is also V_in/2 due to symmetrical circuit structure, and v_Cs can be stable owing to the fact that charging and discharging currents of C_s are balanced over one switching period. Corresponding waveforms are given in Figure 3, and identical circuits can be referenced in Figure 4. The positive and negative pulses of the current flowing through C_s are balanced over one switching period. Hence, C_s can achieve stable voltage over one switching cycle.

3.5. Current Stress of the Primary Component

3.5.1. S₂ and S₄

The average value of i_S2 and i_S4 is

$${\mathrm{I}}_{\mathrm{AVG}\_S_{2,4}}=\frac{{\mathrm{I}}_{\mathrm{o}}}{k_{\mathrm{T}}}\left(\frac{D}{2}-\frac{1}{2}\frac{{\mathrm{T}}_{31}}{{\mathrm{T}}_{\mathrm{s}}}\right)$$

(9)

The RMS value of i_S2 and i_S4 is

$${\mathrm{I}}_{RMS\_S_{2,4}}\approx \sqrt{\frac{1}{{\mathrm{T}}_s}{\displaystyle {{\displaystyle \int }}_0^{D\raisebox{1ex}{${\mathrm{T}}_s$}\!\left/ \!\raisebox{-1ex}{$2$}\right.}}{\left(\frac{{\mathrm{I}}_{\mathrm{o}}}{k_{\mathrm{T}}}\right)}^{2}dt+\frac{1}{{\mathrm{T}}_s}{\displaystyle {{\displaystyle \int }}_0^{{\mathrm{T}}_{31}}}{\left(\frac{{\mathrm{I}}_{\mathrm{o}}}{{\mathrm{T}}_{31}{k}_{\mathrm{T}}}\right)}^2{t}^{2}dt}=\frac{{\mathrm{I}}_{\mathrm{o}}}{k_{\mathrm{T}}}\sqrt{\frac{D}{2}+\frac{{\mathrm{T}}_{31}}{3{\mathrm{T}}_s}}$$

(10)

3.5.2. Q₁ and Q₃

The average value of i_Q1 and i_Q3 is

$${\mathrm{I}}_{\mathrm{AVG}\_Q_{1,3}}\approx \frac{{\mathrm{I}}_{\mathrm{o}}}{k_{\mathrm{T}}}\frac{D}{2}$$

(11)

The RMS value of i_Q1 and i_Q3 is

$${\mathrm{I}}_{RMS\_Q_{1,3}}\approx \sqrt{\frac{1}{{\mathrm{T}}_s}{{\displaystyle \int }}_0^{D\raisebox{1ex}{${\mathrm{T}}_s$}\!\left/ \!\raisebox{-1ex}{$2$}\right.}{\left(\frac{{\mathrm{I}}_{\mathrm{o}}}{k_{\mathrm{T}}}\right)}^{2}dt}=\frac{{\mathrm{I}}_{\mathrm{o}}}{k_{\mathrm{T}}}\sqrt{\frac{D}{2}}$$

(12)

3.5.3. C_in1

The average current of i_Cin1 is zero. The time integral of the positive pulse of i_Cin1 is

$${\mathrm{I}}_{pos\_C_{\mathrm{in}1}}=\underset{0}{\overset{\raisebox{1ex}{$D{\mathrm{T}}_s$}\!\left/ \!\raisebox{-1ex}{$2$}\right.}{{\displaystyle \int }}}\left(\frac{{\mathrm{I}}_{\mathrm{o}}}{k_{\mathrm{T}}}-\left|i_{\mathrm{in}}\right|\right)dt=\left(\frac{{\mathrm{I}}_{\mathrm{o}}}{k_{\mathrm{T}}}-\left|i_{\mathrm{in}}\right|\right)\frac{D{\mathrm{T}}_s}{2}$$

(13)

The time integral of the negative pulse of i_Cin1 is

$${\mathrm{I}}_{neg\_C_{\mathrm{in}1}}={{\displaystyle \int }}_{\raisebox{1ex}{$D{\mathrm{T}}_s$}\!\left/ \!\raisebox{-1ex}{$2$}\right.}^{{\mathrm{T}}_s}\left|i_{\mathrm{in}}\right|dt=\left|i_{\mathrm{in}}\right|\left(2-D\right)\frac{{\mathrm{T}}_s}{2}$$

(14)

To keep charge balance over one switching cycle, the average current of i_Cin1 is zero. Hence, |i_in| can be computed as

$$\left|i_{\mathrm{in}}\right|=\frac{{\mathrm{I}}_{\mathrm{o}}}{k_{\mathrm{T}}}\frac{D}{2}$$

(15)

The RMS value of i_Cin1 is

$${\mathrm{I}}_{RMS\_C_{\mathrm{in}1}}\approx \sqrt{\frac{1}{{\mathrm{T}}_s}{{\displaystyle \int }}_0^{\raisebox{1ex}{$D{\mathrm{T}}_s$}\!\left/ \!\raisebox{-1ex}{$2$}\right.}{\left(\frac{{\mathrm{I}}_{\mathrm{o}}}{k_{\mathrm{T}}}\right)}^2{\left(1-\frac{D}{2}\right)}^{2}dt+\frac{1}{{\mathrm{T}}_s}{{\displaystyle \int }}_{\raisebox{1ex}{$D{\mathrm{T}}_s$}\!\left/ \!\raisebox{-1ex}{$2$}\right.}^{{\mathrm{T}}_s}{\left(\frac{{\mathrm{I}}_{\mathrm{o}}}{k_{\mathrm{T}}}\right)}^2{\left(\frac{D}{2}\right)}^{2}dt}=\frac{{\mathrm{I}}_{\mathrm{o}}}{k_{\mathrm{T}}}\sqrt{\frac{D}{2}-\frac{D^2}{4}}$$

(16)

3.5.4. C_in2

The average current of i_Cin2 is zero. The RMS value of i_Cin2 can be computed according to Figure 3

$${\mathrm{I}}_{RMS\_C_{\mathrm{in}2}}\approx \frac{{\mathrm{I}}_{\mathrm{o}}}{k_{\mathrm{T}}}\sqrt{\frac{D}{2}-\frac{D^2}{4}+\frac{2{\mathrm{T}}_{31}}{3{\mathrm{T}}_s}}$$

(17)

3.5.5. C_s

The average current of i_Cs is zero. The RMS value of i_Cs can be computed according to Figure 3

$${\mathrm{I}}_{RMS\_C_s}\approx \frac{{\mathrm{I}}_{\mathrm{o}}}{k_{\mathrm{T}}}\sqrt{\frac{2{\mathrm{T}}_{31}}{3{\mathrm{T}}_s}}$$

(18)

3.6. Comparison with the Conventional Capacitor Clamped TL dc-dc Converter

3.6.1. Main Switches

As illustrated in Figure 5a, the current difference between Q₁ and Q₂ of the converter in Figure 1a is inversely proportional to the duty ratio D, and when D = 0.3, the current of Q₂ would be twice that of Q₁. Hence, the current distribution of the main switches of the converter in Figure 1a is imbalanced. Consequently, the current rating of Q₂ and Q₄ is much higher than that of Q₁ and Q₂. However, in the proposed converter, the primary switches have balanced and reduced current. As shown in Figure 5c, the current difference between i_Q1 and i_Q2P is around 0.01 per unit, which is mainly caused by the negative current pulse of i_Q2P. However, the RMS value of the negative pulse can be neglected due to the fact that the time of this pulse is very short. As the primary free-wheeling current is reset to zero, the current stress on the main switches in the proposed converter is also reduced. The maximum value of the off-voltage stress on Q₃ is V_in/2 + Δv_Cin2, which is slightly higher than that of the converter in Figure 1a. However, as Δv_Cin2 is usually small, which is not exceed 30 V. Hence, the increasing voltage stress on Q₃ can still be accepted.

3.6.2. Primary Capacitors

As illustrated in Figure 5b, the current difference between C_in1 and C_in2 of the converter in Figure 1a is varied with the duty ratio D, and when D = 0.3, the current of C_in2 would be twice that of C_in1. Hence, the current distribution of the input capacitors of the converter in Figure 1a is imbalanced. Furthermore, the current rating of C_in2 is much higher than that of C_in1. However, in the proposed converter, the input capacitors have balanced and reduced current. As shown in Figure 5d, the current difference between i_Cin1 and i_Cin2 is around 0.01 per unit, which is mainly caused by the current pulses during switching instants. However, the RMS value of these pulses can also be neglected due to fact that the times are very short. As i_p during the free-wheeling stages is zero, the RMS value of i_Cin1 and i_Cin2 in the proposed converter is also reduced. The current comparison of C_s is provided in Figure 5e, and the RMS value of i_Cs in the proposed converter is obviously lower than C_s in Figure 1. Hence, the required value of C_s in the proposed converter is much lower than C_s in Figure 1, which results in reduced volume of this capacitor.

3.6.3. Soft Switching Load Range

As proven in

Table 1. Soft switching of the main switches.

Item	Q1	Q2	Q3	Q4
Proposed	ZCZVS, easy	ZVZCS, easy	ZCZVS, easy	ZVZCS, easy
Figure 1a	ZVS, hard	ZVS, easy	ZVS, hard	ZVS, easy

, the ZVS load range of Q₁ and Q₃ in Figure 1a is narrow owing to the fact that only low energy kept in L_lk can be used to discharge or charge C₁, C₃, C_2p, and C_4p, which would lead to poor efficiency under light load condition. Hence, C₁, C₃, C_2p, and C_4p in Figure 1a should be small to ensure ZVS operation of Q₁ and Q₃. However, a large value of C₁, C₃, C_2p, and C_4p is better for minimizing turn-off power loss of Q₁ and Q₃. Hence, the switching-off power loss of Q₁ to Q₃ in Figure 1a cannot be optimized.

As depicted in Figure 2, Figure 3 and Figure 4, Q_2P and Q_4P in the proposed converter are turned-on with zero-voltage and off with zero-current; while, Q₁ and Q₃ are on with quasi-ZCS mode and off with quasi-ZVS mode. Hence, the soft-switching conditions of the primary switches in the proposed converter are not interconnected, and the switching-off power loss of Q₁ and Q₃ can be reduced without increasing the switching-on power loss.

3.7. Brief Comparison with Other Typical HB TLDCs

To evaluate the proposed converter further, some brief comparison is carried out in this part. The components comparison is shown in

Table 2. Components comparison.

Converter	Power Devices High Voltage	Power Devices Low Voltage	Capacitors Large Value	Capacitors Small Value
Proposed	4	2	0	3
[1]	6	0	2	0
[6]	6	1	2	1
[7]	6	2	2	2

. Compared with classical HB TLDCs, the power devices with high voltage rating of the proposed converter are less than other converters. As allowed voltage ripple on the input capacitors is large, C_in1 and C_in2 in the proposed converter are small, which means reduced system volume and BOM cost. In Reference [7], an extra capacitor is required to generate the reset voltage of i_p, and the number of capacitors of the converter in Reference [7] is highest.

The performance comparison is depicted in

Table 3. Performance comparison.

Converter	Soft Switching Primary Switches	Soft Switching Extra Power Devices	Current Stress Primary Components	Duty Ratio Loss
Proposed	Good	Good	Small (even)	Small
[1]	Worse	NA	Large (uneven)	Large
[6]	Medium	Worse	Small (even)	Small
[7]	Medium	Good	Small (even)	Small

. As two of the primary switches cannot ensure safe ZVS operation under light output current, the converter in Reference [1] has the worst soft-switching characteristics. As the switching-on power loss and switching-off power loss can be optimized at the same time, the proposed converter has the best soft switching characteristics among the four converters. The extra power devices in Reference [6] are operated in hard switching mode, which will reduce the efficiency. As i_p is reduced to zero in the free-wheeling stages, the proposed converter and the converters in References [6,7] have small duty ratio loss. In addition, the current stress of the primary components is large and uneven in the converter [1], owing to similar reasons as the converter in Figure 1a.

4. Experimental Results

The operation principle and characteristics of the proposed converter are proved by a 1–kW experimental equipment, and some specifications of the experimental equipment are listed in

Table 4. Specifications of the experimental equipment.

Item	Parameter
Vin	400 V–600 V
Rated Vo	200 V
Rated Io	5 A
fs	100 kHz
Q1, Q3, Q2p and Q4p	20 A/600 V
Q2R, Q4R	20 A/25 V
Do1 to Do4	20 A/600 V
kT	1:1.15
Cin1, Cin2	200 μF
Cs	1.5 μF
Lo	20 μH/5 A
Co	200 μF

. Figure 6, Figure 7, Figure 8 , Figure 9, Figure 10, Figure 11 and Figure 12 show the experimental results.

Figure 6 gives the primary voltage of the transformer, and v_p changes with the same rate with v_Cin1 and v_Cin2 during the power-transferring stages. At the beginning of the free-wheeling stages, v_p provides enough and constant reset voltage of i_p. As provided in Figure 7, i_p remains as zero during the free-wheeling stages, which ensures zero-current turn-off of Q_2p and Q_4P. In addition, the primary circulating current is nearly zero, which reduces the conduction loss. As proved in Figure 8, C_in2 is charged or discharged by i_p during power-transfer stages, hence, v_Cin2 varies within the boundary of Δv_Cin2 linearly with time. During free-wheeling stages, v_Cin2 is unchanged, owing to i_p remaining as zero. As shown in Figure 9, v_Do1 is also changed with the slope of v_p/k_T, and the voltage stress of v_Do1 is increased.

The soft-switching characteristic of Q_2P is proved in Figure 10, and it is clear that Q_2P can achieve ZVZCS. Before the switch-on instant, i_Q2P conducts in the reverse direction owing to the fact that D_2P is already on, hence, Q_2p is switched on with zero-voltage. Before the switching-off signal of Q_2P is coming, i_2P reduces to zero. Therefore, Q_2P can achieve ZCS turn-off properly.

v_Q3, i_Q3 and v_GSQ3 are depicted in Figure 11, which proves Q₃ is operated in ZCZVS. At the time of switching-on, i_Q3 cannot change sharply owing to the fact that L_lk limits the changing rate of i_p, thus, Q₃ is switched with quasi-ZCS mode. At the time of switching-off, v_Q3 cannot change sharply owing to the fact that C₃ limits the changing rate; therefore, the switching-off power loss of Q₃ is also small. It should be pointed out that a large value of C₃ would not take great effect on ZVS turn-on of Q₃, which means both the turn-on and turn-off switching loss of Q_2P and Q₃ can be optimum. As proved in Figure 10 and Figure 11, the voltage stress of Q₃ and Q_2P is confined close to V_in/2.

The efficiency comparison results are illustrated in Figure 12. In Figure 12a, the proposed converter has high efficiency under low output current condition owing to reduced switching power loss of the primary switches. Under high output current conditions, the efficiency of the proposed converter is also better due to the fact that switching-off power loss can be further reduced. In Figure 12b, when I_o is constant, the efficiency of both converters is changed inversely proportional to V_in. In addition, the efficiency of the proposed converter is decreased slowly owing to the fact that V_in has a small effect on the soft switching condition of the primary switches.

5. Conclusions

A new ZVZCS capacitor-clamped HB TLDC with two unsymmetrical bidirectional switches is proposed and analyzed, and the experimental results can well support the theoretical analysis. After discussion, some obvious advantages of the proposed converter can be concluded, e.g., balanced and reduced current stress of the primary components, small and reduced volume of the clamping capacitor, wide load range soft-switching operation for both turn-on and turn-off instants and a simple switching scheme. The only drawback of the proposed converter is the off voltage of Q₃ is slightly higher than V_in/2.