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Energies 2017, 10(2), 233; doi:10.3390/en10020233

Evaluation and Reliability Assessment of GaN-on-Si MIS-HEMT for Power Switching Applications

1
Department of Mechanical Engineering, National Chiao-Tung University, No. 1001, University Road, Hsinchu 30010, Taiwan
2
Department of Materials Science and Engineering, National Chiao-Tung University, No. 1001, University Road, Hsinchu 30010, Taiwan
3
Microsystems Technology Laboratories, Massachusetts Institute of Technology, Cambridge, MA 02139, USA
*
Author to whom correspondence should be addressed.
Academic Editors: Alberto Castellazzi and Andrea Irace
Received: 6 December 2016 / Revised: 20 January 2017 / Accepted: 8 February 2017 / Published: 16 February 2017
(This article belongs to the Special Issue Semiconductor Power Devices)
View Full-Text   |   Download PDF [2939 KB, uploaded 16 February 2017]   |  

Abstract

This paper reports an extensive analysis of the physical mechanisms responsible for the failure of GaN-based metal–insulator–semiconductor (MIS) high electron mobility transistors (HEMTs). When stressed under high applied electric fields, the traps at the dielectric/III-N barrier interface and inside the III-N barrier cause an increase in dynamic on-resistance and a shift of threshold voltage, which might affect the long term stability of these devices. More detailed investigations are needed to identify epitaxy- or process-related degradation mechanisms and to understand their impact on electrical properties. The present paper proposes a suitable methodology to characterize the degradation and failure mechanisms of GaN MIS-HEMTs subjected to stress under various off-state conditions. There are three major stress conditions that include: VDS = 0 V, off, and off (cascode-connection) states. Changes of direct current (DC) figures of merit in voltage step-stress experiments are measured, statistics are studied, and correlations are investigated. Hot electron stress produces permanent change which can be attributed to charge trapping phenomena and the generation of deep levels or interface states. The simultaneous generation of interface (and/or bulk) and buffer traps can account for the observed degradation modes and mechanisms. These findings provide several critical characteristics to evaluate the electrical reliability of GaN MIS-HEMTs which are borne out by step-stress experiments. View Full-Text
Keywords: DC stress; degradation; GaN HEMT; GaN MIS-HEMT; reliability; failure mechanisms; trapping DC stress; degradation; GaN HEMT; GaN MIS-HEMT; reliability; failure mechanisms; trapping
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This is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. (CC BY 4.0).

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MDPI and ACS Style

Chou, P.-C.; Chen, S.-H.; Hsieh, T.-E.; Cheng, S.; del Alamo, J.A.; Chang, E.Y. Evaluation and Reliability Assessment of GaN-on-Si MIS-HEMT for Power Switching Applications. Energies 2017, 10, 233.

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