In recent R&D efforts on CMOS image sensors (CIS), there have been many attempts to reduce pixel size for higher image resolution and/or higher density of integration. One obvious way to do this is to minimize the number of in-pixel transistors. This has led to architectural explorations instead of accepting 3 T and 4 T pixel structures as standard. Sharing pixel transistors has been proposed [1-3] and proved to be an effectively approach: it allows the number of transistors per pixel to be reduced to 2.5 T, 1.75 T, or 1.5 T. On the other hand, a more ambitious approach aims at ultimate achievement: single component for the pixel. There have been suggestions of specific transistor structures as single pixel component working on the charge-modulation principle [4-6]. However, to meet system integration requirements, the structure of the pixel transistor should be simple, compact, and integrable with minimum extra fabrication process steps.

This paper presents a 1T pixel using a floating-body MOSFET. Instead of employing a photodiode (PD), the transistor is also operated as photo-sensing device, with its floating body to collect and store charges during integration. For signal readout, the transistor is operated as source follower. Finally for reset operation, the stored charges can be evacuated by bias control. We describe this 1T pixel structure and its operating principle in the following section (Section 2). Our studies include device modeling and model validation (in Section 3), pixel implementation (in Section 4), as well as characterization. The evaluated performances are presented in Section 5.

The proposed 1T pixel consists of an n-type MOSFET. Alternatively a p-type MOSFET may also be used. However, n-type transistor pixel operates with collection and storage of photo-generated holes rather than electrons, which is a better choice to reduce electrical crosstalk, because holes have much lower mobility than electrons.

The transistor structure differs from the conventional one mainly in that floating P-well with controlled doping profile is employed. It is also used as photo-sensing element of the pixel. At the same time, under different bias conditions, this same transistor can be operated to perform integration, readout and reset.

In the integration phase, a low voltage level is applied to the gate of the transistor to turn it off. The floating body of the transistor exhibits a potential valley for collecting and storing holes (red curve in Figure 1). The pixel being under illumination, light penetrates through the gate and is absorbed in the transistor body. There is separation of photo-generated electron-hole pairs due to built-in electrical field in the body. The electrons are swept away mainly to the V_dd-connected drain, while the holes are collected and accumulated in the potential valley. The stored holes raise the potential of the transistor body, which leads to a decrease of the transistor threshold voltage V_tn [6].

In the readout phase, the transistor is switched on by applying a gate voltage higher than the maximum V_tn corresponding to the dark conditions. The potential valley becomes shallower with shrink of charge-storage region under the transistor gate (green curve in Figure 1). The transistor in this phase is operated as a source follower with fixed gate and drain voltages. The decrease of V_tn reflecting the amount of the stored charge is sensed as an increase of the transistor's effective gate-source voltage. Accordingly, the drain current and the output source voltage increase. The source voltage in this period can be readout by sampling.

For the reset of the pixel, a still higher voltage is applied to the transistor gate. At the same time, the source voltage is clamped to the drain voltage to minimize channel current. The potential valley disappears and the stored holes are pushed away to the substrate because the transistor body potential near the silicon surface is so substantially increased that the potential becomes monotonic decreasing (blue curve in Figure 1).

The operation of the 1T pixel can be verified by simulations using ISE TCAD tools, as is shown in Figure 2. The biasing conditions of the transistor are indicated in Table 1.

One feature of this 1T pixel is its reset mode with depletion of the storage zone does not generate kTC noise. Thus there is no need to employ CDS (correlated double sampling). Instead, rapid simple non-correlated double sampling is suggested (see Figure 3) to suppress V_tn dispersion and thus to reduce FPN (fixed pattern noise). It is more efficient in reducing low-frequency noise.

One should notice that in readout mode, some stored holes are displaced under the source due to shrink of charge storage region under the gate and source potential lowering. This shift of the charge storage region to the source and toward the pixel edge should be stopped to avoid electrical crosstalk. One solution to the problem is to employ STI (shallow trench isolation), as shown in Figure 2. It was adopted in our first design configuration.

Conventional design of the 1T pixel is the rectangular-gate configuration, as shown in Figure 6a. Implementing the 1T pixel in rectangular-gate configuration has minimized transistor size. However as already mentioned, to avoid electrical crosstalk we should employ STI. This solution unavoidably increases pixel size. Moreover, it also increase significantly the pixel dark current, because of increased silicon surface depletion areas, where dark-current generation is a major contribution [12].

Another way of designing 1T pixel is a ring-gate configuration, with source at the center and peripheral drain (shown in Figure 8a). This time the readout-induced shift of the charge-storage region goes to the pixel center, which does not raise crosstalk problems. Thus there is no need to employ STI. The floating body of the transistor is shielded by a deep buried N-type layer and N peripheral region below the drain (see Figure 8b). The surrounding drain and the non-depleted N-peripheral region underneath in the peripheral pixel area also play the role of pixel isolation. This STI suppression allows not only smaller pixel size and/or fill-factor improvement, but also substantial reduction of surface dark current component.

At the fabrication process level, we have implemented several configurations on test chips with variations of parameters, with the aim of both model validation (subsection 3.3.) and optimization of pixel characteristics. This includes: -

increasing gate-oxide thickness to enhance CG;

As gate-oxide nitridation may induce much more interface traps, a higher level of low-frequency noise in the MOS transistor is predicted. The interface-trap-related noise includes RTS (Random Telegraph Signal) noise and 1/f noise due to both carrier-trap (ΔN) and charge-scattering (Δμ) effects [13-15]. The low-frequency noise is becoming an important issue for CMOS image sensors (CIS) as the size of transistor components continues to shrink [16]. It may have dominant contribution to pixel read noise, and thus should be taken into account in the choice of oxidation parameters.

It should be mentioned that stored holes in the pixel transistor's floating body will not communicate with interface traps, and that the main noise effect of these traps is resulting fluctuations of the transistor drain current when it is in readout mode.

Measurements of test chips have been made to estimate impacts of oxidation process parameters on CG (shown in Figure 7) and on temporal noise. Temporal noise of the pixel structure has been evaluated by measuring its output fluctuations in dark conditions with short integration duration, so as to neglect dark-current-contributed shot noise. The measured results shown in Table 3 confirm noise lowering with the increase of t_ox, because increasing t_ox will enhance CG, and thus lead to lower equivalent noise. On the other hand, the observed difference of noise levels between oxidation with and without nitridation indicates that interface-trap-induced noise is a main temporal noise source.

Figure 9 shows two photo-conversion transfer characteristic curves, corresponding to a 2.2 μm-pitch rectangular-gate pixel and a 1.4 μm-pitch ring-gate pixel respectively. From the photoelectric conversion characteristic curve V_pix(I_in), several performance aspects can be evaluated: the first portion of the curve before saturation determines the sensitivity and the linearity, while the saturation level indicates the full-well capacity (FWC).

The sensitivity corresponds to the slope of the curve divided by the integration time t_int: (9) S = 1 t int Δ V pix Δ I in

It can be shown to be geometry-dependent, and proportional to the pixel's sensing surface area as well as its conversion gain. Table 4 presents measured sensitivity of different design configurations. The obtained results show that: -

pixel shrink will lead to rapid degradation of sensitivity;

Table 5 compares characteristics of two fabricated CIS test chips, one integrating an array of 2.2 μm-pitch rectangular-gate pixels [17], and the other an array of 1.4μm-pitch ring-gate pixels [18]. The pixel fabrication process requires only three extra masks for specific implants and is fully compatible with the CMOS digital process.

The 1.4 μm-pitch ring-gate pixel has improved characteristics compared to its 2.2 μm-pitch rectangular-gate counterpart: -

smaller size for a comparable fill factor, mainly because STI is not employed;

The 1.4μm-pitch pixel has also degraded performances: -

lower FWC, because of smaller size and ring shape of the charge-storage region [19];

The above comparison between the two design configurations shows that some performance aspects can substantially be enhanced by the use of appropriate design techniques. It is, however, a challenging task to preserve and/or improve FWC and sensitivity when reducing pixel size. Methods of improvements include optimization of process and bias parameters. Figure 10 presents two examples of quantum-efficiency (QE) improvement: employing thinner Poly-Si gate to reduce short-wavelength absorption loss (Figure 10a), and enlarging charge-colleting region by implant optimization (Figure 10b).

FWC of the 1T pixel may be improved by lowering V_tn of the transistor via shallow channel implant, so as to widen the gate-bias-voltage difference between reset and readout modes (i.e. V G Rst − V G Rd). As can be seen from Figure 1, V G Rd should be low enough for obtaining a potential valley with a certain depth, and V G Rst should be high enough to sweep away completely stored holes. Decreasing V_tn leads to the decrease of V G Rd, which means an increase of the term ( V G Rst − V G Rd). Another way of increasing the term ( V G Rst − V G Rd) is to consider possible higher supply voltages (for the thick-gate-oxide pixel). It should be noted that rectangular-gate configuration cannot benefit from this supply-voltage relaxation because of early appearance of band-to-band tunneling effect [17]. Ring-gate configuration, on the other hand, seems to withstand a higher supply voltage without sharp increase of dark current.

Via implant control, the potential profile of the pixel transistor can be optimized to increase the depth of the potential valley in readout mode, but this will also increase difficulties to ensure complete evacuation of stored holes in reset phase. It should be mentioned that V_G is not the only controlling voltage: the perimeter of the charge-storage region depends on the transistor bias voltages V_S, V_G and V_D. Especially V_S has a more efficient control than V_G, with: (10) ∂ W j B ′ S / ∂ V S Rst > > ∂ X dep / ∂ V G Rst

Thus, combining optimization of bias and implant parameters may be an effective approach for FWC improvement.

We have proposed a floating-body MOSFET as a single pixel component. It can be operated as photo-sensing device and source-follower transistor, with charge storage and charge evacuation via bias control. Our investigation into this 1T pixel structure includes modeling and model validation, implementation and characterization.

The pixel structure has been modeled by establishing an equivalent circuit, which allows analytical description of the pixel's linear conversion characteristics. The relationship of the conversion gain with key parameters has thus been determined. The involved parameters have also been modeled and integrated in the device model to allow parametrical analysis. Model validation has been done by comparing theoretical predictions and experimental results.

The proposed pixel structure has been designed in rectangular-gate and ring-gate configurations. Due to stored charges moving toward the transistor's source, the former requires the use of STI to avoid electrical crosstalk, while the latter with the transistor's source at the pixel center suppresses this need. The implemented configurations on test chips include variations of oxidation process parameters for model validation and performance optimization.

The obtained results confirm that reducing pixel size improves conversion gain, but degrades full well capacity. Ring-gate pixel design has much lower dark current than the rectangular-gate counterpart, mainly thanks to STI suppression and smooth-shape layout. Moreover, the ring-gate pixel has lower noise and much lower dark FPN. Dark FPN may largely be contributed by dark current. The dynamic range for the ring-gate pixel is larger, meaning that signal-to-noise ratio outweighs FWC degradation. However, the sensitivity, like FWC, is also degraded in the same proportion. Possible improvements of performances include optimization of process and bias parameters.