Development of Gated Pinned Avalanche Photodiode Pixels for High-Speed Low-Light Imaging
AbstractThis work explores the benefits of linear-mode avalanche photodiodes (APDs) in high-speed CMOS imaging as compared to different approaches present in literature. Analysis of APDs biased below their breakdown voltage employed in single-photon counting mode is also discussed, showing a potentially interesting alternative to existing Geiger-mode APDs. An overview of the recently presented gated pinned avalanche photodiode pixel concept is provided, as well as the first experimental results on a 8 × 16 pixel test array. Full feasibility of the proposed pixel concept is not demonstrated; however, informative data is obtained from the sensor operating under −32 V substrate bias and clearly exhibiting wavelength-dependent gain in frontside illumination. The readout of the chip designed in standard 130 nm CMOS technology shows no dependence on the high-voltage bias. Readout noise level of 15
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Resetar, T.; De Munck, K.; Haspeslagh, L.; Rosmeulen, M.; Süss, A.; Puers, R.; Van Hoof, C. Development of Gated Pinned Avalanche Photodiode Pixels for High-Speed Low-Light Imaging. Sensors 2016, 16, 1294.
Resetar T, De Munck K, Haspeslagh L, Rosmeulen M, Süss A, Puers R, Van Hoof C. Development of Gated Pinned Avalanche Photodiode Pixels for High-Speed Low-Light Imaging. Sensors. 2016; 16(8):1294.Chicago/Turabian Style
Resetar, Tomislav; De Munck, Koen; Haspeslagh, Luc; Rosmeulen, Maarten; Süss, Andreas; Puers, Robert; Van Hoof, Chris. 2016. "Development of Gated Pinned Avalanche Photodiode Pixels for High-Speed Low-Light Imaging." Sensors 16, no. 8: 1294.
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