Next Article in Journal
Distance-Dependent Multimodal Image Registration for Agriculture Tasks
Previous Article in Journal
Towards a Low-Cost Remote Memory Attestation for the Smart Grid
Article Menu

Export Article

Open AccessArticle
Sensors 2015, 15(8), 20825-20844; doi:10.3390/s150820825

Efficient Implementation of a Symbol Timing Estimator for Broadband PLC

Electronics Department, University of Alcalá, Campus Universitario s/n, Alcalá de Henares, Madrid 28805, Spain
These authors contributed equally to this work.
*
Author to whom correspondence should be addressed.
Academic Editor: Vittorio M. N. Passaro
Received: 26 June 2015 / Revised: 27 July 2015 / Accepted: 14 August 2015 / Published: 21 August 2015
(This article belongs to the Section Physical Sensors)
View Full-Text   |   Download PDF [1718 KB, uploaded 21 August 2015]   |  

Abstract

Broadband Power Line Communications (PLC) have taken advantage of the research advances in multi-carrier modulations to mitigate frequency selective fading, and their adoption opens up a myriad of applications in the field of sensory and automation systems, multimedia connectivity or smart spaces. Nonetheless, the use of these multi-carrier modulations, such as Wavelet-OFDM, requires a highly accurate symbol timing estimation for reliably recovering of transmitted data. Furthermore, the PLC channel presents some particularities that prevent the direct use of previous synchronization algorithms proposed in wireless communication systems. Therefore more research effort should be involved in the design and implementation of novel and robust synchronization algorithms for PLC, thus enabling real-time synchronization. This paper proposes a symbol timing estimator for broadband PLC based on cross-correlation with multilevel complementary sequences or Zadoff-Chu sequences and its efficient implementation in a FPGA; the obtained results show a 90% of success rate in symbol timing estimation for a certain PLC channel model and a reduced resource consumption for its implementation in a Xilinx Kyntex FPGA. View Full-Text
Keywords: Power-Line Communications; symbol timing estimation; complementary sequences; Zadoff-Chu sequences; FPGA-based architecture Power-Line Communications; symbol timing estimation; complementary sequences; Zadoff-Chu sequences; FPGA-based architecture
This is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. (CC BY 4.0).

Scifeed alert for new publications

Never miss any articles matching your research from any publisher
  • Get alerts for new papers matching your research
  • Find out the new papers from selected authors
  • Updated daily for 49'000+ journals and 6000+ publishers
  • Define your Scifeed now

SciFeed Share & Cite This Article

MDPI and ACS Style

Nombela, F.; García, E.; Mateos, R.; Hernández, Á. Efficient Implementation of a Symbol Timing Estimator for Broadband PLC. Sensors 2015, 15, 20825-20844.

Show more citation formats Show less citations formats

Related Articles

Article Metrics

Article Access Statistics

1

Comments

[Return to top]
Sensors EISSN 1424-8220 Published by MDPI AG, Basel, Switzerland RSS E-Mail Table of Contents Alert
Back to Top