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Digital Pixel Sensor Array with Logarithmic Delta-Sigma Architecture
Department of Electrical and Computer Engineering, University of Alberta, 9107 116 Street NW, Edmonton, AB T6G 2V4, Canada
* Author to whom correspondence should be addressed.
Received: 29 May 2013; in revised form: 27 July 2013 / Accepted: 6 August 2013 / Published: 16 August 2013
Abstract: Like the human eye, logarithmic image sensors achieve wide dynamic range easily at video rates, but, unlike the human eye, they suffer from low peak signal-to-noise-and-distortion ratios (PSNDRs). To improve the PSNDR, we propose integrating a delta-sigma analog-to-digital converter (ADC) in each pixel. An image sensor employing this architecture is designed, built and tested in 0.18 micron complementary metal-oxide-semiconductor (CMOS) technology. It achieves a PSNDR better than state-of-the-art logarithmic sensors and comparable to the human eye. As the approach concerns an array of many ADCs, we use a small-area low-power delta-sigma design. For scalability, each pixel has its own decimator. The prototype is compared to a variety of other image sensors, linear and nonlinear, from industry and academia.
Keywords: CMOS image sensors; dynamic range; digital pixel sensors; nonlinear response; signal-to-noise ratio; analog-to-digital conversion; delta-sigma modulation; decimation
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MDPI and ACS Style
Mahmoodi, A.; Li, J.; Joseph, D. Digital Pixel Sensor Array with Logarithmic Delta-Sigma Architecture. Sensors 2013, 13, 10765-10782.
Mahmoodi A, Li J, Joseph D. Digital Pixel Sensor Array with Logarithmic Delta-Sigma Architecture. Sensors. 2013; 13(8):10765-10782.
Mahmoodi, Alireza; Li, Jing; Joseph, Dileepan. 2013. "Digital Pixel Sensor Array with Logarithmic Delta-Sigma Architecture." Sensors 13, no. 8: 10765-10782.