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Sensors 2013, 13(2), 1856-1871; doi:10.3390/s130201856

Article
A New Mirroring Circuit for Power MOS Current Sensing Highly Immune to EMI
Orazio Aiello * and Franco Fiori
Microelectronics EMC Group, Eln. Department, Politecnico di Torino, Corso Duca degli Abruzzi, 24, I-10129 Torino, Italy; E-Mail: franco.fiori@polito.it
*
Author to whom correspondence should be addressed; E-Mail: orazio.aiello@polito.it; Tel.: +39-011-090-4223; Fax: +39-011-564-4099.
Received: 8 November 2012; in revised form: 27 December 2012 / Accepted: 8 January 2013 /
Published: 31 January 2013

Abstract

: This paper deals with the monitoring of power transistor current subjected to radio-frequency interference. In particular, a new current sensor with no connection to the power transistor drain and with improved performance with respect to the existing current-sensing schemes is presented. The operation of the above mentioned current sensor is discussed referring to time-domain computer simulations. The susceptibility of the proposed circuit to radio-frequency interference is evaluated through time-domain computer simulations and the results are compared with those obtained for a conventional integrated current sensor.
Keywords:
current sensor; CMOS integrated circuit; smart power; electromagnetic interference (EMI); electromagnetic compatibility (EMC); senseFET; miller effect

1. Introduction

In the last decades, the development of CMOS technologies in terms of scale integration and component performance has made the integration of full electronic system into a single chip possible. Such System-on-Chips (SoCs) comprise complex high-speed digital blocks, analog circuits and power section [1,2]. The power-supply voltage of such integrated circuits has decreased over time, leading to lower noise margins. However, the level of disturbances collected by the wiring harnesses of the electronic systems from the surrounding environment has strongly increased because of the widespread use of wireless systems for radio/TV broadcasting and mobile communications. In this context, the need to understand the effect of radio frequency interference (RFI) on baseband integrated circuits has continued to grow and several studies have tried to set out design guidelines and new circuit topologies for making integrated circuits immune to RFI [38]. Such disturbances superimposed onto nominal signals are of particular concern in the design of input and output front-end integrated circuits like those included in smart power ICs, which cannot be protected using EMI-filters at the PCB level because either their presence can affect the nominal circuit operation or the PCB is not present since the SoC is encapsulated inside the sensor (actuator) plastic holder. For instance, EMI filters and capacitors cannot be connected to the power transistor terminals because they would reduce the power efficiency. As a result, the power transistors that drive actuators through cables can experience high-level RFI that can lead to unexpected transistor switching and leakage currents, as shown in [9,10]. In addition to this problem, the circuits that are connected to the transistors' terminals, including circuits embedded in smart power ICs for monitoring the operation of the power transistors and the actuators, are also affected by RFI.

Within the aforementioned context, this paper investigates the susceptibility of integrated current sensors that are used in power circuits for control and/or safety purposes to RFI. The current of a power transistor can be sensed by using one of the circuits presented in [11], but only a few of them are suitable for integration on silicon. Among these integrated current sensors, one of the most frequently used is that based on a small transistor namely SenseFET. The voltages at the terminals of the SenseFET are kept equal to those of a power transistor in which the current to be detected flows. In this way, such a current is scaled by a constant K and provided by the SenseFET. K depends only on the aspect ratios ( W L ) of the two transistors. In this circuit, the SenseFET is electrically connected to the terminals of the power transistor and therefore it is affected by the RF disturbances collected by cables. In order to design embedded current sensor immune to such RF interferences, this paper presents a new integrated current-sensing solution conceived to be electrically not connected to the power transistor drain that can be affected by disturbances. The current is sensed whenever during its transient the power transistor and the SenseFET both operate in saturation. Therefore, the current flowing through the power transistor is mirrored by the SenseFET, is not dependent on the drain-source voltage and is only related with the mirroring factor K. The paper is organized as follows. Section 2 describes the operation of a common integrated current sensor. Section 3 summarizes the switching behavior of power MOSFETs. On the basis of such a behavior, a new current sensor not electrically connected to the drain terminal of the power transistor is proposed in Section 4. Then, the results of computer simulations aimed at evaluating the susceptibility of the proposed current sensor, the MagFET-based sensor and the commonly used current sensor to RFI are shown in Section 5. Finally, some concluding remarks are drawn in Section 6.

2. A Conventional Current Sensor: The SenseFET

Common current sensors for integrated applications are based on the SenseFET circuit topology, in which the current iD (t) that flows through an MOS Power transistor is sensed using an elementary transistor of the same type that is used in the power transistor. Figure 1 shows the operation of the SenseFET current sensor, where the gate terminals of the aforementioned transistors are connected to each other and driven by an MOS driver, while the drain-to-source voltage of the SenseFET is made equal to that of the power transistor by means of a voltage follower. In this circuit, the relationship between the power transistor current (ID) and the sensed current (ISENSE) can be written as

K = ( W L ) power ( W L ) sense
where ( W L ) power and ( W L ) sense are the aspect ratios of the power and SenseFET transistors, respectively. K is typically not lower than 103. The scaled current ISENSE is then converted to a voltage, using a resistor to be used for digital signal processing. This paper focuses on a low side sensing topology highlighted in Figure 1.

However, the same reasoning can be applied for the high side topologies. In this technique the power dissipation is low and the accuracy is related to the matching of the SenseFET and the Power MOS. The two transistors are driven in the deep triode region by the same gate-source voltage and have to be kept at the same drain-source voltages. Therefore, to minimize the error in the sensed current, the amplifier needs to have a very high gain. Moreover, the amplifier should maintain the accuracy across the large input common-mode range. Although several circuit topologies of current sensors have been proposed, all of them include an amplifier, which implies stability issues, limited bandwidth and increased design complexity. In fact, the improvements in integrated current-sensing are basically focused on increasing amplifier performance [1219]. Furthermore, the presence of the amplifier increases the overall susceptibility of the commonly employed SenseFET-based current sensing to EMI. In fact, this amplifier is connected through an over-voltage protection (see Figure 1) to the power transistor drain, and hence to the wiring interconnects at the system level that collect EMI. Since interference with an amplitude of hundreds of mV causes distortion in the amplifier and in the over-voltage protection, the operation of the current sensor can be impaired [6].

For all the above mentioned reasons, a new current sensor with improved performance due to the absence of any amplifier has been designed and its immunity to EMI is specifically addressed in this paper.

3. Power MOSFET Switching Characteristics

The Power MOSFET is usually employed as a switch in circuits for energy conversion and management applications and to drive high-power loads. For instance, a Power MOSFET is used to control the current in inductive loads such as the windings of motors. A Power MOSFET that drives an inductive load is represented in Figure 2 where a freewheeling diode carries the load current when the Power MOS is switched-off and a stray inductance is included to account for package and board parasitic elements.

The switching behavior of Power MOSFET structures is governed by the gate drive circuit and the nature of the load. The power transistor is switched on and off by a control or gate drive circuit, which can be represented (Thevenin's equivalent) as a DC voltage VG with a series resistance RG. The load current iL transfers between the power MOSFET device and the freewheeling diode during each operating cycle. The inductor is charged and its current is increased when the Power MOSFET is turned-on while it is discharged when the load current flows through the diode. However, the change in the inductor current is small during one cycle, allowing the assumption that the current IL is constant. On the basis of that, a new current sensor that operates during the transient of the Power MOSFET has been conceived. To this purpose, the waveform of the transient of a Power MOSFET is represented in Figure 3 and described in the following. Whenever the Power MOSFET is in off-state, the load current flows through the freewheeling diode. The initial conditions for the Power MOSFET are defined by vGS(0) = 0, iD(0) = 0, vDS(0) = VDSOFF. During the turn-on process, the gate bias voltage source VG starts to charge the capacitances of the Power MOSFET. Since no drain current can flow through the power MOSFET device until the gate voltage exceeds its threshold voltage, the drain voltage initially remains at the drain bias voltage. The gate–drain capacitance CGD(VDSOFF) remains constant because the drain voltage is constant. Consequently, the time constant for charging the gate of the power MOSFET device is RG · [CGS + CGD(VDSOFF)], resulting in a gate voltage given by

v GS ( t ) = V GS max [ 1 e t R G [ C GS + C GD ( V DS OFF ) ] ]
and represented in Figure 3. The gate voltage reaches the threshold voltage at time t1:
v GS ( t ) | t = t 1 = V TH
t 1 = R G [ C GS + C GD ( V DS OFF ) ] ln ( V GS max V GS max V TH )

Once the gate voltage exceeds the threshold voltage, drain current begins to flow.

i D ( t ) = μ ni C OX W CH L CH [ v GS ( t ) V TH ] 2

Although the drain current increases, the drain voltage remains at the drain supply voltage VDSOFF because the diode cannot sustain any voltage until all of the load current is transferred to the Power MOSFET. Since the drain voltage remains constant, the drain–gate capacitance is also invariant in the range [t1t2]. Consequently, the gate voltage continues to increase at an exponential rate as described by Equation (2) with the same time constant. The drain current increases as the square of the gate voltage as described by Equation (5) with a nonlinear waveform as represented in Figure 3.

The drain current increases until it becomes equal to the load current ID = IL and vGS(t) reaches the voltage plateau VGSplateau at the time t2.

v GS ( t ) | t = t 2 = V GS plateau = V GS max [ 1 e t 2 R G [ C GS + C GD ( V DS OFF ) ] ]
t 2 = R G [ C GS + C GD ( V DS OFF ) ] ln ( V GS max V GS max I D L CH μ n C ox W CH V TH ) .

All of the load current has transferred from the diode to the Power MOSFET device at time t2 and the diode is now able to support voltage. The drain-source voltage of the Power MOSFET starts to reduce at this time. Since the drain current is constant and equal to the load current (ID = IL), the gate voltage at time t2 can be also expressed as

v GS ( t ) | t 2 t 3 = V GS plateau = V TH + I D L CH μ n C ox W CH .

The gate-source voltage remains constant at the plateau voltage until the drain-source voltage has reduced to the on-state voltage drop corresponding to the product of the load current and the on-resistance of the device at a gate bias equal to the plateau voltage. Since the gate voltage is constant during the plateau phase, all the gate current iGplateau is used to charge the gate–drain or Miller capacitance. The gate current during the plateau phase is given by

i G plateau = V GS max V GS plateau R G .

As this current charges the gate–drain capacitance, its voltage decreases at a rate given by

d v GD ( t ) d t = i GP ( t ) C GD ( v DS ( t ) ) .

Since the gate–source voltage is constant at VGSplateau during this time, the drain voltage also decreases linearly with time:

d v DS ( t ) d t = d v GD ( t ) d t = i GP ( t ) C GD ( v DS ( t ) ) = V GS max V GS plateau R G C GD ( v DS ( t ) ) .

At the end of the plateau phase at time t3, the drain–source voltage becomes equal to the on-state voltage drop corresponding to the plateau gate bias voltage. Based on this, the duration of the plateau can be expressed as:

t 2 t 3 d v D = t 2 t 3 V GS max V GS plateau R G C GD ( v DS ( t ) ) d t
t 3 t 2 = R G C GD AVG V GS max V GS plateau [ V DS OFF I D R DS ON ( V GS plateau ) ]
where CGDav is the gate–drain capacitance assumed to have a constant average value during the transient and RDSON(VGSplateau) is the on-resistance of the power MOSFET device for a gate-source voltage equal to the plateau voltage. Beyond the plateau, the gate voltage increases exponentially again as shown in the Figure 3 until it reaches the gate supply voltage. The time constant for this exponential rise is different from the initial phase due to the large gate–drain capacitance. The increasing gate voltage produces a reduction of the on-resistance of the power MOSFET device, resulting in a small reduction of the drain voltage during this fourth phase of the turn-on process.

Considering reasonable value for the parasitics of the Power transistor sized in the order of mm2 and for the integrated driving resistance RG, the interval time (t3t2) results to be larger than hundreds of nanoseconds. On the basis of a trigger event occurring during this interval, a new current sensor is proposed in Section 4.

4. A New Current Sensor Based on the Miller Effect

In order to design a current sensor immune to EMI, a new circuit is conceived, which is not electrically connected with the Power MOSFET drain terminal that is prone to disturbances. To this purpose, the current that flows through the Power MOSFET (iD) is mirrored and processed during the VGS voltage plateau due to the Miller effect (between points 2 and 3 in Figure 3). In this region, the Power MOSFET operates in the saturation region and the mirrored current IMIRROR is not dependent on the drain-source voltage and is only related with the mirroring factor K. The Power MOSFET is driven by a PWM signal that provides both the proper-timing driving voltage and a negative pulse that generates a switching transient with negligible reduction of the current in inductive loads.

The block diagram of the proposed current sensor is shown in Figure 4. A low-pass RC filter (RF– CF) with a cut-off frequency significantly lower than the frequency of the EMI disturbances is placed between the Power MOSFET and SenseFET gates. In particular, RF = 10 kΩ and CF = 2 pF, so that the cut-off frequency is less than 10 MHz (fCUT_OFF ≈ 8 MHz). The current Iunknown is mirrored by a SenseFET, processed and converted in a serial code (Analog to Digital Converter in Figure 4, further reported in Figure 5). The SenseFET current, in turn, is mirrored 128 times. Each of these currents is compared with progressively scaled current references in order to provide a thermometric digital code of the SenseFET current IMIRROR. Then, a further thermometric-to-binary conversion is provided [20]. As soon as a trigger event occurs, the binary code is written in a register. Such a binary word provides the value of the current to detect Iunknown, which is then converted to a serial code.

The trigger circuit is based on the comparison of an attenuated gate-source characteristic VGSatt with the gate-source voltage after a low-pass filtering process VGS_f. Both these two voltages are obtained from the gate-source voltage VGS by means of only passive component as represented in Figure 6. An inverting stage made of a high voltage inverter allows to null the current dissipation whenever the VGS voltage transient ends. Neglecting the drop voltage across the transistor MSD that operates in triode during the transient, the voltage VGS_att is given by:

V GS _ att = R 2 ( 1 + s R 1 C 1 ) R 2 ( 1 + s R 1 C 1 ) + R 1 ( 1 + s R 2 C 2 ) V G S

Setting R1C1 = R2C2 the voltage VGSatt is simply the gate-source voltage VGS scaled by a factor kdin_adp independently by the frequency components of the switching transient of the Power MOSFET.

V GS _ att = R 2 R 1 + R 2 V GS = C 1 C 1 + C 2 V GS = k din _ adp V GS
where kdin_adp is set in order to not overcome the maximum voltage deliverable to the analog blocks.

k din _ adp = R 2 R 1 + R 2 = C 1 C 1 + C 2

The voltage VGS_f is obtained by a filtering and the passive components (Rsm1, Csm1, Rsm2 and Csm2) are set to makes this voltage VGS_f lower than the attenuated voltage VGSatt during the interval [0 – t1]. At the same time, the passive components are set such that the filtered voltage VGS_f reaches the attenuated voltage VGSatt at the time t* during the plateau, as sketched in Figure 7.

{ V GS _ f ( t ) < V GS _ att ( t ) if 0 < t < t V GS _ f ( t ) > V GS _ att ( t ) if t < t < t 3

Assuming VGS as a ramp before the voltage plateau, it can be shown that the filtered voltage VGS_f(t) can be expressed as:

V GS _ f ( t ) = { m G ( s p ) 2 ( s p s z ) ( 1 e s p t ) + m G s z s p t if 0 < t < t 2 m G s p 2 ( s p s z ) e s p t ( e s p t 2 1 ) + m G s z s p t 2 if t 2 < t < t 3
where
m = V T H t 1
G = C s m 1 C s m 1 + C s m 2
s z = 1 R s m 1 C s m 1
s p = R s m 1 + R s m 2 R s m 1 R s m 2 ( C s m 1 + C s m 2 )

On the basis of the two considered voltages VGS_f and VGS_att, it is possible to find out the time t* during the voltage plateau when they are equal.

V GS _ f ( t ) | ( t 2 < t < t 3 ) = k din _ adp V GS plateau
m G s p 2 ( s p s z ) e s p t ( e s p t 2 1 ) + m G s z s p t 2 = k din _ adp V G S plateau
t = 1 s p ln [ k din _ adp V G S plateau m G s z s p t 2 G s p 2 ( s p s z ) ( e s p t 2 1 ) ] .

Firstly, a minimum value for Csm1 = 200 fF is set and a reasonable value of Rsm1 = 62 kΩ is chosen to set the zero sz = 12.8 MHz. Consequently, the value of Csm2 = 2.5 pF and Rsm2 = 19 kΩ are set in order to place the pole sp = 4.05 MHz before the zero. In this way an instant t* in the range [ t2t3] according to Equation (25) is found out and a correct trigger event can be provided. As soon as the mentioned two voltages VGS_att and VGS_f reach the same value during the gate-source plateau voltage due to the Miller effect, a comparator finds out a trigger event. Such an event enables to write the register whenever the Power MOSFET is in saturation during its switching transient. In the register, the digital value of the SenseFET current IMIRROR is stored. Such a value represents the current to sense Iunknown scaled by the mirroring ratio K.

The proposed circuit is suitable for inductor current monitoring in DC-DC converter that operates in Continuous Conduction Mode (CCM) and whenever the detection of the current flowing in a Power MOSFETs operating in PWM that drive resistive and inductive loads is needed. The current to be monitored ranges from 100 μA to 5 A, and the mirroring factor K has been set K = 104. The sensibility of the designed sensor is 50 μA (LSB). The absence of the amplifier provides an higher immunity to EMI and a faster response in inductor-current monitoring than the traditional current-sensing technique as shown in Section 5.

5. Prediction of Integrated Current Sensors to RFI

This section shows the results of the time-domain simulations carried out to evaluate the susceptibility of the proposed current sensor and the traditional sensor to RFI.

The proposed new current sensor is based on the transient behavior of the Power MOSFET in which the current to detect flows, and such a transient strongly depends on the parasitics of the Power transistor itself. For this reason, no other additional parasitic capacitances due to the test circuit have to affect the transient behavior of the Power MOSFET. Therefore, a CW RFI current of magnitude iRF = 200 mA has been superimposed onto the current to detect ID by means of a toroidal RF transformer.

In fact, the analyses of the susceptibility to RFI have been carried out referring to the schematic view of Figure 8 similarly to immunity tests [21]. A resistor RBIAS sets the value of the current ID.

Figure 9 shows the switching transient traces (VDS, VGS) of a Power MOSFET in which the current to be detected ID flows, as well as the respective currents provided by a traditional SenseFET sensor (ISENSE) and the proposed new sensor (IMIRROR). In such a time-domain simulations, a CW RFI current iRF = 200 mA at 100 MHz superimposed on the drain current have been considered. The currents provided by the traditional SenseFET sensor (ISENSE) and by the proposed new sensor (IMIRROR) versus current to sense ID and their minimum and maximum errors due to the aforementioned RFI magnitude at 10 MHz, 100 MHz and 400 MHz are shown respectively in Figures 1012. Furthermore, the minimum and maximum errors of the two considered currents due to a CW RFI iRF = 200 mA superimposed on the drain current ID versus frequency are reported in Figure 13. The results highlight that the immunity of the proposed current sensor to RFI is significantly greater than that of the conventional SenseFET circuit shown in Figure 1.

6. Conclusions

In this work, the susceptibility of common integrated sensors to RFI has been discussed for power transistor current monitoring. In order to improve the immunity of Power MOSFET transistor to RFI in current sensing, a new integrated solution has been proposed. It exploits the Miller effect on the switching transient of the Power MOSFET. The detection of the gate-source voltage plateau due to the Miller effect allows to mirror the current to be detected whenever the Power MOSFET operates in saturation. In this way, the mirrored current is not dependent on the drain-source voltage and the RFI that reaches the drain terminal of the Power MOSFET does not strongly influence the operation of the current sensor. Furthermore, there is no need to connect any amplifier to the drain terminal of the Power MOSFET, hence eliminating a barrier on the overall current sensor performance. The operation of the new current sensing circuit and that of a conventional current sensor have been compared in time-domain simulations. Since the novel sensor operates during the switching transient, it provides a faster current detection than the traditional sensor. Whereas the amplifier usually limits the performance of the SenseFET-technique, no such issue has to be considered for the new sensor. The susceptibility of the proposed current monitoring solution has been evaluated through time-domain simulations and compared with that of a conventional current sensor. The analyses carried out in this work have shown a significant improvement in the immunity to RFI in the range 1 MHz–1 GHz that the new proposed solution enables.

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Figure 1. Current sensor based on the SenseFET technique.

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Figure 1. Current sensor based on the SenseFET technique.
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Figure 2. Power MOSFET device operating in an inductive load circuit.

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Figure 2. Power MOSFET device operating in an inductive load circuit.
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Figure 3. Waveforms for the power MOSFET during turn-on with a gate voltage source.

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Figure 3. Waveforms for the power MOSFET during turn-on with a gate voltage source.
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Figure 4. Block diagram of the proposed current sensor that exploits the Miller effect.

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Figure 4. Block diagram of the proposed current sensor that exploits the Miller effect.
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Figure 5. Analog to Digital Converter in Figure 4.

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Figure 5. Analog to Digital Converter in Figure 4.
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Figure 6. Trigger circuit.

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Figure 6. Trigger circuit.
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Figure 7. Principle of the detection of the gate-source plateau.

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Figure 7. Principle of the detection of the gate-source plateau.
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Figure 8. Schematic view of the Power MOSFET considered in the time-domain simulations.

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Figure 8. Schematic view of the Power MOSFET considered in the time-domain simulations.
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Figure 9. Switching transient traces of a Power MOSFET (VDS, VGS, ID) and the respective currents provided by a traditional SenseFET sensor (ISENSE) and the new sensor based on the Miller effect (IMIRROR). CW RFI current amplitude 200 mA @ 100 MHz superimposed on the drain current.

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Figure 9. Switching transient traces of a Power MOSFET (VDS, VGS, ID) and the respective currents provided by a traditional SenseFET sensor (ISENSE) and the new sensor based on the Miller effect (IMIRROR). CW RFI current amplitude 200 mA @ 100 MHz superimposed on the drain current.
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Figure 10. Maximum and minimum current-sensing of the traditional SenseFET current sensor (ISENSE) and the new sensor based on the Miller effect (IMIRROR) versus current to sense ID. CW RFI current amplitude 200 mA @ 10 MHz.

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Figure 10. Maximum and minimum current-sensing of the traditional SenseFET current sensor (ISENSE) and the new sensor based on the Miller effect (IMIRROR) versus current to sense ID. CW RFI current amplitude 200 mA @ 10 MHz.
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Figure 11. Maximum and minimum current-sensing of the traditional SenseFET current sensor (ISENSE) and the new sensor based on the Miller effect (IMIRROR) versus current to sense ID. CW RFI current amplitude 200 mA @ 100 MHz.

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Figure 11. Maximum and minimum current-sensing of the traditional SenseFET current sensor (ISENSE) and the new sensor based on the Miller effect (IMIRROR) versus current to sense ID. CW RFI current amplitude 200 mA @ 100 MHz.
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Figure 12. Maximum and minimum current-sensing of the traditional SenseFET current sensor (ISENSE) and the new sensor based on the Miller effect (IMIRROR) versus current to sense ID. CW RFI current amplitude 200 mA @ 400 MHz.

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Figure 12. Maximum and minimum current-sensing of the traditional SenseFET current sensor (ISENSE) and the new sensor based on the Miller effect (IMIRROR) versus current to sense ID. CW RFI current amplitude 200 mA @ 400 MHz.
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Figure 13. Maximum and minimum current-sensing of the traditional SenseFET current sensor (ISENSE) and the new sensor based on the Miller effect (IMIRROR) versus frequency. CW RFI current amplitude 200 mA superimposed on a current ID = 1A.

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Figure 13. Maximum and minimum current-sensing of the traditional SenseFET current sensor (ISENSE) and the new sensor based on the Miller effect (IMIRROR) versus frequency. CW RFI current amplitude 200 mA superimposed on a current ID = 1A.
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