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Efficient Architecture for Spike Sorting in Reconfigurable Hardware
Department of Computer Science and Information Engineering, National Taiwan Normal University, Taipei 116, Taiwan
Department of Electronic Engineering, National Ilan University, Yilan 260, Taiwan
* Author to whom correspondence should be addressed.
Received: 4 August 2013; in revised form: 21 October 2013 / Accepted: 21 October 2013 / Published: 1 November 2013
Abstract: This paper presents a novel hardware architecture for fast spike sorting. The architecture is able to perform both the feature extraction and clustering in hardware. The generalized Hebbian algorithm (GHA) and fuzzy C-means (FCM) algorithm are used for feature extraction and clustering, respectively. The employment of GHA allows efficient computation of principal components for subsequent clustering operations. The FCM is able to achieve near optimal clustering for spike sorting. Its performance is insensitive to the selection of initial cluster centers. The hardware implementations of GHA and FCM feature low area costs and high throughput. In the GHA architecture, the computation of different weight vectors share the same circuit for lowering the area costs. Moreover, in the FCM hardware implementation, the usual iterative operations for updating the membership matrix and cluster centroid are merged into one single updating process to evade the large storage requirement. To show the effectiveness of the circuit, the proposed architecture is physically implemented by field programmable gate array (FPGA). It is embedded in a System-on-Chip (SOC) platform for performance measurement. Experimental results show that the proposed architecture is an efficient spike sorting design for attaining high classification correct rate and high speed computation.
Keywords: spike sorting; reconfigurable computing; system-on-chip; generalized Hebbian algorithm; fuzzy C-means; FPGA
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Cite This Article
MDPI and ACS Style
Hwang, W.-J.; Lee, W.-H.; Lin, S.-J.; Lai, S.-Y. Efficient Architecture for Spike Sorting in Reconfigurable Hardware. Sensors 2013, 13, 14860-14887.
Hwang W-J, Lee W-H, Lin S-J, Lai S-Y. Efficient Architecture for Spike Sorting in Reconfigurable Hardware. Sensors. 2013; 13(11):14860-14887.
Hwang, Wen-Jyi; Lee, Wei-Hao; Lin, Shiow-Jyu; Lai, Sheng-Ying. 2013. "Efficient Architecture for Spike Sorting in Reconfigurable Hardware." Sensors 13, no. 11: 14860-14887.