Sensors 2013, 13(11), 14860-14887; doi:10.3390/s131114860
Article

Efficient Architecture for Spike Sorting in Reconfigurable Hardware

1,* email, 1email, 2email and 1email
Received: 4 August 2013; in revised form: 21 October 2013 / Accepted: 21 October 2013 / Published: 1 November 2013
(This article belongs to the Section Physical Sensors)
This is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
Abstract: This paper presents a novel hardware architecture for fast spike sorting. The architecture is able to perform both the feature extraction and clustering in hardware. The generalized Hebbian algorithm (GHA) and fuzzy C-means (FCM) algorithm are used for feature extraction and clustering, respectively. The employment of GHA allows efficient computation of principal components for subsequent clustering operations. The FCM is able to achieve near optimal clustering for spike sorting. Its performance is insensitive to the selection of initial cluster centers. The hardware implementations of GHA and FCM feature low area costs and high throughput. In the GHA architecture, the computation of different weight vectors share the same circuit for lowering the area costs. Moreover, in the FCM hardware implementation, the usual iterative operations for updating the membership matrix and cluster centroid are merged into one single updating process to evade the large storage requirement. To show the effectiveness of the circuit, the proposed architecture is physically implemented by field programmable gate array (FPGA). It is embedded in a System-on-Chip (SOC) platform for performance measurement. Experimental results show that the proposed architecture is an efficient spike sorting design for attaining high classification correct rate and high speed computation.
Keywords: spike sorting; reconfigurable computing; system-on-chip; generalized Hebbian algorithm; fuzzy C-means; FPGA
PDF Full-text Download PDF Full-Text [15724 KB, uploaded 21 June 2014 09:59 CEST]

Export to BibTeX |
EndNote


MDPI and ACS Style

Hwang, W.-J.; Lee, W.-H.; Lin, S.-J.; Lai, S.-Y. Efficient Architecture for Spike Sorting in Reconfigurable Hardware. Sensors 2013, 13, 14860-14887.

AMA Style

Hwang W-J, Lee W-H, Lin S-J, Lai S-Y. Efficient Architecture for Spike Sorting in Reconfigurable Hardware. Sensors. 2013; 13(11):14860-14887.

Chicago/Turabian Style

Hwang, Wen-Jyi; Lee, Wei-Hao; Lin, Shiow-Jyu; Lai, Sheng-Ying. 2013. "Efficient Architecture for Spike Sorting in Reconfigurable Hardware." Sensors 13, no. 11: 14860-14887.

Sensors EISSN 1424-8220 Published by MDPI AG, Basel, Switzerland RSS E-Mail Table of Contents Alert