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Using SRAM Based FPGAs for Power-Aware High Performance Wireless Sensor Networks
Centro de Electronica Industrial, Universidad Politecnica de Madrid, Jose Gutierrez Abascal 2, Madrid 28006, Spain
* Author to whom correspondence should be addressed.
Received: 2 December 2011; in revised form: 23 December 2011 / Accepted: 22 February 2012 / Published: 28 February 2012
Abstract: While for years traditional wireless sensor nodes have been based on ultra-low power microcontrollers with sufficient but limited computing power, the complexity and number of tasks of today’s applications are constantly increasing. Increasing the node duty cycle is not feasible in all cases, so in many cases more computing power is required. This extra computing power may be achieved by either more powerful microcontrollers, though more power consumption or, in general, any solution capable of accelerating task execution. At this point, the use of hardware based, and in particular FPGA solutions, might appear as a candidate technology, since though power use is higher compared with lower power devices, execution time is reduced, so energy could be reduced overall. In order to demonstrate this, an innovative WSN node architecture is proposed. This architecture is based on a high performance high capacity state-of-the-art FPGA, which combines the advantages of the intrinsic acceleration provided by the parallelism of hardware devices, the use of partial reconfiguration capabilities, as well as a careful power-aware management system, to show that energy savings for certain higher-end applications can be achieved. Finally, comprehensive tests have been done to validate the platform in terms of performance and power consumption, to proof that better energy efficiency compared to processor based solutions can be achieved, for instance, when encryption is imposed by the application requirements.
Keywords: wireless sensor networks (WSNs); FPGA; dynamic and partial reconfiguration (DPR); energy efficiency
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Cite This Article
MDPI and ACS Style
Valverde, J.; Otero, A.; Lopez, M.; Portilla, J.; de la Torre, E.; Riesgo, T. Using SRAM Based FPGAs for Power-Aware High Performance Wireless Sensor Networks. Sensors 2012, 12, 2667-2692.
Valverde J, Otero A, Lopez M, Portilla J, de la Torre E, Riesgo T. Using SRAM Based FPGAs for Power-Aware High Performance Wireless Sensor Networks. Sensors. 2012; 12(3):2667-2692.
Valverde, Juan; Otero, Andres; Lopez, Miguel; Portilla, Jorge; de la Torre, Eduardo; Riesgo, Teresa. 2012. "Using SRAM Based FPGAs for Power-Aware High Performance Wireless Sensor Networks." Sensors 12, no. 3: 2667-2692.