Advanced Interconnect and Packaging

Edited by
February 2023
266 pages
  • ISBN978-3-0365-6733-4 (Hardback)
  • ISBN978-3-0365-6732-7 (PDF)

This book is a reprint of the Special Issue Advanced Interconnect and Packaging that was published in

Chemistry & Materials Science
Physical Sciences

Unlike transistors, the continuous downscaling of feature size in CMOS technology leads to a dramatic rise in interconnect resistivity and concomitant performance degradation. At nanoscale technology nodes, interconnect delay and reliability become the major bottlenecks faced by modern integrated circuits. To resolve these interconnect problems, various emerging technologies, including airgap, nanocarbon, optical, and through-silicon via (TSV), have been proposed and investigated. For example, by virtue of TSV technology, dies can be stacked to increase the integration density. More importantly, 3D integration and packaging also offer the most promising platform to implement "More-than-Moore" technologies, providing heterogeneous materials and technologies on a single chip. The "Advanced Interconnect and Packaging" Special Issue seeks to showcase research papers on new developments in advanced interconnect and packaging, i.e., on the design, modeling, fabrication, and reliability assessment of emerging interconnect and packaging technologies. Additionally, there are two interesting papers on carbon nanotube interconnects and interconnect reliability issues.

  • Hardback
License and Copyright
© 2022 by the authors; CC BY-NC-ND license
antenna current; transmission line model; frequency-selective surface analytical approximation; low-temperature soldering; 3D IC; Bi aggregation; Sn-Bi solder; integrated circuit interconnects; aging; reliability; electromigration; physics-based modeling; average power handling capability (APHC); slow-wave transmission line (SWTL); thermal resistance; average heat-spreading width; temperature-dependent resistivity; broadside structure; far-end crosstalk; impedance; interposer channel; silicon interposer; vertical tabbed via; on-chip interconnect; carbon nanotube; through-silicon-via (TSV); Cu-CNT composite; Cu–Sn bonding; Au–Au bonding; graphene; high-temperature pressure sensor; substrate integrated waveguide (SIW); spoof surface plasmon polaritons (SSPPs); integrated passive device; through-dielectric capacitor (TDC); electromagnetic bandgap (EBG); interposers; low-loss substrates; noise suppression structures; packages; power delivery network (PDN); power/ground noise; Pt–Pt interconnection; high-temperature resistant packaging; metallic bonding; Au wire bonding; high-temperature annealing; focused ion beam (FIB); morphology analysis; wettability; hot-melt glass; flow time; coverage thickness; SiO2 and Au substrate; MEMS sensor; reliability evaluation; vacuum degradation; mathematical model; parylene; blood oxygen; sensing array; wearable device; graphene; on-chip spiral inductor; circuit model; kinetic inductance; quantum resistance; frequency selective rasorber (FSR); spoof surface plasmon polaritons (SSPP); frequency selective surface (FSS); broadband; dual active bridge; deadbeat controller; load feedforward; n/a

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