Low Cost Test Pattern Generation in Scan-Based BIST Schemes
Round 1
Reviewer 1 Report
Globally, the proposed approach is shown to be better with respect to some criteria than the previous approach presented by the authors (although it is in many cases less efficient in terms of power, and especially peak power, that is claimed to be the main target). I am not convinced that this paper will have a tremendous impact but it may give some complementary information with respect to the previous paper ([4] 2013).
The authors should mention early in the introduction what kind of circuits (or blocks) they are targetting. As an example, a BIST for a memory has not many similarities with a BIST for logic.
General structure (figure 1): the clock control module is a real drawback of the proposed approach, because it is difficult to implement (and route). Why is this block considered as necessary?
I have not understood what is m w.r.t. M (line 32) ... The number of scan chains in the circuit has no reason to change due to the "broadcaster".
Line 35: we are happy to learn that you know the solution ... but this should be shown in the paper with the required justifications rather just to be claimed.
Line 47: a LFSR is ONE shift register, not multiple shift registers ...
Why choosing a Johnson counter and not for example a Gray code?
Table 1: the number of patterns is VERY small. More realistic numbers should be used in the evaluations.
More on the form:
Introduction: "VLSI testing is an important method" => VLSI testing is not a method ... there are many methods to achieve the goals of VLSI testing. Globally, the English formulations in the paper are quite poor and should be noticeably enhanced. This is not mainly related to language editing, but to the presentation of the main ideas.
The structure of the paper should be announced at the end of the introduction.
Most of the references are quite old. A lot of work is on-going at the international level and should be better taken into account.
Author Response
Reply to Reviewers’ Comments
Dear Editors and Reviewers:
Thank you for your comments concerning our manuscript that was entitled “Low Cost Test Pattern Generation in Scan-Based BIST Schemes”. Thank you very much for giving us an opportunity to revise our manuscript. Those comments are all valuable and very helpful for revising and improving our paper, as well as the important guiding significance to our researches. We tried our best to improve the manuscript and made some changes in the manuscript. These changes will not influence the content and framework of the paper. We appreciate for your warm work earnestly, and hope that the correction will meet with approval. Once again, thank you very much for your comments and suggestions.
The main corrections are labeled red in the paper and the main improvement are described as follows.
Response to Reviewer #1
Globally, the proposed approach is shown to be better with respect to some criteria than the previous approach presented by the authors (although it is in many cases less efficient in terms of power, and especially peak power, that is claimed to be the main target). I am not convinced that this paper will have a tremendous impact but it may give some complementary information with respect to the previous paper ([4] 2013).
1. The authors should mention early in the introduction what kind of circuits (or blocks) they are targetting. As an example, a BIST for a memory has not many similarities with a BIST for logic.
Reply:
Thank you for this significant comment. The test pattern generation proposed in this paper is based on LBIST. The test patterns have the characteristics of pseudo-random. (Revised paper page1 line20 - 22)
2. General structure (figure 1): the clock control module is a real drawback of the proposed approach, because it is difficult to implement (and route). Why is this block considered as necessary?
Reply:
Because our method needs a slow clock (CLK1) and a fast clock (CLK2). A seed generator is an m-stage conventional LFSR, and operates at low frequency CLK1. The reconfigurable Johnson counter operates at high frequency CLK2. The test procedure is as follows.
1) The seed generator generates a new seed by clocking CLK1 one time.
2) The Johnson counter generates a new vector by clocking CLK2 one time.
3) Repeat 2 until 2l Johnson vectors are generated.
4) Repeat 1–3 until the expected fault coverage or test length is achieved.(Revised paper page2 line38 - 40)
3. I have not understood what is m w.r.t. M (line 32) ... The number of scan chains in the circuit has no reason to change due to the "broadcaster".
Reply:
Thank you for this comment. The specific broadcast structure is shown in Figure 3. Firstly we generate the original scan chains by bitwise XOR operation of the seed vector S and J vectors. Then we use broadcast circuit shown in Figure 3 to extend the original scan chains from m to 4m. If M scan chains are needed, the original generation module only needs to generate M/4 original scan chains. This can effectively reduce the hardware area overhead. (Revised paper page2 line44 - 46)
4. Line 35: we are happy to learn that you know the solution ... but this should be shown in the paper with the required justifications rather just to be claimed.
Reply:
Thank you for your encouragement. This configuration method has been obtained through a lot of mathematical analysis and experiments. Some of the analysis has been revised in the paper. (Revised paper page2 line59 - page3 line68).
5. Line 47: a LFSR is ONE shift register, not multiple shift registers ...
Reply:
Thank you for noting this unfortunate flaw. This problem has been revised in the paper. (Revised paper page3 line71 - 72)
6. Why choosing a Johnson counter and not for example a Gray code?
Reply:
There are some differences between Johnson counter and Gray code. The Johnson sequences also have the following characteristics:
1 ) Johnson sequences consist of a series of "0" and a series of "1".
2) The distribution of "0" and "1" in Johnson sequence is uniform. The probability of "0" and "1" appearing at each position in the Johnson vector is 0.5.
3) Johnson sequence is self-starting cycle.
But simple Johnson counter can not complete the data shift loading process. We reconstruct the Johnson counter according to the test pattern generation method. The structure is shown in Figure 2.
So we choose the reconfigurable Johnson counter. (Revised paper page3 line79 - 83)
7. Table 1: the number of patterns is VERY small. More realistic numbers should be used in the evaluations.
Reply:
Thank you for this significant comment. We added other data in Table 1. (Revised paper page6 Table 1) And we have obtained some statistical laws after our analysis. The data shown in Table 1 are just statistical number of periodic changes. (Revised paper page6 line 129 - 132)
8. Introduction: "VLSI testing is an important method" => VLSI testing is not a method ... there are many methods to achieve the goals of VLSI testing.
Reply:
Thank you for noting this unfortunate flaw. This problem has been revised in the paper. (Revised paper page1 line11 - 12)
9. The structure of the paper should be announced at the end of the introduction.
Reply:
Thank you for significant comment. This problem has been revised in the paper. (Revised paper page1 line30 - page2 line33)
10. Most of the references are quite old. A lot of work is on-going at the international level and should be better taken into account.
Reply:
Thank you for significant comment. This problem has been revised in the references. We added other 12 recent references in this paper. (Revised paper page10 line215 - page11 line268)
Reviewer 2 Report
Section 1: Introduction is very limited in terms of justifying the importance of the problem to solve. Moreover, the references given are very few and limited as well. In addition, authors have to describe the structure of the manuscript at the end of this section.
Section 2: The Broadcaster circuit, according to reference [5], is based on a very old design – what is the reason behind of this selection?
Section 3: Authors must give relevant references to justify their mathematical analysis. Very limited references.
Section 4: Information about the simulation ecosystem toolchain is missing. Very limited references. Furthermore, authors must explain why they only compare their new with their old approaches.
Sections 2, 3, and 4: for the sake of readers, authors must make clear what is their own contribution and what has been adopted as it is form others.
Conclusions: The advantages of the proposed approach should be given in the form of percentages or similar.
References: seems to be very few and very old.
Author Response
Reply to Reviewers’ Comments
Dear Editors and Reviewers:
Thank you for your comments concerning our manuscript that was entitled “Low Cost Test Pattern Generation in Scan-Based BIST Schemes”. Thank you very much for giving us an opportunity to revise our manuscript. Those comments are all valuable and very helpful for revising and improving our paper, as well as the important guiding significance to our researches. We tried our best to improve the manuscript and made some changes in the manuscript. These changes will not influence the content and framework of the paper. We appreciate for your warm work earnestly, and hope that the correction will meet with approval. Once again, thank you very much for your comments and suggestions. The main corrections are labeled red in the paper and the main improvement are described as follows.
Response to Reviewer #2
Section 1: Introduction is very limited in terms of justifying the importance of the problem to solve. Moreover, the references given are very few and limited as well. In addition, authors have to describe the structure of the manuscript at the end of this section.
Reply:
Thank you for your reasonable and great helpful advice. We revised the contents of the introduction and added the recent references (Revised paper page1 line20 - 28). The structure of the article has also been supplemented. (Revised paper page1 line30 - page2 line33)
Section 2: The Broadcaster circuit, according to reference [5], is based on a very old design – what is the reason behind of this selection?
Reply:
Thank you for your comment. As you said, the idea of broadcast is quite old indeed. So at the beginning of the study, we did some research on this aspect. The survey found that broadcast is still a major way to reduce area overhead. References 12-15 are added to explain in more detail. (Revised paper page11 line243 - 253)
Section 3: Authors must give relevant references to justify their mathematical analysis. Very limited references.
Reply:
Thank you for your comment. The mathematical features of BMSIC sequences have been briefly described in our previous paper (reference 9). This problem has been revised in the original paper. (Revised paper page4 line116)
Section 4: Information about the simulation ecosystem toolchain is missing. Very limited references. Furthermore, authors must explain why they only compare their new with their old approaches.
Reply:
Thank you for noting this unfortunate flaw. The simulation ecosystem toolchain has been revised. (Revised paper page8 line164 - 167) Because the method proposed in this paper is to overcome the drawback on the previous method (reference 9). In the previous paper, we have compared our proposed method with the commonly used LFSR method in the industry. This paper adds BMSIC performance on this basis. (Revised paper page8 line167 - 168)
Sections 2, 3, and 4: for the sake of readers, authors must make clear what is their own contribution and what has been adopted as it is from others.
Reply:
Thank you for your important comments for improving the clarity of the paper. References are cited in the structure of other people involved in this paper. The LFSR circuit (reference 8), broadcast circuit (reference 14) and Johnson counter circuit(reference 17) are existing structures. Based on these basic structures, we proposed our BMSIC-TPG method. But simple Johnson counter can’t complete the data shift loading process. So we reconstruct the Johnson counter according to the test pattern generation method, as shown in Figure 2. Since then, the architecture, methods and simulation have been proposed by ourselves.
Conclusions: The advantages of the proposed approach should be given in the form of percentages or similar.
Reply:
Thank you for your important comments for improving the clarity of the paper and its conclusions. This problem has been revised in the paper. (Revised paper page9 line204 - 205) 7. References: seems to be very few and very old. Reply: Thank you for significant comment. This problem has been revised in the references. We added other 12 recent references in this paper. (Revised paper page10 line215 - page11 line268)
Round 2
Reviewer 1 Report
The authors did significant changes that improve the clarity of their proposal. Some language improvements are possible but the paper has now (in my opinion) enough details and references to be clearly understood.
About the scientific and technical outcomes of the proposed approach, I remain less convinced. The fault coverage is not as good as with a LFSR (with large differences) and the power is worse than with the previous approach of the authors. The proposed approach is therefore at best oriented towards area (while the beginning of the paper insists on power) and only with respect to the previous approach of the authors since the LFSR is much better in terms of area.
I will therefore say that the paper can be accepted since I did not notice significant problems, but the impact of this paper will probably not be very high. I also strongly suggest to avoid starting the conclusion saying "This paper proposes a low-cost test pattern generation method that can be easily implemented by hardware to reduce the average and peak power consumption of sequential circuits during the test mode." since this is not true. This should be replaced by a sentence similar to the one added in the middle (in red) or something similar to the last sentence of the abstract.
Author Response
Reply to Reviewers’ Comments
Dear Editors and Reviewers:
Thank you for your comments concerning our manuscript that was entitled “Low Cost Test Pattern Generation in Scan-Based BIST Schemes”. Thank you very much for giving us an opportunity to revise our manuscript. Those comments are all valuable and very helpful for revising and improving our paper, as well as the important guiding significance to our researches. We tried our best to improve the manuscript and made some changes in the manuscript. These changes will not influence the content and framework of the paper. We appreciate for your warm work earnestly, and hope that the correction will meet with approval. Once again, thank you very much for your comments and suggestions.
The main corrections are labeled red in the paper and the main improvement are described as follows.
Response to Reviewer #1
1. The fault coverage is not as good as with a LFSR (with large differences) and the power is worse than with the previous approach of the authors. The proposed approach is therefore at best oriented towards area (while the beginning of the paper insists on power) and only with respect to the previous approach of the authors since the LFSR is much better in terms of area.
Reply:
Thank you for your important comments for improving the clarity of the paper. This paper aims to find a low-cost test pattern generation method based on our previous work MSIC-TPG in reference 6. (Revised paper page1 line12 - 17) As you said, LFSR is superior to MSIC and BMSIC in terms of fault coverage performance, especially in terms of TFC and area overhead. But the power consumption of LFSR is high. In order to reduce the power consumption, a method multi-single-input change (MSIC) test pattern generation combining a pseudo-random sequence with a low-transition sequence has been proposed in reference 6. This method adds the reconstructed Johnson counter and the XOR network circuits and scores well in power consumption. But it is poorer in area overhead. So this paper proposes BMSIC method to balance fault coverage, power consumption and area overhead. From the analysis of Table 2-4, BMSIC can basically reach more than 92% in SFC (the most critical faults in the circuit), and 75% in TFC. It can be seen that the fault coverage of BMSIC can be satisfied. And the BMSIC method is similar in power consumption compared with MSIC method but reduces 50% area overhead. So BMSIC is a method that takes into account three aspects.
2. I also strongly suggest to avoid starting the conclusion saying "This paper proposes a low-cost test pattern generation method that can be easily implemented by hardware to reduce the average and peak power consumption of sequential circuits during the test mode." since this is not true. This should be replaced by a sentence similar to the one added in the middle (in red) or something similar to the last sentence of the abstract.
Reply:
Thank you for your reasonable and great helpful advice. This problem has been revised in the paper. (Revised paper page9 line195 - 197)
