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Electronics 2014, 3(4), 661-674; doi:10.3390/electronics3040661

Optimizing Power Heterogeneous Functional Units for Dynamic and Static Power Reduction

Department of Electronics Engineering and Computer Science/8-19-1 Nanakuma, Fukuoka University, Jonan-ku, Fukuoka 814-0180, Japan
The author is currently with Hitachi Solutions, Ltd.
Author to whom correspondence should be addressed.
Received: 2 June 2014 / Revised: 9 October 2014 / Accepted: 18 November 2014 / Published: 10 December 2014
View Full-Text   |   Download PDF [364 KB, uploaded 10 December 2014]   |  


Power consumption is the major constraint for modern microprocessor designs. In particular, static power consumption becomes a serious problem as the transistor size shrinks via semiconductor technology improvement. This paper proposes a technique that reduces the static power consumed by functional units. It exploits the activity rate of functional units and utilizes the power heterogeneous functional units. From detailed simulations, we investigate the conditions in which the proposed technique works effectively for simultaneous dynamic and static power reduction and find that we can reduce the total power by 11.2% if two out of four leaky functional units are replaced by leakless ones in the situation where the static power occupies half of the total power. View Full-Text
Keywords: power consumption; leakage power; out-of-order processors; functional units power consumption; leakage power; out-of-order processors; functional units

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This is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. (CC BY 4.0).

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MDPI and ACS Style

Sato, T.; Shibata, Y. Optimizing Power Heterogeneous Functional Units for Dynamic and Static Power Reduction. Electronics 2014, 3, 661-674.

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