A Behavior Model of SiC DMOSFET Considering Thermal-Runaway Failures in Short-Circuit and Avalanche Breakdown Faults

Abstract

Accurate fault simulation and failure prediction have long been challenges for SiC MOSFETs users. This paper presents a behavior model of Silicon Carbide (SiC) double-implanted MOSFET (DMOSFET), considering thermal-runaway failures in short-circuit and avalanche breakdown faults on the basis of cell-level physical processes. The proposed model can simulate the faults with extremely high accuracy and precisely predict SiC DMOSFET’s short-circuit withstand time and critical avalanche energy. By finite-element simulations, cell-level physical processes of short-circuit and avalanche breakdown faults are clarified. The mechanisms of thermal-runaway failures are deeply discussed with references to existing studies. Based on semiconductor and device physics mechanisms, the proposed model is constructed upon a traditional behavior model of SiC MOSFET with several parallel branches that are proposed to describe the thermal-runaway failures during both faults. The Cauer thermal network model is used for estimating junction temperature within it. The proposed model is constructed in Simulink, and it is validated using short-circuit and unclamped inductive switching (UIS) tests.

1. Introduction

Silicon Carbide (SiC) is a kind of wide bandgap semiconductor material. Thanks to its excellent physical properties, SiC has advantages over Silicon (Si) in power electronics devices [1]. SiC metal-oxide semiconductor field-effect transistors (MOSFETs) are capable to perform well in high-frequency and high-temperature conditions with negligible tail currents and low switching oscillations [2,3]. SiC double-implanted MOSFET (DMOSFETs), also called planar-gate SiC MOSFETs, are the most mature type of SiC MOSFET and they are becoming more popular in the design of high-power-density and high-efficiency power electronics systems, such as motor drivers and charging piles of electric vehicles [4,5]. But in terms of reliability, especially the short circuit and avalanche ruggedness, they are far weaker than traditional Si IGBTs, which hinders them from large-scale applications [6,7].

Thermal runaway accounts for 38% of the causes of SiC MOSFET’s failures in short-circuit faults [7], and it is also the main failure mechanism in avalanche breakdown faults [6,8,9]. Thus, for integrality and accuracy, thermal-runaway failures are necessary to be included in the fault simulations of SiC MOSFET. However, finite-element simulation, which is often used to evaluate faults and failure of power electronics devices, is inconvenient for circuit designers. Behavior models are widely used by researchers and engineers in the design, optimization, and faults diagnosis of power electronics systems and design of protection circuits of power devices due to their fast simulation speed and considerable accuracy in circuit system simulations. However, the majority of behavior models of SiC MOSFETs focus on the accuracy of static and dynamic characteristics simulation at an operating temperature that is not extremely high [10,11,12,13,14,15,16,17]. They cannot simulate the devices under extreme operating conditions, like short-circuit and avalanche breakdown fault. For users of the devices and the circuit designer, if there exists a behavior model that can describe the faults and thermal-runaway failures of power devices, it is more convenient to carry out some simulations in extreme conditions, validate the design of protection circuit, and evaluate the reliability of the power devices in a power electronics system. For designers of power devices, if a behavior model is capable of reflecting the real cell-level parameters and the physical processes in faults and failures, it is easier to find out the key point in cell-level design to improve the device’s reliability in faults.

In recent years, several papers have paid attention to modeling SiC MOSFET’s faults [18,19,20,21,22,23]. The majority of them focus on fitting short-circuit characteristics of SiC MOSFETs without considering the physical mechanisms, therefore being less generic. Some models simulate short-circuit currents with equations entirely obtained using data fittings [18,19]. They cannot fully describe the physical processes of SiC MOSFET’s short-circuit fault and cannot ensure accuracy in different working conditions due to a lack of physical basis. In [20,21], electrothermal models are established to simulate temperature-dependent characteristics during short-circuit faults, aiming to clarify the short-circuit failure mechanisms and achieve failure prediction. But they can only be used to calculate the short-circuit withstand time, not for circuit simulation. A physically based short-circuit model of SiC MOSFET is presented in [22]. It introduces several physical models into parameter calculations for more accurate simulation and can emulate the short-circuit failure, whereas other faults, such as avalanche breakdown, are not included in it. Michele Riccio et al. proposed a temperature-dependent model accounting for both short-circuit and avalanche breakdown faults [23]. This model is built based on the physical processes of both faults, but the key parameters are all calculated using data fittings, which reduces its physical meaning and may impact its universality.

In a word, the existing models still suffer from one or more of the following weaknesses: (1) the model includes only short-circuit fault and cannot describe avalanche breakdown fault at the same time; (2) it lacks a physical basis, which may decline universality and accuracy of the model; (3) it cannot characterize failure phenomena that occur during faults.

To overcome the aforementioned problems, this paper presents a behavior model of SiC DMOSFET considering thermal-runaway failure in short-circuit and avalanche breakdown faults. The proposed model is more complete and universal than the existing ones because it is built based on cell-level processes of short-circuit and avalanche breakdown faults and can describe thermal-runaway failures in both faults. It can help device users design the protection circuit and evaluate the ruggedness of SiC MOSFET in some to improve the reliability in application. Meanwhile, for designers of SiC DMOSFET, the proposed model can help them intuitively and quickly analyze the influence of the design of the device on the characteristics of it and improve the design.

This paper is organized as follows. Section 2 clarifies the physical basis of the proposed model: it analyzes the cell-level physical processes of both faults by finite-element simulation and further discusses the thermal-runaway failure mechanisms with reference to existing studies. On this basis, Section 3 then illustrates the working principles of the model. Section 4 presents the calculation of the parameters used in the model: junction temperature, carrier mobility, leakage current, and so on. In Section 5, the proposed model is validated using a short-circuit test and unclamped inductive switching (UIS) test experiments, and a commercialized SiC DMOSFET, C2M0080120D produced by Wolfspeed, is selected as the modeling object. Finally, Section 6 concludes this paper.

2. Physical Basis

The cell-level physical processes of short-circuit and avalanche breakdown faults and the failure mechanisms of both faults are the physical basis of the proposed model. However, the cell-level phenomena are microscopic and hard to observe. To clarify the physical basis of the proposed model deeply, in this section, a finite-element model of SiC DMOSFET is built and short-circuit and avalanche breakdown test simulations are carried out. Based on the simulation results, the cell-level physical processes of short-circuit and avalanche breakdown faults are analyzed. Furthermore, with reference to the existing studies, the failure mechanisms of SiC DMOSFET during both faults are discussed in depth.

2.1. Finite-Element Cell Model and Fault Simulations

Thus, in order to clarify the physical basis of the proposed model, as shown in Figure 1, a 2D finite-element cell model of SiC DMOSFET is established in Synopsys Sentaurus TCAD according to the practical structure of the modeling object. The doping distributions of the P-well, N+ and P+ regions are completed using ion implantation simulations, in which Nitrogen is set for the N-type doping and Phosphorus is set for P-type doping. The shape and boundary of the regions in the model are similar with those regions formed using ion implantation in real devices [24]. The key structure parameters of the cell are given in Figure 1.

Appropriate physical models are selected in the finite-element simulation to enable the simulated results to reveal the realistic cell-level physical processes. The default drift-diffusion model is used for carrier transportation calculation and Fermi statistics are chosen as the carrier distribution function here. In terms of carrier mobility calculation, the Masetti model describing doping-dependent mobility degradation is used and the high field saturation effect is taken into account. Furthermore, to calculate the electron mobility near SiC/SiO₂ interface, the University of Bologna mobility model and the interface charge model is included. Moreover, the combination of the exponential and uniform model, N₀exp(−(E − E₀)/E_S) + N₁, is used, to fit the energetic distribution of both donor and acceptor interface traps, where D_IT,T = 1.3 × 10¹³/eV represents the energetic distribution of the interface state density near the band edge and D_IT,M = 4.0 × 10¹²/eV represents that near the middle of band. In the finite-element simulation, E_S = 0.069 eV describes the decay rate of the interface state density from band edge to the middle.

For the recombination model, the SRH, Auger and avalanche recombination are all considered and the Okuto–Crowell model is selected to calculate the impact ionization. Also, incomplete ionization and the anisotropy of 4H-SiC are considered. To emulate the lattice temperature variation during faults, the analytic thermoelectric powers model and thermodynamic model are introduced, and the model’s working temperature in static characteristics simulations and the initial temperature in fault simulations are set to 300 K.

The model’s simulated on-resistance is 90.9 mΩ and the simulated breakdown voltage is 1686 V, whose relative error to the measured results of C2M0080120D is approximately 1.6% and 2.3%, respectively. The simulated static characteristics of the model cannot be identical to a realistic device, because they can be significantly influenced by the incomplete physical model and some unreasonable parameters sets in the simulation software. However, it does not prevent the model and simulation from showing the correct semiconductor-level physical processes. The convinced cell structure, doping distribution formed using process simulation, and the proper physical models selected according to realistic physical mechanisms all indicate that the model is able to describe the modeling object’s cell-level physical processes during faults.

Then, short-circuit and UIS test circuits are built in Sentaurus TCAD and the cell model is put into it for fault simulations. In practical short-circuit and UIS test platforms, there may be some branches for protection between drain-gate or some branches between drain-source as buffer circuits. The aforementioned branches may affect the dynamic responses of the tests, but those factors do not actually influence the cell-level physical processes of SiC DMOSFET during faults. Hence, the simulation test circuit is simplified as shown in Figure 2, in which the inductance L here represents a small stray inductance of the power loop in the short-circuit test and a large load inductance in the UIS test.

By means of the fault simulations of the finite-element cell model, not only are the current and voltage waveforms obtained, but also the distributions of cell-level physical quantities, such as total current density, electric field, lattice temperature and so on, can be observed. These results may help to straightforwardly analyze the cell-level physical processes of SiC DMOSFET during faults as follows.

2.2. Cell-Level Physical Processes of Short-Circuit Fault and the Thermal-Runaway Failure in It

2.2.1. Cell-Level Physical Processes of Short-Circuit Fault

In Figure 3a, the solid blue lines and dotted orange line, respectively, represent the drain current I_D and the drain-source voltage U_DS waveforms in short-circuit fault test simulation when the failure does not occur. The process of SiC DMOSFET’s short-circuit fault can be divided into three stages according to its working states, and the vertical black dashed lines show the boundaries between stages. Figure 3b gives the corresponding maximum lattice temperature T_max curve in short-circuit fault test simulation.

With reference to the waveforms and the typical cell-level total current density distributions of these stages obtained from the simulation, as given in Figure 4, the physical processes of SiC DMOSFET’s short-circuit fault can be demonstrated:

• In stage I, gate drive voltage U_GS = −5 V and the SiC MOSFET is blocking. As shown in Figure 4a, the value of cell-level total current density is very low, which means almost no current flows through the device.
• In stage II, U_GS increases to 20 V and the device turns on. As shown in Figure 4b, the current begins to flow through the channel at the cell level. I_D increases and then falls because the channel electron mobility falls with increasing temperature.
• In stage III, U_GS turns to −5 V and the device turns off. I_D does not drop directly to zero, but first drops sharply to a small value and then slowly to zero, which is called tail current. At the cell level, as provided in Figure 4c, there is still leakage current flowing at the channel, but the value is far lower than that in stage II. The tail current is composed of the leakage current and it increases with the length of short-circuit pulse and maximum lattice temperature, indicating that high temperature is a main cause of non-negligible tail current [9,25,26].

2.2.2. Discussion on the Short-Circuit Failure Mechanism

In the past few years, plenty of researchers have focused on SiC DMOSFET’s failures in short-circuit faults. Most of them reach an agreement that there are two failure modes in SiC DMOSFET’s short-circuit fault: thermal runaway and gate oxide breakdown [7,9,25,26,27,28,29,30,31,32,33,34,35,36,37]. As for the origin of thermal runaway failure, there are several different explanations.

On the one hand, some researchers find that the source metal will melt under high-temperature conditions, causing the incapacity of drain and source during fault, which may lead to the failure [32,33,34]. However, lots of experiment results can prove that delayed thermal runaway exists in SiC DMOSFET’s short-circuit test [25,29]. As the I_D waveforms shows in the experiment results provided in those references, when U_GS returns to −5 V, I_D maintains a low value at first and then increase sharply, which indicates that the gate driver can no longer control the device and the thermal-runaway failure happens. If the melting of the source metal is the origin of thermal-runaway failure in a short-circuit fault, the current should increase sharply, which therefore reflects that the melting of the source metal is not the failure mechanism but the result of a failure, and the failure occurs at the semiconductor level.

On the other hand, more studies agree that the main cause of thermal-runaway failure is a non-negligible leakage current generated by a high temperature during the fault, and the leakage current may consist of a channel leakage current, a thermal generation current, and a current generated by parasitic BJT [7,9,25,26,28,29,31]. When the leakage current is high enough to trigger a positive temperature feedback, the device is out of control and the thermal-runaway failure happens. This mechanism has been demonstrated by sufficient experimental results and elaborate simulation analysis [9,25,26,29], so leakage current seems to be the more convincing short-circuit failure mechanism.

To clarify the physical processes of thermal-runaway failure in SiC DMOSFET’s short-circuit failure, we lengthen the short-circuit pulses in finite-element fault simulations and the U_DS, I_D and T_max curves in the case that the failure occurs can be obtained, as Figure 5 shows. The processes can also be divided into three stages. In stage I and II here, the physical processes obtained from the simulation results are essentially the same as the case that the failure does not occur. When the U_GS returns to zero at the beginning of stage III, I_D does not decline but increases rapidly, which implies that the gate driver can no longer control the device and the thermal-runaway failure happens. The total current density distribution of stage III is given in Figure 4d. It can be seen that the leakage current flows through not only the channel, but also the bottom of P-well region. Furthermore, compared with Figure 4c, the value is much higher.

Figure 6 compares the lattice temperature distribution of short-circuit faults before and after U_GS returns to −5 V for both cases that the failure does not occur and occurs. It is obvious that lattice temperature is much higher after U_GS returns to −5 V in the failure case, especially at the regions beside channel. As provided in Figure 5b, after the V_GS returns to −5 V, T_max does not decline like that in Figure 3b but still maintains the increasing trend. In Figure 6b, it can also be seen that the lattice temperature at channel does not decrease when short-circuit failure occurs. This means that there is a positive temperature feedback to hold the temperature. The results are the same with the existing studies [7,28,31].

According to the aforesaid illustrations and discussions, the short-circuit fault and failure part of the proposed model will be established based on the cell-level physical processes shown in simulation results and the failure mechanism discussed here; that a non-negligible leakage current generated by a high temperature leads to the thermal-runaway failure in SiC DMOSFET’s short-circuit fault.

2.3. Cell-Level Physical Processes of Avalanche Breakdown Fault and the Thermal-Runaway Failure within It

2.3.1. Cell-Level Physical Processes of Short-Circuit Fault

Figure 7 gives the U_DS, I_D, and T_max waveforms in UIS test simulation when the failure does not occur in avalanche breakdown fault. According to the working state of the device, the processes of avalanche breakdown in UIS test can be divided into four stages and the vertical dashed lines represent the boundaries between stages.

Similarly, with reference to the waveforms and the cell-level total current density distributions of these stages obtained from the simulation, as given in Figure 8, the physical processes of SiC DMOSFET’s avalanche breakdown fault can be demonstrated:

• In stage I, the device is in off-state. As shown in Figure 8a, at the cell level, there is only leakage current flow through the channel and the value is so small that it can be ignored.
• In stage II, the device turns on. I_D increases linearly because a large inductance is in series. At the cell level, the current flows through a thin channel closed to the SiC/SiO₂ interface, just like the stage II of short-circuit fault.
• In stage III, U_GS returns to −5 V and the device withstands very high voltage stress, causing an avalanche breakdown fault to occur at that moment. During a fault, U_DS is clamped to breakdown voltage, and it varies with increasing T_max. At the cell level, as shown in Figure 8c, it is obvious that the PN junction at the corner of the P-well region is broken down and the current path changes from the channel to the P-well region.
• In stage IV, I_D decreases to zero and U_DS drops to V_DC, which means the avalanche breakdown fault is over and the device returns to the blocking state. The cell-level total current density distribution is just the same as that in stage I.

2.3.2. Discussion on the Avalanche Breakdown Failure Mechanism

For the failure modes in SiC DMOSFET’s avalanche breakdown faults, a lot of studies have been presented. All of them agree that high temperature causes the thermal-runaway failure. In terms of failure mechanisms, there are four mainstream views: (1) the device’s junction temperature is so high that it will exceed the intrinsic limit of 4H-SiC; (2) the melting of the source metal; (3) the activation of the channel because the threshold voltage decreases with increasing junction temperature; (4) parasitic BJT latch-up at a high junction temperature [6,8,9,15,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52].

The intrinsic carrier concentration of 4H-SiC is low because of its wide bandgap and it reaches 1.0 × 10¹⁶ cm⁻³ at 1270 °C [38,39,53]. Some researchers estimate SiC DMOSFET’s junction temperature at the moment that avalanche failure occurs [38,40,41,42]. Though they give different estimated varying from 510 °C to 948 °C, which is a wide scale, it is obvious that the junction temperature during an avalanche breakdown fault cannot reach the intrinsic temperature limit of 4H-SiC. Hence, it seems that intrinsic limit is not likely to be SiC DMOSFET’s avalanche failure mechanism.

In the past several years, the majority of researchers agree that the avalanche failure mechanism is that the melting of source metal, like aluminum, leads to a short circuit between source and drain [38,41,43]. The reason given by them is that the estimated junction temperature when an avalanche failure occurs will be close to or exceed aluminum’s melting point and the temperature is not high enough to cause a latch-up of parasitic BJT and reach intrinsic limit. However, according to optical microscope diagram of failure devices shown in [8,43,44], the failure site steadily locates in the source pad near the bonding wire in different experiments. Figure 9 gives the schematic diagram of the cell-level structure in this area. At the location of source contact, there is a nickel (Ni) layer between the Al layer and 4H-SiC. The melting point of Ni is 1453 °C, which is much higher than that of Al and even 4H-SiC’s intrinsic limit. And in other locations, Al and 4H-SiC are also isolated. Furthermore, as aforementioned, the junction temperature cannot reach the intrinsic limit and the device still have blocking characteristics. The above illustrations suggest that if only the Al melts, the Al cannot be in contact with 4H-SiC and the melting of the Al cannot lead to a short circuit of source and drain. Combined with the junction temperature estimations provided in [38,41], the melting of source metal is more likely to be an inducement but not the immediate cause of SiC DMOSFET’s avalanche failure. Meanwhile, the immediate cause is more likely to occur at another site, maybe at the semiconductor level.

As for activation of the channel and parasitic BJT latch-up, failure mechanisms at the semiconductor level are also supported by several researchers [6,9,45,46]. Lots of researchers disagree with these opinions because they think the junction temperature during SiC DMOSFET’s avalanche breakdown cannot reach the value required by these failure mechanisms at a semiconductor level. However, there is some compelling evidence supporting the fact that mechanisms at the semiconductor level exist in SiC DMOSFET’s avalanche failure: ref. [46] gives some experiment results to show that SiC DMOSFET’s avalanche failure is related to the turn-off voltage of U_GS; and by means of analytically modeling the parasitic BJT, ref. [6] indicates that the BJT can be triggered at a temperature that is possible to be reached during avalanche breakdown fault. Moreover, during avalanche breakdown fault, the temperature distribution is not uniform. There exists hot spots in the active area of a die [43] and the temperature at the hot spot can be much higher than the estimated average junction temperature. Thus, the failure caused by mechanisms at the semiconductor level seems possible to occur in SiC DMOSFET’s avalanche breakdown fault. It may be the immediate cause of avalanche failure after the melting of the source metal. But confirming which of the correct avalanche failure mechanisms of SiC DMOSFET is correct still needs further verification.

To sum up the above discussions, the melting of the source metal seems more likely to be an inducement or a precursor of SiC DMOSFET’s avalanche failure; the immediate cause of the failure is still undecided.

Because SiC DMOSFET’s thermal-runaway failure may be related to the melting of source metal, which occurs out of the semiconductor, the finite-element simulation is not able to emulate this phenomenon. So measured results obtained from experiments, combined with the failure mechanisms discussed above, are used here to explain the physical processes of thermal-runaway failure in SiC DMOSFET’s avalanche breakdown fault. Figure 10 gives measured U_DS and I_D waveforms in the UIS test experiment and it can also be divided into four stages. It is obvious that the waveforms in stage I, II, and III are almost identical with them in the stages shown in Figure 6, indicating that the physical processes of them are almost the same, too. In stage IV, the device reaches a critical threshold. Then, the voltage returns to a very low value and the current begins to rise again in accordance with the slope in stage I. From the perspective of external characteristics, the phenomenon is similar to a short circuit between source and drain.

On the basis of the aforesaid illustrations and discussions, the short-circuit fault and failure part of the proposed model will be established, based on the cell-level physical processes shown in simulation results and the failure mechanism discussed here that a non-negligible leakage current generated by a high temperature leads to the thermal-runaway failure in SiC DMOSFET’s short-circuit fault. Also, the avalanche breakdown faults and thermal-runaway failure parts of the proposed can be built based on the above analysis. Critical threshold of the failure can be decided according to the thermal-runaway failure mechanisms discussed above, and it will be illustrated elaborately in Section III.

3. Working Principles of the Proposed Behavior Model

Based on the cell-level physical processes of both faults and thermal-runaway failures discussed in Section II, five working states can be defined to completely describe SiC DMOSFET’s behaviors in short-circuit and avalanche breakdown faults: off-state (Figure 4a and Figure 8a), on-state (Figure 4b and Figure 8b), leakage current state (Figure 4c,d), avalanche breakdown state (Figure 8c), and avalanche failure state. The five states are explained as follows:

Off-state and on-state are two basic working states that describe SiC MOSFET’s behaviors in conduction and blocking conditions, respectively. Leakage current is critical in tail current and thermal-runaway failure in short-circuit fault. Therefore, leakage current state is introduced. It is worth noting that according to semiconductor physics and the simulation results in Section II, leakage current exists in all working states of SiC MOSFET, but it can be ignored when the junction temperature is low. Hence, leakage current should be included in all five states, whereas it plays a leading role in the leakage current state (at a high junction temperature) and can be negligible in other working states. Because avalanche breakdown fault is caused by impact ionization and the thermal-runaway failure in it is induced by different mechanisms, two different working states, avalanche breakdown state and avalanche failure state, should be separately defined to characterize them. If a behavior model of SiC DMOSFET is able to take all five working states into consideration, it can completely describe all behaviors including short-circuit and avalanche breakdown faults and the thermal-runaway failures.

Figure 11 gives the circuit diagram of the proposed behavior model in this paper. It consists of two parts: a traditional behavior model of SiC MOSFET that describes on-state and off-state (the light blue part) and several extended parallel branches for describing leakage current, avalanche breakdown, and avalanche failure states (the pale golden part).

In the traditional behavior model, voltage-controlled current source I_MOS characterizes basic voltage-current relationships calculated in the metal-oxide-semiconductor (MOS) structure. C_GS, C_GD, and C_DS are parasitic capacitances between three terminals, which play critical roles in the dynamic responses of the model. D represents the body diode and R_G is the gate resistor integrated into the package. R_D represents the total resistance of the N⁻ drift layer and JFET region. Furthermore, because channel electron mobility varies with increasing junction temperature in short-circuit faults, it requires special calculations for carrier mobility used in I_MOS and R_D calculations according to semiconductor and device physics.

A controlled current source I_LEAK is included to describe the leakage current state. The physical mechanisms generating the current in leakage current state are totally different from that in on-state, so I_LEAK should be placed in a separate branch.

The physical mechanism of the PN junction’s avalanche breakdown is the current amplification effect caused by a high electric field. The current increases very sharply when U_DS reaches a critical value, also called the breakdown voltage. According to the above physical basis, a separate branch made up of a temperature-controlled voltage source U_BR and a controlled switch S_BR is included to characterize SiC DMOSFET’s avalanche breakdown state. Their working principles have been demonstrated in previous work [54].

As said in Section 2, from the perspective of external characteristics, the physical process of avalanche failure is similar to a short circuit happening between source and drain. Using the same idea of avalanche breakdown state modeling, as shown in Figure 11, the processes of an avalanche failure state are modeled as a separate branch consisting of a temperature-controlled switch S_F in the proposed behavior model. The avalanche failure mechanisms discussed in Section 2 suggests that the melting of Al seems to be an inducement or a precursor of thermal-runaway failure in SiC DMOSFET’s avalanche breakdown fault, and the undecided mechanism occurs after that is more likely to be the immediate cause. Because the direct failure mechanism is still undecided, it can be simplified as a process spending a short period of time. Thus, the control logic of the switch can be defined as follows: after the junction temperature exceeds a critical threshold temperature T_CRIT, the melting of aluminum by a short time t_FD, enables the S_F to turn on and it cannot be turned off again. The T_CRIT characterizes the melting of the source metal, and the t_FD describes the undecided failure mechanism that occurs after the melting of the source metal. According to subsequent experimental verifications, this modeling approach for thermal-runaway failure in SiC DMOSFET’s avalanche breakdown fault is accurate enough and it is easy to modify and improve if the failure mechanisms are clarified further.

The junction temperature T significantly influences SiC DMOSFET’s characteristics in short-circuit and avalanche breakdown faults. So, the calculation of T should be included.

The models of all components and calculations of the key parameters in the proposed behavior model will be elaborated on in Section 4.

4. Models and Calculations

In this section, the modeling of all components and calculation methods of the key parameters in the proposed behavior model will be elaborated on, including the channel current, parasitic junction capacitances, the resistance of N-type drift layer and JFET layer, leakage current, junction temperature, and key physical parameters used in the above calculations such as intrinsic carrier concentration, threshold voltage and carrier mobility. A physically based and accurate methodology for avalanche breakdown voltage calculation has been explored in previous work [54] and it will not be repeated in this section.

Figure 12 displays the summary of parameters calculations in the proposed model. The parameters used in this section are listed in

Table A1. Parameters used in Section 4.

Symbol	Quantity	Value	Symbol	Quantity	Value
Cox	Capacitance of oxide per unit area	8.63 × 10−8 F/cm2	WCELL	Width of a cell	4.0 μm
LCH	Length of channel	0.5 μm	WJFET	Width of JFET region	0.8 μm
LCELL	Total with of channel considering the number of cells	8.2 × 105 μm	q	Elementary charge	1.602 × 10−19 C
λ	Channel length modulation coefficient	5.44 × 10−5 V−1	kB	Boltzmann constant	1.38 × 10−23 J/K
$C_{\mathrm{GS}}$	Gate-source, drain-source capacitance	1130 pF	εSiC	Permittivity of 4H-SiC	8.553 × 10−13 F/cm
Cr0	Parameters used for fitting parasitic junction capacitances Crss	381.2 pF	S	Equivalent junction area generating leakage current	0.18 cm2
Vr	Ditto	19.7 V	τg	Carrier lifetime	2.0 ns
Mr	Ditto	0.0084	NCH	Equivalent doping concentration of the channel	8.0 × 1016 cm−3
δr	Ditto	872.7 pF	me	Electron mass	9.1 × 10−31 kg
γr	Ditto	0.1861 V−1	h	Planck constant	6.63 × 10−30 kg⸱cm2/s
CrssFD	Ditto	−363.3 pF	nF	Density of fixed charge at the SiC/SiO2 interface	1.3 × 1012 cm−2
Co0	Parameters used for fitting parasitic junction capacitances Coss	1747.9 pF	ΦM	Work function of the poly silicon gate	4.05 eV
Vo	Ditto	2.6 V	χ	Electronic affinity of 4H-SiC	3.60 eV
Mo	Ditto	0.79	μMIN	Parameters used in μB calculation	40
δo	Ditto	−91.8 pF	μL	Ditto	950
γo	Ditto	100 V−1	NREF	Ditto	1.94 × 1017 cm−3
CossFD	Ditto	80.1 pF	K1	Parameters used in μAC calculation	1.0 × 106 cm/s
NJFET	Equivalent doping concentration of JFET region	5.0 × 1016 cm−3	K2	Ditto	3.23 × 106K⸱cm⸱s−1⸱(V/cm)−2/3
NDR	Doping of N-type drift layer	9.0 × 1015 cm−3	ΓSR	Parameters used in μSR calculation	5.82 × 1014 V/s
NPWELL	Equivalent doping of P-well region	1.0 × 1017 cm−3	ΓCit	Parameters used in μCit calculation	2.375 eV−1cm−2
HJFET	Height of JFET region	1.0 μm	nSCR	Ditto	1.4 × 1012 cm−2
HEPI	Thickness of epitaxial layer	12.0 μm	ζC	Ditto	0.8
HDIFF	Thickness of current diffusion layer	4.0 μm

in the Appendix A. The majority of the parameters related to device structure and fabrication can be obtained from the finite-element model of Section 2 and the open literature. Some fitting parameters can be obtained through curve fitting.

4.1. Channel Current I_MOS, Parasitic Junction Capacitance C_GS, C_DS, C_GD, and Body Diode D

In the proposed model, the channel current I_MOS is calculated using (1). The selected model is derived in an ideal N-channel enhanced MOS structure and takes the channel length modulation effect into account [19]. It is widely used in characterizing MOSFET’s fundamental voltage–current relationship.

In (1), channel electron mobility μ_CH and threshold voltage V_T are the key parameters influencing the variation in current and the calculations of them will be presented later. C_ox is the capacitance of oxide per unit area; L_CH is the length of channel; L_CELL represents the equivalent total width of channel considering the number of cells; λ is the channel length modulation coefficient.

Models of parasitic junction capacitances are necessary for switching process simulations. In the proposed model, C_GS is modeled as a constant capacitance, C_GD and C_DS are, respectively, modeled as C_rss and (C_oss−C_rss), in which C_rss and C_oss is calculated using (2) and (3) [55]. C_r0, V_r, M_r, δ_r, γ_r, C_rssFD, V_o, M_o, δ_o, γ_o, and C_ossFD are all fitting parameters used for parasitic capacitance calculation. In (2) and (3), except U_DS which represents the drain-source voltage, all other parameters are obtained from data fitting according to the datasheet.

$$I_{\mathrm{MOS}}=\left\{\begin{array}{cc}0\hfill & U_{\mathrm{GS}}\le V_{\mathrm{T}}\hfill \\ {\mu }_{\mathrm{EFF}}{C}_{\mathrm{ox}}\frac{L_{\mathrm{CELL}}}{L_{\mathrm{CH}}}\left[\left(U_{\mathrm{GS}}-V_{\mathrm{T}}\right)\cdot U_{\mathrm{CH}}-{U_{\mathrm{CH}}}^2/2\right]\cdot \left(1+\lambda U_{\mathrm{CH}}\right)\hfill & U_{\mathrm{GS}}>V_{\mathrm{T}}, U_{\mathrm{CH}}<U_{\mathrm{GS}}-V_{\mathrm{T}}\hfill \\ \frac{{\mu }_{\mathrm{EFF}}{C}_{\mathrm{ox}}}{2}\cdot \frac{L_{\mathrm{CELL}}}{L_{\mathrm{CH}}}{\left(U_{\mathrm{GS}}-V_{\mathrm{T}}\right)}^2\cdot \left(1+\lambda U_{\mathrm{CH}}\right)\hfill & U_{\mathrm{GS}}>V_{\mathrm{T}},U_{\mathrm{CH}}\ge U_{\mathrm{GS}}-V_{\mathrm{T}}\hfill \end{array}\right.$$

(1)

$$C_{\mathrm{rss}}=C_{\mathrm{r}0}{\left(\frac{V_{\mathrm{r}}}{V_{\mathrm{r}}+U_{\mathrm{DS}}}\right)}^{M_{\mathrm{r}}}+{\delta }_{\mathrm{r}}\left[1-\tanh \left({\gamma }_{\mathrm{r}}{U}_{\mathrm{DS}}\right)\right]+C_{\mathrm{rssFD}}$$

(2)

$$C_{\mathrm{oss}}=C_{\mathrm{o}0}{\left(\frac{V_{\mathrm{o}}}{V_{\mathrm{o}}+U_{\mathrm{DS}}}\right)}^{M_{\mathrm{o}}}+{\delta }_{\mathrm{o}}\left[1-\tanh \left({\gamma }_{\mathrm{o}}{U}_{\mathrm{DS}}\right)\right]+C_{\mathrm{ossFD}}$$

(3)

The parasitic body diode is an indispensable part of SiC DMOSFET, but it has almost no effect on the fault and failure characteristics of the device. Hence, the body diode is modeled as an anti-parallel ideal diode in the proposed model. The results shown in Section V can verify that the simplified model of the body diode does not influence the accuracy of the proposed model.

4.2. Drain Resistance R_D

The resistance of the N-type drift layer and the JFET region of SiC DMOSFET changes with increasing junction temperature, which can significantly influence the characteristics of the device during fault because the junction temperature increases sharply. Thus, the resistances are carefully modeled as follows and they are combined into a drain resistance, R_D, in the proposed model.

The resistance of the JFET region can be calculated using (4).

$$R_{\mathrm{JFET}}=\frac{1}{q{\mu }_{\mathrm{N}}{N}_{\mathrm{JFET}}}\cdot \frac{H_{\mathrm{JFET}}}{(W_{\mathrm{JFET}}-W_{\mathrm{SCR}})L_{\mathrm{CELL}}}$$

(4)

In (4), the μ_N represents the electron mobility of the JFET region and the N-type layer, and its calculation will be presented in part E; q represents elementary charge; N_JFET is the equivalent doping concentration of the JFET region; W_SCR is the width of the space charge region between the JFET region and the P-well region and it can be calculated using (5).

$$W_{\mathrm{SCR}}=\sqrt{\frac{2{\epsilon }_{\mathrm{SiC}}}{q{N}_{\mathrm{DR}}}\cdot \left[\frac{k_{\mathrm{B}}T}{q}\ln \left(\frac{N_{\mathrm{JFET}}{N}_{\mathrm{PWELL}}}{n_{\mathrm{i}}^2}\right)+U_{\mathrm{CH}}\right]}$$

(5)

In (5), n_i, the intrinsic carrier concentration, will be modeled physically in Section 4.5; ε_SiC is the permittivity of 4H-SiC; N_DR is the doping of the N-type drift layer; k_B represents the Boltzmann constant; N_PWELL is the equivalent doping of the P-well region; U_CH is the voltage on the channel.

According to the cell-level total current distribution obtained from the finite-element simulation, when SiC DMOSFET is in on-state, there is a trapezoid-like “current diffusion layer” located at the top of the N-type drift layer because the depletion region is blocked. Under the layer, the current distribution is uniform. So, the resistance of the N-type drift layer can be divided into two parts. The upper one, named as R_DRU, represents the resistance of the current diffusion layer and is modeled as a trapezoidal resistance. It can be calculated using (6).

$$R_{\mathrm{DRU}}=\frac{H_{\mathrm{DIFF}}/(W_{\mathrm{CELL}}-W_{\mathrm{JFET}}+W_{\mathrm{SCR}})}{q{\mu }_{\mathrm{N}}{N}_{\mathrm{DR}}{L}_{\mathrm{CELL}}}\ln \left(\frac{W_{\mathrm{JFET}}-W_{\mathrm{SCR}}}{W_{\mathrm{CELL}}}\right)$$

(6)

In (6), H_DIFF is the thickness of the current diffusion layer, W_CELL is the width of a cell, W_JFET is the width of the JFET region. The lower one, named as R_DRL, represents the resistance of the layer in which current flows uniformly and it can be calculated using (7).

$$R_{\mathrm{DRL}}=\frac{1}{q{\mu }_{\mathrm{N}}{N}_{\mathrm{DR}}}\cdot \frac{H_{\mathrm{EPI}}-H_{\mathrm{JFET}}-H_{\mathrm{DIFF}}}{W_{\mathrm{CELL}}{L}_{\mathrm{CELL}}}$$

(7)

In (7), H_EPI is the thickness of the epitaxial layer.

On this basis, the drain resistance in the proposed model can be defined as (8).

$$R_{\mathrm{D}}=R_{\mathrm{JFET}}+R_{\mathrm{DRU}}+R_{\mathrm{DRL}}$$

(8)

4.3. Leakage Current I_LEAK

The leakage current can be negligible in SiC DMOSFET under low-temperature conditions. But in high-temperature cases, it has a strong influence, which is a distinguishing feature of the SiC MOSFET’s short-circuit fault and the main cause of short-circuit failure. Hence, the accurate calculation of the leakage current is necessary. For SiC DMOSFET, the leakage current usually consists of three components: thermal generation current I_TH, diffusion current I_DIFF, and avalanche leakage current I_AV(LEAK) [12,14]. According to previous calculations, in SiC DMOSFET’s thermal-runaway failure in a short-circuit fault, the thermal generation current I_TH plays the leading role in total leakage current, and the other two components are miniscule, so they can be ignored in the total leakage current.

In the proposed model, a controlled current source I_LEAK is used to characterize the leakage current, and it is expressed by (9).

$$I_{\mathrm{L}}=I_{\mathrm{TH}}=S\cdot \frac{q{n}_{\mathrm{i}}}{{\tau }_{\mathrm{g}}}\sqrt{\frac{2{\epsilon }_{\mathrm{SiC}}{U}_{\mathrm{CH}}}{q}\left(\frac{N_{\mathrm{DR}}+N_{\mathrm{CH}}}{N_{\mathrm{DR}}{N}_{\mathrm{CH}}}\right)}$$

(9)

In (9), S is the equivalent junction area generating leakage current; τ_g is the carrier lifetime.

4.4. Junction Temperature

During short-circuit and avalanche breakdown faults, SiC MOSFET generates high power dissipation, which causes the junction temperature to increase sharply and can considerably influence its behavior.

An RC thermal network is widely used for junction temperature evaluation in behavior models of power semiconductor devices. In the proposed model, a 14-order Cauer thermal network, shown in the red part of Figure 12, is included to calculate the junction temperature. As provided in

Table 1. Values of thermal resistances and thermal capacitances in Cauer thermal network.

i	1	2	3	4	5	6	7	8	9	10	11	12	13	14
Rthi (mK/W)	13.3	13.3	37.8	36.9	83.6	58.4	43.2	51.2	51.9	47.5	46.6	58.7	40.8	10.4
Cthi (mJ/K)	0.424	0.341	1.32	1.58	1.88	2.64	8.50	14.2	26.0	47.8	102	165	282	2410

, the values of the thermal resistance R_thi and thermal capacitance C_thi used in this paper are obtained from the SPICE models given via Wolfspeed, Durham, NC, USA.

4.5. Physical Parameters

As mentioned above, some key physical parameters are introduced in the proposed model, such as intrinsic carrier concentration, threshold voltage, and carrier mobility. They have important effects on SiC DMOSFET’s behaviors under fault and failure conditions, because they significantly change with the sharp increase in junction temperature. Thus, it is necessary to calculate them carefully. In this part, the models of intrinsic carrier concentration, threshold voltage, and carrier mobility are presented as follows.

4.5.1. Intrinsic Carrier Concentration

Intrinsic carrier concentration n_i is the key factor deciding the high-temperature characteristics of the power semiconductor devices. In this paper, n_i is calculated using its definition given in (10) [56].

$$n_{\mathrm{i}}={\left(N_{\mathrm{c}}{N}_{\mathrm{v}}\right)}^{1/2}\exp \left(\frac{E_{\mathrm{g}}}{2k_{\mathrm{B}}T}\right)$$

(10)

In (10), E_g is the band gap of 4H-SiC, which can be calculated using (11) [57].

$$E_{\mathrm{g}}=3.267-6.5\times {10}^{-4}\frac{T^2}{T+1300}$$

(11)

N_c and N_v, provided in (12) and (13) [56], represent the effective density of state in the conduction band and the valence band, respectively.

$$N_{\mathrm{c}}=2{\left(\frac{2\pi \cdot 0.8m_{\mathrm{e}}\cdot k_{\mathrm{B}}}{h^2}\right)}^{3/2}{T}^{3/2}$$

(12)

$$N_{\mathrm{v}}=2{\left(\frac{2\pi \cdot 1.2m_{\mathrm{e}}\cdot k_{\mathrm{B}}}{h^2}\right)}^{3/2}{T}^{3/2}$$

(13)

In (12) and (13), m_e is the electron mass, h is the Planck constant.

4.5.2. Threshold Voltage

Threshold voltage V_T is a temperature-sensitive parameter of SiC DMOSFET and it significantly influences the high-temperature behavior of the device. In this paper, modeling of the V_T is given in (14), which considers the fixed charges in gate oxide, the traps at the SiC/SiO₂ interface, and the correction of the surface potential in the flat-band voltage calculation [39].

$$V_{\mathrm{T}}=\left[\frac{{\Phi }_{\mathrm{MS}}}{q}-\frac{q{n}_{\mathrm{F}}}{C_{\mathrm{ox}}}-\frac{Q_{\mathrm{IT}}({\Psi }_{\mathrm{S}}=2 {\Psi }_{\mathrm{F}})}{C_{\mathrm{ox}}}\right]+2 {\Psi }_{\mathrm{F}}+2\sqrt{V_0{\Psi }_{\mathrm{F}}}$$

(14)

In (14), n_F is the density of the fixed charge at the SiC/SiO₂ interface; Φ_MS is the work function difference between the high-doped poly silicon gate and the P-type 4H-SiC at the channel. It can be defined as (15).

$${\Phi }_{\mathrm{MS}}={\Phi }_{\mathrm{M}}-\chi -\frac{E_{\mathrm{g}}}{2}-{\Psi }_{\mathrm{F}}$$

(15)

In (15), χ is the electronic affinity of 4H-SiC; Ψ_F represents the Fermi potential at the channel and it can be calculated using (16).

$${\Psi }_{\mathrm{F}}=\frac{k_{\mathrm{B}}T}{q}\ln \left(\frac{N_{\mathrm{CH}}}{n_{\mathrm{i}}}\right)$$

(16)

V₀ is a constant related to the material properties and the design of device and it is defined as (17).

$$V_0=\frac{q{\epsilon }_{\mathrm{SiC}}{N}_{\mathrm{CH}}}{C_{\mathrm{ox}}^2}$$

(17)

In (17), N_CH is the equivalent doping concentration of the channel.

As for Q_IT, the charge density of interface traps, is the key parameter influencing the value and high-temperature characteristics of V_T. It also has a significant influence on the channel electron mobility μ_CH. The modeling and calculation of it will be presented in the Appendix B.

4.5.3. Carrier Mobility

In SiC DMOSFET, the carrier mobility is one of the most important parameters affecting the electric conductivity and high-temperature characteristics. It is decided by multiple different physical mechanisms, and generally, it can be calculated using (18).

$${\mu }_{\mathrm{TOTAL}}^{-1}={\mu }_1^{-1}+{\mu }_2^{-1}+{\mu }_3^{-1}+\cdot \cdot \cdot$$

(18)

In (18): μ_TOTAL is the carrier mobility that considers several physical mechanisms; μ₁, μ₂, μ₃ are the ones affected by only one physical mechanism. In general, there are four types of physical mechanisms and the corresponding carrier mobilities that should be taken into consideration are bulk mobility (μ_B), acoustic-phonon scattering (μ_AC), surface roughness scattering (μ_SR), and Coulomb scattering at interface traps (μ_C). The above four kinds of carrier mobility can be calculated using (19)–(22) [22,39,58,59,60,61,62,63,64].

$${\mu }_{\mathrm{B}}={\mu }_{\mathrm{MIN}}+\frac{{\mu }_{\mathrm{L}}{\left(T/300\mathrm{K}\right)}^{-2.4}-{\mu }_{\mathrm{MIN}}}{1+{\left(\left(N_{\mathrm{CH}}+N_{\mathrm{DR}}\right)/N_{\mathrm{REF}}\right)}^{0.61}}$$

(19)

$${\mu }_{\mathrm{AC}}=\frac{K_1}{E_{\mathrm{NOR}}}+\frac{K_2{\left(N_{\mathrm{CH}}+N_{\mathrm{DR}}\right)}^{0.0284}}{T{E}_{\mathrm{NOR}}^{1/3}}$$

(20)

$${\mu }_{\mathrm{SR}}=\frac{{\Gamma }_{\mathrm{SR}}}{E_{\mathrm{NOR}}^2}$$

(21)

$${\mu }_{\mathrm{Cit}}=\frac{{\Gamma }_{\mathrm{Cit}}T}{N_{\mathrm{F}}+N_{\mathrm{IT}}}{\left(1+\frac{n_{\mathrm{INV}}}{n_{\mathrm{SCR}}}\right)}^{{\zeta }_{\mathrm{C}}}$$

(22)

In the above equations, μ_MIN, μ_L, μ_REF, K₁, K₂, Γ_SR, Γ_Cit, n_SCR, and ζ_C are the physics-based parameters used in carrier mobility calculation; the effective perpendicular electric field E_NOR and the interface inversion charge n_INV are calculated utilizing the charge sheet model [60,65]; the interface trapped charge n_IT is calculated with references to [22,66,67]. The models and calculations of them are complex works and, therefore, will be elaborated in the Appendix B.

In the channel of SiC DMOSFET, limited by the technology of manufacturing, the quality of the SiC/SiO₂ interface is poor, which has a great impact on the channel electron mobility μ_CH [39,66]. Thus, as given in (23), the calculation of μ_CH should consider all four aforesaid physical mechanisms.

$${\mu }_{\mathrm{CH}}={\left({\mu }_{\mathrm{B}}^{-1}+{\mu }_{\mathrm{AC}}^{-1}+{\mu }_{\mathrm{SR}}^{-1}+{\mu }_{\mathrm{Cit}}^{-1}\right)}^{-1}$$

(23)

Because the JFET region and N-type drift layer is inside of the 4H-SiC, only bulk mobility should be considered in the calculation of electron mobility μ_N in R_D calculation. Hence, as given in (24), μ_N is equal to μ_B.

$${\mu }_{\mathrm{N}}={\mu }_{\mathrm{B}}$$

(24)

5. Model Validation

In this section, the proposed model is validated via comparing simulation results with experimental results, including static characteristic tests, short-circuit fault tests and UIS tests. All simulations are performed in MATLAB/Simulink and the modeling object, C2M0080120D produced by Wolfspeed, is chosen as the device under test (DUT) in both test experiments to verify the correctness and accuracy of the proposed model.

5.1. Static Characteristics

To validate the accuracy of the static characteristics, output curves under 300 K of C2M0080120D are measured via Keysight B1506A (manufactured by Keysight Technologies, Santa Rosa, CA, USA), and the corresponding curves of the proposed model under different gate-source voltages are simulated. Figure 13 gives the comparison between measured and simulated curves. The simulated on-resistance under V_GS = 20 V and I_D = 20 A is 95.8 mΩ, whose relative error is 6.4%. The simulated threshold voltage is 2.894 V at T = 300 K and 2.414 V at T = 423 K, whose relative error is only 0.2% and 0.5%, respectively. The results indicate that the model can correctly simulate the key static characteristics of SiC MOSFET.

5.2. Short-Circuit Faults and Failures

To measure the behaviors of SiC DMOSFET in short-circuit faults, a short-circuit test experiment platform was built. Figure 14 gives the schematic circuit diagram: L = 231 nH is the stray inductance of the power loop; C_i = 35 nH and R_i = 4.7 kΩ are the input capacitance and resistance used to reduce gate oscillation; the gate resistance R_g equals 10 Ω for turning on and 20 Ω for turning off; the gate driver voltage is −5/+20 V. The room temperature is approximately 27 °C, so the T_CASE of SiC MOSFET is set to 300 K in the simulations. Figure 15 shows the test experiment platform, in which the load is replaced by a short wire for short-circuit test. The types and key parameters of instruments included in the platform are listed in

Table 2. Instruments used in short-circuit test experiment.

Instruments	Types	Parameters
DC power supply	Magna-Power XR6000	0~6000 V
Oscilloscope	Tektronix MSO58	500 MHz
Voltage probe	Tektronix THDP0100	6000 Vpk/600 Vpk
Current probe	CWTUM/06	120 A

.

Figure 16 reports the simulated and measured waveforms of the drain-source voltage U_DS and drain current I_D under the condition of V_DC = 400/500 V during a short-circuit pulse with a duration of 10 μs. The results show that the proposed model can accurately describe the short-circuit current that increases and then decreases. Also, the simulated peak current and the time to reach it are almost the same as the experimental results. These results can imply that the temperature characteristics of the channel electron mobility model, the drain resistances model, and the junction temperature calculation, are reasonable. Furthermore, it is worth noting that when V_DC = 500 V, the tail current can be directly observed, and the simulated tail current matches the experiments well. It can be seen that in the proposed model, the tail current is made up entirely of the leakage current I_LEAK, verifying that the calculation of I_LEAK is precise and the aforesaid composition of the tail current is correct. It also suggests that the cell-level physical basis of the short-circuit fault is correct. Figure 16a,b shows the results under different V_DC. In both conditions, the simulated waveforms match the experimental waveforms well, which validates the universality of the proposed model in different working conditions.

As provided in Figure 17, The U_DS and I_D waveforms are measured when short-circuit failure occurs under long-pulse short-circuit faults. Short-circuit failure occurs at 28.5 μs when V_DC = 400 V and at 15.5 μs when V_DC = 500 V. The simulated waveforms match the measured results accurately and the short-circuit withstand time of the model perfectly matches that of the experimental results in both working conditions, indicating that the proposed can precisely predict the thermal-runaway failure in SiC MOSFET’s short-circuit fault. Analyzing the composition of simulated I_D, compared with I_MOS, I_LEAK becomes non-negligible, which is the main cause of the thermal-runaway failure. This result can match the short-circuit failure mechanism shown in the physical basis.

In addition, the proposed model can also reveal the physical mechanisms behind some details of the measured results. In Figure 17a, there is an abnormal slight turn in I_D waveform at the moment t ≈ 13.6 μs. The proposed model can predict the inconspicuous phenomenon correctly and show the cause of it. The resistances of the N-type drift layer and JFET region increase with the increasing junction temperature, making the channel voltage drop. At the moment t ≈ 8.6 μs, the channel voltage is so low that the device transitions from the saturation region to the linear region. In the linear region, it is the continuous lowing of the channel voltage that causes the slight drop of I_D.

Figure 18 gives the simulated junction temperature T curves under the above four different working conditions. It is obvious that when the thermal-runaway failure does not occur, T begins to drop after V_GS returns to −5 V, but when thermal-runaway failure occurs, T rises faster because of the increasing I_LEAK. The positive temperature feedback is obvious in the junction temperature curves when thermal-runaway failure occurs, which proves the thermal-runaway failure mechanisms discussed in Section II.

5.3. Avalanche Breakdown Faults and Failures

Unclamped inductive switching (UIS) tests were performed to validate the model in avalanche breakdown fault. The schematic circuit diagram used for it can also be described in Figure 14 and the temperature conditions are the same. Compared with the short-circuit test platform, the inductance L here is a large load inductance, and there are several branches for protection between drain and source of the device. These branches can influence the dynamic responses of the device, but they do not change the physical processes of the avalanche breakdown faults in UIS test. Because the structure of these branches is complex, they are omitted in the circuit diagram, but they are carefully taken into consideration in the simulations. Figure 15 also shows the UIS test platform, in which the load is a line-frequency inductor for the UIS test.

Figure 19 displays U_DS and I_D waveforms measured in the UIS test under the condition of (a) L = 5.0 mH and the peak current I_peak ≈ 14.5 A and (b) L = 2.3 mH and I_peak ≈ 17.1 A, where the avalanche breakdown fault has occurred, but the thermal-runaway failure has not yet occurred. The simulated waveforms show great agreement with the measured results. It validates that the proposed model can correctly describe the working state changes in SiC MOSFET’s avalanche breakdown fault, and also implies that the aforementioned cell-level physical processes of avalanche breakdown fault are shown to be correct. When the avalanche breakdown is over, there is an oscillation in U_DS waveform, which is mainly caused by the parasitic capacitances of the protection branches between drain and source. They are considered in the simulations, so the simulated and measured results can show a high degree of consistency. It can be seen that during avalanche breakdown, the simulated drain-source voltage U_DS, that is, the breakdown voltage U_BR, shows excellent agreement with the experimental waveform, which demonstrates that the model selected to calculate the breakdown voltage is accurate in a wide temperature range.

As shown in Figure 20, under the condition of (a) L = 5.0 mH and I_peak ≈ 19.2 A, (b) L = 5.0 mH and I_peak ≈ 24.1 A, and (c) L = 2.3 mH and I_peak ≈ 25.1 A, avalanche failure occurs, and when avalanche breakdown is over, I_D does not drop to zero but begins to rise instead. In the proposed model, t_FD is set to 4.0μs for describing the undecided failure mechanism that occurs after the melting of source metal. The agreements between simulated and measured results validate that the proposed model can correctly describe the changes in working states during SiC MOSFET’s avalanche failure.

Table 3. Comparisons of the avalanche breakdown durations.

Working Conditions	Measured	Simulated	Error
L = 5.0 mH, Ipeak = 19.2 A	32.82 μs	32.75 μs	0.2%
L = 5.0 mH, Ipeak = 24.1 A	17.47 μs	18.05 μs	3.3%
L = 2.3 mH, Ipeak = 25.1 A	25.39 μs	25.80 μs	1.7%

gives the comparisons of the avalanche breakdown durations in three working conditions. The relative errors are very small in these working conditions, which verifies that the proposed model is universal in different conditions. It also suggests that using a short time t_FD to describe the undecided failure mechanism is advisable and it does not affect the model’s accuracy.

Figure 21 provides the simulated curves of junction temperature T in the above four working conditions. It is obvious that when the avalanche breakdown is over, the junction temperature will decrease whether the thermal failure occurs or not. It can be explained as follows. When thermal-runaway failure occurs, the current is concentrated at the hot spots at the active area of a die, which causes junction temperature to rise near hot spots. However, the temperature will decrease in other areas far from the hot spots because the currents flowing through them will decrease. Therefore, the results do not contradict the avalanche breakdown failure mechanisms discussed in Section 2.

In general, the critical avalanche energy E_AV is the key parameter to evaluate SiC MOSFET’s avalanche ruggedness [15,40]. In our experiments, several DUTs are tested under different L for measuring E_AV. Because measured E_AV exists in small differences between devices, the average value will be regarded as the reference value here.

Table 4. Comparisons between measured and simulated E_AV.

Working Conditions	Measured	Simulated	Error
VDC = 500 V, L = 5.0 mH	837.6 mJ	802.9 mJ	4.14%
VDC = 500 V, L = 2.3 mH	727.4 mJ	749.7 mJ	3.06%

provided the comparisons between measured and simulated E_AV under the condition of (a) V_DC = 500 V, L = 5.0 mH, and (b) V_DC = 500 V, L = 2.3 mH. The relative errors are less than 5%, indicating that the proposed model is able to precisely predict SiC MOSFET’s critical avalanche energy.

6. Conclusions

In this paper, a behavior model of SiC DMOSFET considering thermal-runaway failures in short-circuit and avalanche breakdown faults is presented. It is constructed based on cell-level physical mechanisms demonstrated through finite-element simulation and discussions on the existing studies. The models and parameters used in it are mostly physically based. To validate the proposed model, short-circuit and UIS test experiments are performed. In short-circuit and avalanche breakdown fault simulations, the model can simulate the current and voltage waveforms in different working conditions with extremely high consistency. In short-circuit fault simulation, the results indicate that it can accurately predict the short-circuit withstand time. In avalanche breakdown fault simulation, the model can accurately simulate the avalanche breakdown durations and the maximum relative error is only 3.3% in the experiments. Moreover, the proposed model can precisely predict the critical avalanche energy, in which the maximum relative error is 4.14%. The results indicate that the proposed model can accurately predict SiC MOSFET’s avalanche ruggedness.