Next-Generation Hybrid RF Front-End with MoS₂-FET Supply Management Circuit, CNT-FET Amplifiers, and Graphene Thin-Film Antennas

Abstract

One-dimensional (1D) and two-dimensional (2D) materials represent the emerging technologies for transistor electronics in view of their attractive electrical (high power gain, high cut-off frequency, low power dissipation) and mechanical properties. This work investigates the integration of carbon-nanotube-based field-effect transistors (CNT-FETs) and molybdenum disulphide (MoS₂)-based FETs with standard CMOS technology for designing a simple analog system integrating a power switching circuit for the supply management of a 10 GHz transmitting/receiving (T/R) module that embeds a low-noise amplifier (LNA) and a high-power amplifier (HPA), both of which loaded by nanocrystalline graphene (NCG)-based patch antennas. Verilog-A models, tuned to the technology that will be used to manufacture the FETs, were implemented to perform electrical simulations of the MoS₂ and CNT devices using a commercial integrated circuit software simulator. The obtained simulation results prove the potential of hybrid CNT-MoS₂-FET circuits as building blocks for next-generation integrated circuits for radio frequency (RF) applications, such as radars or IoT systems.

1. Introduction

Among recent nanotechnology-based integrated circuits, one-dimensional (1D) and two-dimensional (2D) materials have been identified by the scientific community as the most promising solutions for future electronics, such as next-generation radars and wireless telecommunication applications. Indeed, they both offer scalability potential well beyond that of silicon and all other conventional semiconductors.

In detail, 2D materials such as graphene or transition metal dichalcogenides (TMDCs), e.g., molybdenum disulphide (MoS₂), hafnium disulphide (HfS₂), and tungsten diselenide (WSe₂), have gained increasing interest as transistor channel materials in digital applications thanks to their atomic scale thicknesses and suitable bandgaps, which are highly desirable properties for low-power FETs that can be utilised in back-end-of-line non-volatile memory and logic applications to augment conventional silicon technology in the future sub-5 nm tech nodes [1,2,3,4,5,6,7,8,9,10,11].

At the same time, 1D materials, such as carbon nanotubes (CNTs) deployed in variable capacitors for tunable microwave filters [12] or as channel material for building CNT-based field-effect transistors (CNT-FETs), have demonstrated to be well suitable for mixed-signal and RF applications with respect to both conventional bulk semiconductors and 2D materials [13,14,15,16,17,18]. This is due to the fact that the 1D transport mechanism in CNTs leads not only to a low scattering rate and high current-carrying capability but also, under some conditions, to a linear $I_{\mathrm{D}}$–$V_{\mathrm{GS}}$ characteristic [19,20,21], as it was also confirmed by electromagnetic and quantum simulations that are supposed to mimic the actual technology used for circuit manufacturing, as carried out in [22], where a compact CNT-FET model was derived. This I–V behaviour could be considered an advantage in future mobile communication systems, where increasingly complex modulation techniques are expected to be used, e.g., in radars or cutting-edge Internet-of-Things (IoT) applications [23].

The implementation of a transmitting/receiving module (T/R) using 1D and 2D materials at 10 GHz is a real challenge. A T/R module implies at least an antenna connected to (i) a high-power amplifier (HPA) for the transmitter side and (ii) a low-noise amplifier (LNA) for the receiver side. These two functions are monitored by a power management module, whose principal function is to disconnect inactive circuits to minimise the power dissipation. The implementation of such circuits implies the utilisation of different 2D materials, depending on their specific physical properties at microwaves and the possibility to grow them at the wafer scale. In this paper, we have used a nanocrystalline graphene (NCG)-based patch antenna at 10 GHz, the NCG thin film having a thickness of 110 nm and a bulk conductivity of 16,000 S/m, thus much thinner than any metal used for metallic antennas to prevent skin depth effects. The NCG-based patch antenna can be grown at the wafer scale on SiO₂ thermally grown on a 4-inch high-resistivity silicon (HRSi) wafer. Excellent performance has already been obtained with such antennas in array configuration at 24 GHz [24]. However, the amplifiers cannot be fabricated using graphene monolayers or thin films, since the reproducibility of the circuits is still an unsolved problem. The state of the art is an amplifier at 10 GHz with a gain of 4.2 dB [25], selected out of other thirteen devices and showing a wide variation of its main key performance indicators. Therefore, in this manuscript, we used FETs based on aligned semiconducting CNT arrays, thanks to (i) their high reproducibility when they are grown on SiO₂/HRSi wafers and (ii) their low contact resistance [26]. CNTs are folded graphene nanomaterials, and FETs based on them exhibit very good performance at microwaves [27] up to 100 GHz [28] and have already proved to be good candidates to build RF amplifiers [29,30,31,32,33]. Yet, the very properties that make CNT-FETs promising for RF applications, such as their excellent linearity, make them not very suitable for power switching applications, as those needed in the power management block, since it is essentially a DC unit. For it, a high-side power switching circuit based on MoS₂-FETs, since they show an impressive on/off ratio [34] and are low-power transistors [35], seems more appropriate and was indeed designed and included in the performed simulations.

This paper is organised as follows. Section 2 is dedicated to describing the whole system architecture together with details of the design of its sub-blocks, namely the supply management circuit using MoS₂-FET as power switches, the CNT-FET HPA, and the CNT-FET LNA, both loaded by an NCG-based patch antenna. In Section 3, the simulation results of the whole hybrid system are reported and discussed. Finally, Section 4 concludes the work and gives details about future research and perspectives.

2. System Implementation

The entire T/R module is represented schematically in Figure 1.

It is composed of two independent chains. The RX chain starts with the receiving patch antenna that feeds the LNA, whose power can be cut off when not needed by the high-side switch in the power management circuit. Similarly, the TX chain starts with the HPA that feeds the transmitting patch antenna, and another high-side power switch controls the amplifier operation. This dual antenna configuration avoids the necessity of an RX/TX RF switch and its associated losses.

The RF systems’ performance mainly depends on their front-end amplifiers, e.g., the LNA and HPA. So far, only very few CNT-FET RF amplifiers have been manufactured. The first amplifiers with reasonable gain above 1 GHz were published in [36] and, in the last year, prototypes of RF amplifiers up to 18 GHz have been constructed in [37]. The design of these building blocks is usually implemented through circuit simulators that use compact models representing the actual devices on a given technology. Once the device compact models have been validated through actual experimental measurements, an excellent agreement between physical circuit performance and simulation results should be expected. With this considerations in mind, we designed both the LNA and HPA using the widely acknowledged Stanford CNT-FET model, which was tuned to our technology and to which a noise model was added as in [30].

In the following, a detailed discussion of the design and models used for the different parts is given.

2.1. MoS₂-FET Power Controller

MoS₂-FET devices exhibit interesting characteristics that should make them ideally suited to build relatively low-speed (with respect to the RF transistors) but higher-efficiency power switches. They were thus used to selectively cut the power to the RF amplifiers, so that the LNA and HPA can individually be enabled or disabled according to the requirements of the protocol/application.

In order to design a power switching circuit, including its driving components, we used the Stanford 2D semiconductor (S2DS) transistor model [38] for the MoS₂ power transistors to describe their static voltage/current relationship. The S2DS model is a physics-based and data-calibrated model with a freely available Verilog-A implementation [39] suitable to be directly incorporated into standard design tools, and it is derived using a semiclassical drift transport approach that takes into consideration the density of states in the semiconductor, impurities, and traps, but not the diffusion currents, and so leakage will be underestimated. Moreover, although the S2DS model includes some parasitic capacitance effects, given the low activation/deactivation frequency of the power control circuit, basically DC, we can neglect the behaviour of the parasitic capacitances of the transistors, as the dynamic performance of the switch will be dominated by the bypass capacitors on the supply lines of the amplifiers it powers, as will be seen in Section 3.

For our power switching needs, the S2DS model main parameters, namely the sizes W and L, threshold $V_{\mathrm{T}}$, and the two parasitic resistances due to contacts ($R_{\mathrm{C}}$) and leakage ($R_{\mathrm{L}}$), were adjusted to match what is expected from higher-current devices, as listed in Figure 2a. $R_{\mathrm{L}}$ was actually added to the the S2DS model, and it represents a resistance in parallel between the drain and source terminals introduced to model the leakage that can be expected from such larger devices. These parameters yield the voltage characteristics shown in Figure 2b. With these devices, higher drain voltages than those shown might cause breakdown and should be avoided.

Taking into consideration the fact that these FETs need a negative gate voltage to be turned off and are limited on the maximum $V\mathrm{DS}$ voltage, and the amplifiers, as will be shown later, need a 1.5 V supply voltage, we designed a gate drive circuit to bias the power FETs based on a voltage shifter (to adapt the logic control signal to the gate drive requirements) and a discrete inverter to control the output discharge transistor, as seen in the highlighted dashed red box in Figure 3, where the complete schematic of the power switching circuit is reported. The power components of the circuit, M₁ and M₂, are, respectively, a power MoS₂-FET pass element that should interrupt the current to the load and an output discharge MoS₂-FET that drains to ground the pass element leakage current and helps to quickly discharge the load capacitance.

As derived from simulations, the required gate voltage swing for optimum operation of the MoS₂ devices is about from $-1$ V to $+2$ V, which exceeds their maximum drain voltage handling capability. We thus chose to build the gate drive circuit using standard off-the-shelf MOSFET components, which also allows greater flexibility in the final optimisation of the whole system. Considering the current handling capability, the system has been designed to deliver a supply voltage $V_{\mathrm{DD}}=+1.5$ V to the amplifiers from a global $V_{\mathrm{SUPPLY}}=+2.0$ V power supply (which corresponds to the maximum blocking voltage of these MoS₂-FETs), with a drop $V_{\mathrm{DS}}=V_{\mathrm{SUPPLY}}-V_{\mathrm{DD}}$ across the MoS₂-FET. This shall enable the reference transistor to sustain around 4 mA of current if biased with the maximum $V_{\mathrm{GS}}$, but such a high voltage is not easily achievable. Indeed, we can assume to use a $V_{\mathrm{CC}}=3\mathrm{V}$ logic system for the digital signals, and drive the M₁ gate with the same voltage to limit the number of power rails in the system. This leads to a driving voltage $V_{\mathrm{GS}}=V_{\mathrm{CC}}-V_{\mathrm{DD}}=1.5\mathrm{V}$, which yields (according to the simulations shown before) an $I_{\mathrm{D}}@{\mathrm{V}}_{\mathrm{DS}}=0.5\mathrm{V}=3.41\mathrm{mA}$, and M₁ must then be scaled so that its $I_{\mathrm{D}}$ matches the DC current drawn by the load (amplifiers) as determined in the next section, plus the leakage of M₂.

Having sized the MoS₂ FETs, it is easy to size the rest of the circuit. The driving circuit must be designed to provide the gate voltages for the high-side power switch M₁ ($V_{\mathrm{HI}}$) and the low-side discharge FET M₂ ($V_{\mathrm{LO}}$). $V_{\mathrm{HI}}$ should swing from $-1\mathrm{V}$ (OFF) to $+3\mathrm{V}$ (ON), while $V_{\mathrm{LO}}$ should swing from $+2\mathrm{V}$ (OFF) to $-1\mathrm{V}$ (ON).

This is achieved by M_D1, which acts as a voltage translator that lowers the digital low level at the input $V_{\mathrm{CTRL}}$ from 0 V to $-V_{\mathrm{NN}}=-1$ V, while allowing the high level to pass through unaltered, so that the high level on $V_{\mathrm{HI}}$ equals the digital supply $V_{\mathrm{CC}}$. $V_{\mathrm{LO}}$ is then obtained by inverting $V_{\mathrm{HI}}$, and its high level is set by the resistor divider R_D2/R_D3 to $+2$ V so that $V_{\mathrm{PP}}$ can be connected to the same rail as $V_{\mathrm{CC}}$ since $V_{\mathrm{LO}}^{\mathrm{H}}=-V_{\mathrm{NN}}+(V_{\mathrm{PP}}+V_{\mathrm{NN}})R_{\mathrm{D}3}/(R_{\mathrm{D}2}+R_{\mathrm{D}3})=+2$ V simply imply $R_{\mathrm{D}3}=3R_{\mathrm{D}2}$.

A simulation of the whole circuit is shown in Figure 4, which also reports the output voltage driven to loads corresponding to the DC current consumption of the RF amplifiers. To achieve that, i.e., 6.67 mA for the HPA, an M₁ 2.1 times the reference FET is needed (accounting for leakages), whereas an M₁ 6.0 times the reference FET is required to drive the 20 mA needed by the LNA.

2.2. CNT-FET Amplifiers

As previously stated, CNT-based transistors have interesting properties in terms of linearity and mobility that make them particularly well-suited for high-frequency amplifier realisation. We thus designed both the LNA and HPA for the T/R module with this type of transistors, using the Verilog-A implementation [40] of the Stanford CNT-FET model [41,42] for the simulations, with parameters tuned to the technology that is being developed to build these devices, and with an added noise model as in [30].

As an indication of the type of performance we can expect from these transistors, Figure 5 reports the output characteristics of the FET used as the input stage of the LNA. Its transition frequency $f_{\mathrm{t}}$, simulated using the intrinsic capacitances included in the Stanford model, was found to be around 45 GHz.

In the design of the CNT-FET HPA we chose to employ a cascode configuration because it combines the high gain of a common-source (CS) topology with the higher operating frequencies of the common-gate (CG) topology, and therefore it is of interest in RF applications. The schematic of the proposed CNT-FET HPA is shown in Figure 6.

More in detail, the cascode topology formed by transistors M₁ and M₂ helps to reduce the Miller effect of M₁ and to obtain excellent reverse isolation, high gain, and improved stability. The degeneration inductor L₂ at the source of M₁ is used to provide the input resistive impedance without physical resistor for optimum matching. However, increasing the value of L₂ reduces the gain of the amplifier. The value of L₂ in this design is set at 195 pH. For the inductors, we designed the circuit with the conservative assumption that the technology with which it will be implemented allows the realisation of inductors with a quality factor Q of at least 10. The CNT-FETs M₁ and M₂ are chosen with the same geometry consisting in a channel width W of 200 µm and channel length L of 200 nm.The power consumption is designed to be 10 mW from a 1.5 V power supply.

The input-matching network was designed by adding the series of C₁ and L₁ to match the 50 $\mathsf{\Omega }$ resistance. The output is loaded with an inductor L₃ of 800 pH to increase the gain at 10 GHz. The output-matching network to 50 $\mathsf{\Omega }$ was designed by using L₃, C₂, L₄, and C₃. The resistor R₁ provides the M₁ DC gate bias.

Two typical architectures, the CS and CG topologies, are usually adopted for the design of the first stage of an LNA due to the input-matching and noise characteristics of the circuit. A wideband input matching could be provided by the CG topology at the expense of high noise figure (NF) [43]. The advantage of the CS topology consists in higher gain, but compromises need to be made between gain and broadband input matching.

With these considerations in mind, we chose to employ a cascode LNA because it combines the high gain and low NF of a CS topology with the higher operating frequencies of the CG topology, and therefore it is of interest in RF applications. In this particular application, we used a resonant load for the cascode amplifier because it is important to increase the first stage gain to minimise the overall noise figure. Because of the very high resistance of the resonant load, we added an output common drain stage to help match this to the 50 $\mathsf{\Omega }$ output load. The schematic of the CNT-FET LNA is shown in Figure 7.

The CNT-FETs M₁ and M₂ of the first stage are chosen with the same channel width $W=100$ µm and channel length $L=200$ nm. For the second stage, an M3 transistor of $W=400$ µm and $L=200$ nm was chosen. The power supply is designed to be a 1.5 V. The input-matching network was designed by adding the series of C₁ and L₁ to match the 50 $\mathsf{\Omega }$ resistance. The resistors R₁ provides the DC gate bias for M₁. The interstage matching was implemented through L₄ along with the load inductor L₃ optimised to increase the gain at 10 GHz. The resistors R₂ and R₃ were added for stability purposes. The second stage, represented by the transistor M₃ in common-drain configuration, was designed along with the matching network L₅, C₃, and L₆ to adapt the output to 50 $\mathsf{\Omega }$.

2.3. NCG-Based Patch Antenna

In order to simulate a realistic T/R module, at least an antenna is necessary for both the transmitter and the receiver side. The validation of the proposed concept of hybrid integration of 1D and 2D materials into a 10-GHz front-end can be achieved by considering two single NCG-based patch antennas, one connected to the CNT-FET HPA (in transmitting mode) and one connected to the CNT-FET LNA (in receiving mode), as displayed in Figure 1. A more sophisticated solution will comprise a full antenna array, which also allows increasing the overall gain (taking into account that NCG-based antennas exhibit a radiation efficiency around 30%).

For this purpose, we started from the fabrication and experimental characterisation of NCG thin films. The deposition was performed by means of a Plasma-Enhanced Chemical Vapour Deposition (PECVD) process using a NANOFAB 1000 (Oxford Instruments, Bristol, UK) as equipment. The HRSi/SiO₂ 4-inch wafer was covered by NCG using a methane–hydrogen plasma at 900 °C. Then, the electrical characterisation was performed with the four-point probe (4PP) method, based on 4 aligned electrodes: a current is passed through the two outer probes, and the voltage through the two inner probes is measured, allowing the measurement of the sheet resistance. The measured sheet resistance was 579 $\mathsf{\Omega }$, from which the thickness of the film was estimated to be approximately 110 nm, whereas the bulk resistance was 6.2 M$\mathsf{\Omega }·$cm, which is equivalent to a conductivity of about 16,150 S/m. The Raman spectroscopy showed that the D band/G band intensity peak ratio I_D/I_G is within the interval 1.5–2.5, which is a proof of the nanocrystalline nature of the material.

The next step was the electromagnetic (EM) simulation of the NCG-patch antenna at 10 GHz using the 3D EM tool CST Microwave Studio, in which the measured electrical characteristics of the NCG thin film were deployed to properly model the material. The results of the simulation are reported in Figure 8. In particular, the 3D layout is displayed in Figure 8b: the patch has overall dimensions of 10 mm × 10 mm, whereas the NCG layer has a width of 5 mm and a length of 4.2 mm. The SiO₂/HRSi substrate has a thicknesses of 300 nm/525 µm, respectively, whereas the gold metallisation has a thickness of 500 nm. The chosen configuration is in coplanar waveguide (CPW) technology for (i) ease of integration with the other components of the T/R module, (ii) straightforward on-wafer measurements, and (iii) simple DC biasing of the NCG layer [24]. Figure 8a presents the resulting 2D gain of the antenna as a function of the polar coordinates $\theta$ and $\varphi$, where $\theta$ is defined in the $(x,z)$ plane and $\varphi$ is defined in the $(x,y)$ plane: the maximum (in the broadside direction) is about $-2.6$ dB, which corresponds to a maximum radiation efficiency of about 16%. Finally, Figure 8c shows the reflection coefficient $S_{11}$ in the X band (i.e., 8–12 GHz), exhibiting a clear resonance around 10 GHz, with $S_{11}=-17.96$ dB and a $-10$ dB-bandwidth of 570 MHz (or, equivalently, a $-10$ dB-relative bandwidth of 5.7%).

3. Simulation Results

To validate the correct operation and overall performance of the whole system thus designed, several linear, non-linear, and transient simulations were performed. However, before the simulations of the whole system, each individual block was characterised individually, to verify that the system integration does not significantly degrade their performance. Each sub-circuit schematic was thus captured using Cadence Virtuoso^® version 6.1.8.210 and simulated using Spectre^® version 20.1.0.298. The Verilog-A models of the CNT-FETs and MoS₂-FETs were downloaded from [39,40] and adapted to our needs, as thoroughly described in the previous section. The antenna was simulated in CST Microwave Studio 2014, and its $S_{11}$ scattering parameters imported into Virtuoso through a Touchstone .s1p data file as a 1-port element, so that the amplifiers see a realistic frequency-dependent load.

Starting from the transmit chain, the scattering parameters of the isolated HPA are shown in Figure 9a, from which it can be seen that a gain of over 10 dB is achieved in the band of interest, while providing good matching at the input and output ports. As expected, the cascode configuration provides very good reverse blocking performance, with an $S_{12}$ well below $-30$ dB.

As far as the output power delivering capability is concerned, Figure 9b shows the input-referred 1 dB compression point. The output power is somewhat limited by the available supply voltage, which restricts the voltage swing of the output device. Nevertheless, about 0 dBm of power can be delivered to the load at the onset of distortion, which corresponds to a drain efficiency of around 10% in linear operation.

A summary of the achieved HPA performances is shown in

Table 1. Performance comparison of the designed HPA with other works.

Reference	[44]	[45]	[46]	[47]	[48]	[49]	This Work
Node	200 nm	150 nm	100 nm	100 nm	40 nm	28 nm	90 nm
Technology	GaN-on-SiC	GaN-on-SiC	GaN-on-Si	GaN-on-Si	CMOS	CMOS	CNT-FET
Data	Meas.	Meas.	Meas.	Meas.	Meas.	Meas.	Sim.
BW (GHz)	17.2–20.2	18.5–24	17–20.5	17–20.5	26.9–33.2	19.7–38.9	8.7–11.3
Pout (dBm)	40	36.5	40	40.4	17.8	16.2	3.0
Gain (dB)	20	25	24	23	14.8	18.1	10.3
PAE (%)	38	40	30	33	30.7	27.3	10

, together with a comparison with those obtained by similar works that focus on HPAs made with conventional GaN-based or CMOS standard technologies, since to the best of our knowledge there are not yet any other published results of CNT-based HPAs.

As can be seen, the performances of the CNT-FET HPA are not yet competitive with those obtained by more mature technologies such as CMOS and GaN. Indeed, the CNT technology can be considered still in its infancy compared with the CMOS one, and 1D devices might, due to their peculiar conduction structure, perform less than optimally in higher-power applications.

The behaviour of the whole system, specifically including the power management circuit to which the actual amplifier acts as the load, and with the antenna $S_{11}$ model connected to the amplifier output with a 204 pH inductor for impedance matching, was simulated as well. To achieve this, a transient simulation was performed, whose results are shown in Figure 10. Here, the system starts in the OFF condition, with the power manager disabled. The bias and supply voltages are not zero because of the leakage of the MoS₂-FET pass element but are low enough to keep the amplifier transistors below threshold. At 1 µs the power manager is enabled, causing the supply and bias voltages to ramp up. The bias voltages are indeed obtained from the supply rail through a simple resistor divider network, with bypass capacitors to shunt the RF signal. The turn-on time is thus dominated by the charging time of those bypass capacitors, and can be tuned to the application requirements by adjusting the divider network resistance (at the expense of increased static power consumption). After the voltages reach a stable state, a 100 mV RF signal source is activated that produces an output power of around $-1.2$ dBm. The turn-off transient was then simulated as well, this time keeping the RF source activated to verify the isolation capabilities of the amplifier in its OFF state. It is apparent that the power delivered to the antenna immediately drops by about 25 dB, whereas the amplitude of the input signal increases as the input transistor is debiased and so reflects back most of the incoming power.

Other simulations were performed for the LNA, too, whose scattering parameters are shown in Figure 11a, from which it can be seen that a gain of over 28 dB is achieved in the band of interest, while providing good matching at the input and output ports. As expected, the cascode configuration provides very good reverse blocking performance, with an $S_{12}$ well below $-40$ dB. The 1 dB compression point, as shown in Figure 11b, is a bit low but adequate for the input stage given its high gain. The simulated noise figure is reported in Figure 12a, and it is below 1.2 dB around 10 GHz.

A summary of the achieved LNA performance is shown in

Table 2. Performance comparison of the designed LNA with other works.

Reference	[50]	[51]	[43]	[36]	[31]	[30]	This Work
Node	65 nm	65 nm	130 nm	450 nm	32 nm	90 nm	90 nm
Technology	CMOS	CMOS	CMOS	CNT-FET	CNT-FET	CNT-FET	CNT-FET
Data	Meas.	Sim.	Sim.	Meas.	Sim.	Sim.	Sim.
BW (GHz)	1–20	0.03–3	0.1–5	1–1.2	3–38	0.01–2.5	9.75–10.25
Supply (V)	1.6	1.2	1.2	2.5	1.0	2.0	1.5
Power (mW)	20.3	5.7	4.4	N/A	16	18	30
Gain (dB)	12.8	11.6	20	11	13.7–14.7	27.5	28.4
NF (dB)	3.3–5.3	2.7–3.32	3.04–3.97	8	0.4–1.3	1.0	1.2

, together with a comparison with those obtained by similar works that focus on LNAs made with CNT-FETs, also taking into account some results related to conventional CMOS LNAs.

In particular, with respect to the three CNT-FET LNAs reported in the table, our architecture has the highest gain. The high gain also helped in achieving a low NF, of the same order as the CNT-FET LNAs reported in the table, and at a comparable power dissipation level, and much lower than the CMOS alternatives due to the intrinsic lower noise of the carbon nanotubes versus standard CMOS transistors.

Finally, as regards the NCG-based patch antenna, a thorough comparison was conducted in [24], which highlights its capabilities of providing a simple yet effective reconfigurability of its gain, together with a high fabrication yield and the possibility of tuning the electrical characteristics of the NCG layer by optimising its growth process.

The whole system simulation was also performed in this case, attaching the simulated antenna at the input of the LNA and powering the amplifier through the power switching circuit. A 5 µA current at 10 GHz is considered as the equivalent current source of the incoming radiation at a few meters from the transmitter (by using the well-known Reciprocity theorem), and the noise sources of all the active components and bias resistors were taken into account. The resulting output voltage spectrum is reported in Figure 12b, from which the amplified signal’s first and second harmonics can easily be seen above the noise floor. The overall gain of the whole system results in about 26 dB, which is very similar to the 28 dB obtained by simulating the LNA alone.

4. Conclusions

In this paper, the integration at the design level of different state-of-the-art 1D and 2D nanomaterials with standard silicon CMOS technology for the next generation of RF applications was investigated and simulated. One-dimensional and two-dimensional materials are still in their infancy with respect to the technological maturity of silicon-based electronics, which have approached or already reached their theoretical limits in many aspects. On the contrary, nanomaterials represent a still emerging branch, with a huge potentiality to implement new functionalities and improve their performance. Moreover, a translation of their properties at the macro-scale is always desirable for the practical realisation of components working in the microwave range. Hence, a modular approach envisaging the optimisation of a specific 1D- or 2D-material-based device could be of great help to oversee the potentialities and constraints of each nanomaterial. For all these reasons, in this work, we propose the integration of a proof-of-concept 10 GHz transmitting/receiving module, comprising a power switching circuit for the supply management, a low-noise amplifier, and a high-power amplifier, both designed using CNT-FETs for which the model parameters were tuned from the blueprint and technology data of prototyping devices. In order to complete this T/R module, two nanocrystalline graphene-based patch antennas were used to load or feed the amplifiers.

The obtained simulation results of the overall framework demonstrate that the optimisation of the performance of each part of the T/R module, based on CNT-MoS₂-FET hybrid circuits, gives an added value to the performance of modern RF applications, such as radars or IoT systems where low power, high frequency, small size, low weight, and mechanical flexibility are often desired but not always possible when exploiting conventional CMOS technology. Indeed, the designed CNT-FET LNA, despite the infancy of the CNT technology for which it was tuned, already exhibits a very good performance: a gain of over 28 dB with a noise figure of just 1.2 dB. This performance is in line with other published CNT-based LNAs and much better than the referenced CMOS-based LNAs, proving the advantage of using 1D materials for critical amplification tasks. On the other hand, the CNT-FET HPA we were able to design, with a gain just above 10 dB and an output power of 3 dBm at saturation, is not on par with standard CMOS technology or more advanced technologies such as GaN-on-Si or GaN-on-SiC. This can be ascribed to the fact that the 1D technology is in its early stages. After all, this is, to the best of our knowledge, the first attempt at making an HPA out of CNT-based transistors, and knowing its limitations can still be useful.

Finally, the proposed technique also offers a comprehensive view of the capabilities of a multi-domain approach to multi-physics problems (time, frequency, and nano- and macro-scale), which are harmonised into a circuit model with scalable characteristics and reliable outputs in terms of global system performance.