New Resistor-Less Electronically Controllable ±C Simulator Employing VCII, DVCC, and a Grounded Capacitor

Abstract

In this paper, a new realization of electronically controllable positive and negative floating capacitor multiplier (±C) is presented. The peculiarity of the presented topology is that, for the first time, it implements a floating equivalent capacitor between its two input terminals, rather than a grounded one. To achieve the best performance, we simultaneously use the advantages provided by the current conveyor and its dual circuit, the voltage conveyor. The proposed topology is resistor free and employs one dual-output second-generation voltage conveyor (VCII^±) and one electronically tunable differential voltage current conveyor (E-DVCC) as active building blocks (ABBs) and a single grounded capacitor. The value of the simulated capacitor is controlled by means of a control voltage V_C which is used to control the current gain between X and Z terminals of E-DVCC. The circuit is free from any matching condition. A complete non-ideal analysis by considering parasitic impedances as well as non-ideal current and voltage gains of the used ABBs is presented. The proposed circuit is designed at the transistor level in 0.18 µm and ±0.9 V supply voltage. Simulation results using the SPICE program show a multiplication factor ranging from ±10 to ±25.4 with a maximum error of 0.56%. As an example, the application of the achieved floating capacitor as a standard high pass filter is also included.

1. Introduction

The advantages of capacitance multipliers in realizing large value capacitors in the CMOS process regarding the cost and chip size reduction are well known [1,2,3,4,5,6]. Capacitance multipliers find wide use in applications requiring large time constants, such as low-frequency filters in biomedical applications. In recent years, capacitor multiplier implementation has become a more important topic and several techniques have been developed to realize capacitor multipliers [7,8,9,10,11,12,13,14,15,16,17,18,19]. The feature of electronic tuning is considered a great advantage because it gives suitable tuning of filters, oscillators, and other circuits employing the simulated capacitor. Based on the intended application, simulated capacitors can be either grounded or floating.

Literature survey shows that various active building blocks (ABBs) have been used to develop floating capacitance multipliers [7,8,9,10,11,12,13,14,15,16,17,18,19,20,21]. The used ABBs are mainly the second-generation current conveyor (CCII) [22,23], current-controlled differential difference current conveyor (CCDDCC) [24,25], current follower transconductance amplifier (CFTA) [26], voltage current gain controlled second-generation current conveyor (VGC-CCII), dual output second-generation current conveyor (Do-CCII) [27], current-controlled second-generation current conveyor (CCCII), differential voltage current conveyor (DVCC), multiple output DVCC(MODVCC), differential voltage current conveyor transconductance amplifier (DVCCTA), operational transconductance amplifier (OTA), and flipped voltage follower (FVF) [28]. However, the previous implementations of floating capacitors in [7,8,9,10,11,12,13,14,15,16,17,18,19] suffer from several drawbacks. For example, the circuit reported in [7] employs two OTA, one CCII, and one resistor, and the achieved floating capacitor shows a high error. The power consumption of the circuits reported in [9,11,12,13,17] is high. The solution reported in [9] uses five CFTA and the one reported in [19] requires four OTA. The circuits reported in [12,13,15,17,18,20,21] lack electronic tuning capability. In the circuits reported in [10,14,17,18,21], a floating capacitor is employed. More importantly, in [17], two floating capacitors are used which must be well matched. Even worse, in [18], four floating capacitors are used, and matching is required between these four capacitors.

Recently, the application of a second-generation voltage conveyor (VCII) [29,30,31] as the dual circuit of CCII has been investigated in realizing impedance simulators [2,32,33,34]. In particular, in [2,33], its application in simulating grounded capacitor multiplier is shown, where the VCII-based grounded capacitors outperform the previously reported works in many terms.

In this paper, we intend to use the intrinsic capabilities of VCII in designing high-performance floating capacitor multipliers. To this aim, we introduce a new topology to implement a floating capacitor using a dual output VCII, an electronically controllable DVCC (which we call E-DVCC), and a grounded capacitor. In order to have an electronic tuning capability, the current gain between the X and Z terminals of E-DVCC is controlled using a control voltage, V_C. Employing both VCII and DVCC in the proposed topology, the benefits of voltage conveyors and current conveyors are combined to achieve the desired properties of floating capacitance multiplication, low-voltage low-power operations, reduced associated parasitic elements, electronic tunability, low error, no matching condition, and simple circuitry. Both positive and negative multiplications can be implemented by the proposed circuit. A complete non-ideal analysis is given, and the SPICE simulation results are reported. The application of the proposed floating capacitor as a standard high pass filter is also given, as an application of study.

The organization of this paper is as follows: in Section 2, the proposed circuit is introduced; in Section 3, non-ideal analysis is performed; Section 4 shows the implementation of the active blocks; Section 5 includes the simulation results; and finally, Section 6 concludes the paper.

2. The Proposed VCII-Based Floating ±C Multiplier

The proposed VCII-based floating +C multiplier is shown in Figure 1. It is composed of one VCII^±, one E-DVCC, and a single grounded capacitor. Here, we use the intrinsic potential of voltage conveyors and current conveyors to achieve a high-performance floating capacitor multiplier. In the E-DVCC, the current gain between the X and Z terminals can be regulated by the voltage V_C which allows us to electronically control the value of simulated +C. Consequently, as it will be shown, the value of the simulated floating capacitor can be varied by V_C.

In the following, we perform the analysis of the proposed circuit: operation the VCII^± is ideally expressed by the equations:

$$\left[\begin{array}{c}{I}_{X+}\\ I_{X-}\\ V_{Z+}\\ V_{Z-}\\ V_Y\end{array}\right]=\left[\begin{array}{cccc}1& 0& 0& 0\\ -1& 0& 0& 0\\ 0& 1& 0& 0\\ 0& 0& 1& 0\\ 0& 0& 0& 0\end{array}\right]\left[\begin{array}{c}{I}_Y\\ V_{X+}\\ V_{X-}\\ I_Z\end{array}\right]$$

(1)

while the following matrix represents the ideal operation of E-DVCC:

$$\left[\begin{array}{c}{V}_X\\ I_{Y1}\\ I_{Y2}\\ I_Z\end{array}\right]=\left[\begin{array}{cccc}1& -1& 0& 0\\ 0& 0& 0& 0\\ 0& 0& 0& 0\\ 0& 0& K& 0\end{array}\right]\left[\begin{array}{c}{V}_{Y1}\\ V_{Y2}\\ I_X\\ V_Z\end{array}\right]$$

(2)

Being K, the tunable current gain between the X and Z terminals. Using Equation (3a,b) for V_Z+ and V_Z− we have:

V_Z+ = V₁,

(3a)

V_Z− = V₂,

(3b)

where V₁ and V₂ are the input voltages. Using (2) and (3a,b) the voltage across C is:

V_X = V_Y1 − V_Y2 = V₁ − V₂

(4)

From Equation (4), the produced current across C is found as:

I_C = sCV_X = sC(V₁ − V₂)

(5)

The current produced across C is conveyed to the E-DVCC Z terminal while it is amplified by the gain of K as follows:

I_Z = KI_C = sKC(V₁ − V₂)

(6)

As the Z terminal of E-DVCC is directly connected to the Y terminal of VCII^±, we have I_Y = I_Z. According to Equation (1), the current at Y terminal of VCII^± is conveyed to the X+ and X− terminals by gains of (+1) and (−1), respectively, so for I₁ and I₂ we have:

I₁ = I_X+ = sKC(V₁ − V₂)

(7a)

I₂ = I_X− = −sKC(V₁ − V₂)

(7b)

From Equation (7a,b), the input impedance is found as:

Z_in = 1/sKC

(8)

From which the equivalent capacitor is ideally:

C_eq = KC

(9)

Figure 2 shows the realization of a floating negative capacitance simulator where, differently from Figure 1, Z+ and Z− terminals of VCII^± are respectively connected to Y₂ and Y₁ terminals of the E-DVCC. For Figure 2, it can be easily shown that the equivalent floating capacitor is ideally given

C_eq = −KC

(10)

3. Non-Ideal Analysis

Figure 3 shows a more detailed representation of the used ABBs showing the parasitic impedances associated with each port of VCII^± and E-DVCC. In non-ideal conditions, by considering these non-idealities, the operation of VCII^± is expressed by the following matrix:

$$\left[\begin{array}{c}{I}_{X+}\\ I_{X-}\\ V_{Z+}\\ V_{Z-}\\ V_Y\end{array}\right]=\left[\begin{array}{cccc}{\beta }_{v1}& \frac{1}{r_{X+}}& 0& 0\\ -{\beta }_{v2}& 0& \frac{1}{r_{X-}}& 0\\ 0& {\alpha }_{v1}& 0& r_{Z+}\\ 0& 0& {\alpha }_{v2}& r_{Z-}\\ r_Y& 0& 0& 0\end{array}\right]\left[\begin{array}{c}{I}_Y\\ V_{X+}\\ V_{X-}\\ I_Z\end{array}\right]$$

(11)

where β_v1 and β_v2 are current gains between the Y and X+ terminals and between the Y and X− terminals, respectively, α_v1 and α_v2 are voltage gains between the X+ and Z+ terminals and between the X− and Z− terminals, respectively, with ideal values of unity. Parameters r_Y, r_X+, r_X−, r_Z+, and r_Z− are the low-frequency impedances at the Y, X+, X−, Z+, and Z− terminals, respectively. The ideal values of r_Y, r_X+, r_X−, r_Z+, and r_Z− are zero, infinite, infinite, zero, and zero, respectively. Matrix Equation (12) represents the real operation of E-DVCC:

$$\left[\begin{array}{c}{V}_X\\ I_{Y1}\\ I_{Y2}\\ I_Z\end{array}\right]=\left[\begin{array}{cccc}{\alpha }_{c1}& -{\alpha }_{c2}& r_X& 0\\ 0& 0& 0& 0\\ 0& 0& 0& 0\\ 0& 0& K& \frac{1}{r_Z}\end{array}\right]\left[\begin{array}{c}{V}_{Y1}\\ V_{Y2}\\ I_X\\ V_Z\end{array}\right]$$

(12)

where α_c1 is voltage gain between the Y₁ and X terminals and α_c2 is voltage gain between Y₂ and X terminals, K is tunable current gain between the X and Z terminals, and r_x and r_z are low-frequency parasitic impedances at the X and Z terminals, respectively. The ideal value of α_c1, α_c2, r_x, and r_z are unity, unity, zero, and infinite, respectively.

Figure 4 shows the proposed positive floating C simulator while all low-frequency parasitic impedances are considered.

In Figure 4, for V_Z+ and V_Z− we have:

$$V_{Z+}={\alpha }_{v1}{V}_1$$

(13a)

$$V_{Z-}={\alpha }_{v2}{V}_2$$

(13b)

Using Equation (13) and considering the fact that r_Y1 >> r_Z+ and r_Y2 >> r_Z−, for V_Y1 and V_Y2 we have:

$$V_{Y1}=\frac{r_{Y1}}{r_{Z+}+r_{Y1}}{V}_{Z+}\approx {\alpha }_{v1}{V}_1$$

(14a)

$$V_{Y2}=\frac{r_{Y2}}{r_{Z-}+r_{Y2}}{V}_{Z-}\approx {\alpha }_{v2}{V}_2$$

(14b)

Using Equations (12)–(14), I_C is found as:

$$I_C=\frac{sC}{1+sC{r}_X}\left({\alpha }_{c1}{\alpha }_{v1}{V}_1-{\alpha }_{c2}{\alpha }_{v2}{V}_2\right)$$

(15)

Assuming r_Y << r_Z, using Equations (12) and (15) we have:

$$I_Y=\frac{sCK}{1+sC{r}_X}\left({\alpha }_{c1}{\alpha }_{v1}{V}_1-{\alpha }_{c2}{\alpha }_{v2}{V}_2\right)$$

(16)

According to Equation (11), neglecting the parasitic components (that is 1/r_x± ≅ 0), the current at Y terminal of VCII^± is conveyed to the X+ and X− terminals by gains of (+β_v1) and (−β_v2), respectively, and for I₁ and I₂ we have:

$$I_1=I_{X+}={\beta }_{v1}{I}_Y=\frac{sCK}{1+sC{r}_X}\left({\alpha }_{c1}{\alpha }_{v1}{V}_1-{\alpha }_{c2}{\alpha }_{v2}{V}_2\right){\beta }_{v1}$$

(17a)

$$I_2=I_{X-}=-{\beta }_{v2}{I}_Y=-\frac{sCK}{1+sC{r}_X}\left({\alpha }_{c1}{\alpha }_{v1}{V}_1-{\alpha }_{c2}{\alpha }_{v2}{V}_2\right){\beta }_{v2}$$

(17b)

In the worst case, β_v1 and β_v2 can be expressed as the following where ε << 1:

$${\beta }_{v1}=\left(1\pm \epsilon \right)$$

(18a)

$${\beta }_{v2}=\left(1\mp \epsilon \right)$$

(18b)

Inserting Equation (18a) into Equation (17a) and Equation (18b) into Equation (17b) gives:

$$I_1=\frac{sCK}{1+sC{r}_X}\left({\alpha }_{c1}{\alpha }_{v1}{V}_1-{\alpha }_{c2}{\alpha }_{v2}{V}_2\right)\pm \frac{sCK}{1+sC{r}_X}\left({\alpha }_{c1}{\alpha }_{v1}{V}_1-{\alpha }_{c2}{\alpha }_{v2}{V}_2\right)\epsilon$$

(19a)

$$I_2=-\frac{sCK}{1+sC{r}_X}\left({\alpha }_{c1}{\alpha }_{v1}{V}_1-{\alpha }_{c2}{\alpha }_{v2}{V}_2\right)\mp \frac{sCK}{1+sC{r}_X}\left({\alpha }_{c1}{\alpha }_{v1}{V}_1-{\alpha }_{c2}{\alpha }_{v2}{V}_2\right)\epsilon$$

(19b)

Using Equation (19), the input admittance of the proposed circuit is found as:

$$Z_{in}=\frac{\left(V_1-V_2\right)\left(1+sC{r}_X\right)}{sCK\left({\alpha }_{c1}{\alpha }_{v1}{V}_1-{\alpha }_{c2}{\alpha }_{v2}{V}_2\right)\pm sCK\left({\alpha }_{c1}{\alpha }_{v1}{V}_1-{\alpha }_{c2}{\alpha }_{v2}{V}_2\right)\epsilon }$$

(20)

The parameters α_c1, α_c2, α_v1, and α_v2 can be defined as Equation (21a–d) in which ε_c << 1 and ε_v << 1:

$${\alpha }_{c1}=\left(1\pm {\epsilon }_c\right)$$

(21a)

$${\alpha }_{c2}=\left(1\mp {\epsilon }_c\right)$$

(21b)

$${\alpha }_{v1}=\left(1\pm {\epsilon }_v\right)$$

(21c)

$${\alpha }_{v2}=\left(1\mp {\epsilon }_v\right)$$

(21d)

Inserting Equation (21a–d) into Equation (20) and simplifying the equation gives:

$$Z_{in}=\frac{1+sC{r}_X}{sCK\left[1\pm {\epsilon }_c\pm {\epsilon }_v\right]}=\frac{1}{sCK\left[1\pm {\epsilon }_c\pm {\epsilon }_v\right]}+\frac{r_X}{K\left[1\pm {\epsilon }_c\pm {\epsilon }_v\right]}$$

(22)

From Equation (22), the value of C_eq is found as:

$$C_{eq}=CK\left[1\pm {\epsilon }_c\pm {\epsilon }_v\right]$$

(23)

As can be seen, the non-ideal gains have a negligible effect on the value of C_eq, and in addition, using K, the value of C_eq is adjustable.

The value of the series of the parasitic capacitance of the simulated capacitor is found as:

$$R_{seri}=\frac{r_X}{K\left[1\pm {\epsilon }_c\pm {\epsilon }_v\right]}$$

(24)

As can be seen from Equation (24), the value of R_seri is reduced by increasing multiplication factor K. The equivalent circuit of the proposed capacitor multiplier is shown in Figure 5 where C_eq is the proposed electronically tunable equivalent floating capacitance. r_x± is the parasitic parallel resistances of the X± terminals, and R_seri is the parasitic series resistance of the simulated capacitor. A similar analysis can be performed for negative floating C.

4. The CMOS Implementation of VCII^± and E-DVCC

A realization of the internal structure of VCII^± is shown in Figure 6. The low impedance at the Y port is provided by the negative feedback loop made by the M₁–M₅ transistors. The input current to the Y port is transferred to the X+ port by a simple current mirror M₆–M₇. The voltage produced at the X+ node is transferred to the Z+ port by voltage buffer made by M₈–M₁₂. Similarly, the Y port input current is reversed by the current mirror, M₁₄–M₁₅, and transferred to the X− port. The voltage at the X− port is transferred to the Z₋ port by M₁₆–M₂₀. The transistor-level implementation of an electronically tunable E-DVCC is shown in Figure 7. The difference between input voltages V₁ and V₂ is produced at low impedance X port utilizing the negative feedback loop established by differential pairs, M₁–M₂ and M₃–M₄, along with M₅–M₇ transistors as reported in [27]. In the previously reported works, DVCC is used while the gain between the X and Z terminals is unity. Here, we add a gain cell between the X and Z terminals to electronically tune the current at the Z terminal. The used gain cell is a variable gain current mirror previously reported in [35].

The current of the X terminal is transferred to the gain cell using the current mirror made of M₇–M_7C and M₈–M_8C. As was described in [35], the current gain between the X and a Z terminal is tunable by control voltage V_C, expressed as:

$$K=\frac{I_Z}{I_X}=\frac{g{m}_7}{g{m}_8}\frac{1+g{m}_{8}rd{s}_{M8c}}{1+g{m}_{7}rd{s}_{M7c}}$$

(25)

being:

$$rd{s}_{M8c}=\frac{1}{\mu C_{ox}\frac{W_{M8c}}{L_{M8c}}\left(V_{dd}-Vc-V_{THP}\right)}$$

(26a)

and

$$rd{s}_{M7c}=\frac{1}{\mu C_{ox}\frac{W_{M7c}}{L_{Mc}}\left(V_{dd}-V_{THP}\right)}$$

(26b)

where, according to the usual meaning of symbols, gm_i and rds_i represent the transconductance and the drain-source resistance of the ith transistor, respectively, µ is the mobility of the carriers, C_ox represents the capacitance per unit of area of the specific fabrication technology, W/L_i is the ratio between the width and the length of the ith transistor, and V_TH is the threshold voltage that is a technology-dependent parameter.

As it is seen from (26a), the current gain is controllable by V_C.

5. Simulation Results

The proposed floating capacitor of Figure 1 is simulated in 0.18 µm CMOS technology and supply voltage of ±0.9 V using the SPICE program. The used aspect ratios are reported in

Table 1. The used transistors aspect ratios.

E-DVCC	Transistor	M1–M4	M5–M6, M7, M8C, M10C, M9	M7C, M9C	M11, M12	M8, M10
	Aspect Ratio (W/L)	9 µm/0.18 µm	72 µm/0.9 µm	7.2 µm/0.9 µm	9 µm/0.9 µm	720 µm/0.9 µm
VCII	Transistor	M1–M2, M8–M9, M17–M18, M6–M7, M13	M3–M4, M10–M11, M18–M19	M5, M12, M20
	Aspect Ratio (W/L)	9 µm/0.72 µm	36 µm/0.72 µm	8 µm/0.72 µm

. All current sources are implemented by simple current mirrors with aspect ratio of W = 9 µm and L = 0.72 µm with the values of I_B1 = I_B2 = I_B3 = 30 µA, IB4 = 31.4 µA. The performance parameters of VCII and E-DVCC are reported in

Table 2. The simulated low-frequency characteristics of VCII^± and E-DVCC.

VCII±		E-DVCC
rY	38.6 Ω	αc1		0.998
rX+	147.5 kΩ	αc2		0.997
rX−	133.7 kΩ	rx		574 Ω
rZ+	37 Ω	rY1, rY2		>2 GΩ
		rZ	VC = 0 V	120 kΩ
			VC = −0.45 V	80 kΩ
			VC = −0.9 V	50 kΩ
rZ−	37 Ω	K	VC = 0 V	10
β1 (DC)	1.023		VC = −0.45 V	19.5
β2 (DC)	1.01		VC = −0.9 V	25.4
αv1 (DC)	0.983	Pd	VC = 0 V	1.43 mW
αv2 (DC)	0.983		VC = 0 V	2.03 mW
Pd	0.804 mW		VC = −0.9 V	2.38 mW

.

The value of C is set at 10 pF. To verify the functionality of the proposed circuit, the plot of impedance magnitude and phase response of the simulated floating capacitor and the ideal one are shown in Figure 8. By changing the value of V_C from −0.9 V to 0 V, different multiplication factors are set. The frequency operation range of the proposed circuit results is equal to about two decades (from 10 kHz to 1 MHz). The maximum error value for different control voltages is shown in

Table 3. Deviation between theoretical and simulated values at different multiplication factors, C = 10 pF and f = 100 kHz.

	VC	Multiplication Factor	Expected Value of Ceq	Simulated Value of Ceq	% Error
Positive simulator	VC = 0 V	10	100 pF	99.4 pF	−0.6
	VC = −0.45 V	19.5	195 pF	196.1 pF	0.56
	VC = −0.9 V	25.4	254 pF	255.4 pF	0.55
Negative simulator	VC = 0 V	10	−100 pF	−99.47 pF	−0.53
	VC = −0.45 V	19.5	−195 pF	−196 pF	0.51
	VC = −0.9 V	25.4	−254 pF	−255.3 pF	0.51

. As can be seen, the maximum error value is only 0.56%. The application of the proposed floating capacitor as a high pass filter is shown in Figure 9. The frequency response of the high pass filter for different control voltages is shown in Figure 10. The −3 dB frequencies of the filter are 100 kHz, 130 kHz, and 230 kHz for V_C = −0.9 V, −0.45 V, and 0 V, respectively.

In order to examine the time domain response of the proposed circuit, an input voltage with a peak-to-peak value of 0.4 V and frequency of 1 MHz is applied. For different values of control voltages of 0, −0.45 V, and −0.9 V, the value of the input current phase is −101°, −101.4°, and −101°, respectively. The time domain responses are shown in Figure 11.

A comparison between the proposed circuit and other previously reported ones is presented in

Table 4. Comparison between proposed circuit and other reported works.

Electronic Tuning	Max Error	Vdd–Vss	Power Consumption	Number of Transistors	Passive Elements		ABB	Ref
					R	Floating C
Yes	20% 1	NA	NA	NA	1	No	2OTA + CCII	[7]
Yes	NA	±1.25 V	4.05 Mw 2	99	0	No	3CCDDC	[8]
Yes	NA	±1.5 V	NA	104	0	No	4CFTA	[9]
Yes	NA	2 V	0.7 mW	47	0	Yes	VGC-CCII	[10]
Yes	NA	±2.5 V	4.98 mW	70	0	No	Do-CCII + 3CCCII	[11]
No	NA	±1.5 V	9.52 mW	36	2	No	2DVCC	[12]
No	NA	±0.75 V	1.29 mW	98	2	No	2MODVCC	[13]
Yes	8.60%	±0.75 V	2.3 µW–6.34 µW	76	0	Yes	CCII + 4OTA	[14]
No	NA	NA	NA	NA	2	No	2CCII	[15]
Yes	10%1	±2 V	NA	24	1	No	DVCCTA	[16]
No	7.60%	1.3 V	1.32 mW	72	0	yes	2OTA	[17]
No	NA	1.5 V	240 μW	34	0	Yes	FVF	[18]
Yes	8%	±2.5 V	0.565 mW	104	0	No	4Gm	[19]
No	NA	±0.45 V	0.556 mW	56	2	No	2DVCC	[20]
No	NA	1.8 V	5.72 µW	11	0	Yes	MOS	[21]
Yes	0.56%	±0.9 V	2.234 mW–3.184 mW	51	0	No	VCII± + E-DVCC	Proposed

¹ Calculated. ² Power consumption for control current of 10 µA.

. As can be seen, the proposed circuit outperforms previous works in terms of reduced supply voltage, resistor-free structure, electronic tunability, reduced error, and simplicity.

6. Conclusions

In this paper, we present a new resistor-free topology for implementing either a positive or negative floating capacitor multiplier with electronic tuning capability. One VCII^±, one E-DVCC, and a single grounded capacitor are used. Using an electronically tunable current gain stage between the X and Z terminals of the E-DVCC, various multiplication factors are achieved. The circuit enjoys low voltage operation and offers reduced error compared with other works. A non-ideal analysis is given by taking into account non-ideal gains and parasitic impedances of the used active elements. The proposed circuit is free from any restricting matching requirements. The application of the proposed circuit as a standard high pass filter is also given to verify its functionality.