An Integrated Buck and Half-Bridge High Step-Down Converter

Abstract

In this paper, an integrated buck and asymmetrical half-bridge (IBAHB) high step-down converter utilizing a single-stage driving design for highly efficient energy conversion is proposed. The proposed converter is able to instantly and synchronously transfer energy from input to output within one conversion period. The advantages of high step-down conversion, lower voltage stress and fewer semiconductor elements verify the feasibility of this proposed topology. The turns ratio of the transformer can be reduced to increase the coupling rate, which decreases the leakage inductance. The proposed integrated topology utilizes the single-stage energy transfer control algorithm to verify that the proposed experimental circuit has a full-load efficiency. This development will achieve the market’s demand for high-buck converters and other related products and the competitive advantage of growing with the trend.

1. Introduction

High step-down converters and high efficiency energy transformation are increasingly required in many industrial applications such as UPSs, LEDs, voltage regulator for MCUs, battery chargers, EVs and power supply for railways. A buck converter and a modified push−pull converter are merged in a novel conversion topology with galvanic isolation; thus, a high step-down ratio is easily achieved without extremely low duty cycle or high turns ratio of the transformer in [1]. Based on the capacitive voltage division, the main objectives of the converter are storing energy in the blocking capacitors for increasing the step-down conversion ratio and reducing voltage stresses. As a result, the converter topology possesses the low switch voltage stress and chooses lower voltage rating MOSFETs to reduce both switching and conduction losses, and the overall efficiency is consequently improved in [2]. An integrated conventional buck–boost converter with a coupled inductor is proposed. The coupled inductor operates not only as a filter inductor of the buck–boost, but also as a transformer [3]. In [4], for the high step-down multiple output and high conversion ratio, isolated bidirectional distributed energy storage systems in [5] are proposed. A new single-switch (without considering SR switch) coupled inductor high step-down converter with an extended duty cycle and non-pulsating output current is presented in [6]. In order to recover the leakage energy, a simple lossless clamp circuit is also proposed. A non-isolated ultra-high step-down interleaved converter with low voltage stress and common ground between the input and output ports is proposed in [7]. High step-down converters and a new topology ISC-TaB and LLC converter are discussed [8,9]. A single-stage step-down ac–dc universal input voltage application is proposed in [10]. A high step-up/down resonant converter at MHz switching frequency, as well as the circuit design techniques to reduce the parasitic effects are discussed in [11]. High efficiency under both full-load and light-load conditions [12] and auto-balanced hybrid LLC series resonant converters with flying capacitors have been proposed in [13]. A bidirectional dc–dc converter with a coupled inductor is proposed in [14,15], which is suitable for applications requiring a large step-down ratio topology. A high-efficiency SIMO step-down converter was applied well to a single input power source plus two output terminals in [16]. An isolated bidirectional dc–dc converter with low current ripples was discussed in [17]. An isolated double step-down dc–dc converter was proposed in [18]. At present, most of the high step-down converters studied in the literature are 400 V/48 V, and 380 V/5 V converters are rarely studied. The buck converter with coupled winding, showing excellent ZVS operation, was proposed in [19]. In this paper, the proposed topology can lower the voltage on the transformer and thus the turns ratio can be reduced. As shown in Figure 1, the proposed high step-down converter can be used for power supply in renewable energy conversion and high DC conversion systems applications. DC Bus can be regarded as the battery of electric vehicles. In this situation, more converts are needed to lower the DC voltage from high DC voltage for load use. The main consideration of this research is the demand for possible future development, so the commonly used 5V output voltage specification is preliminarily determined. It can be speculated that the power supply system used in green energy applications in the future must rely on high-voltage buck converters to provide stable low-voltage power supplies.

In order to achieve a very high step-down ratio in the design of the buck converter, the conduction period is extremely low, so the conversion efficiency cannot be improved. Isolated buck conversion topologies are designed to achieve very high step-down voltage gain; the higher transformer turns ratio results in poor coupling, increased leakage inductance and reduced conversion efficiency. Considering that the isolated high step-down conversion ratio design uses an integrated Buck+AHB cascade topology, in order to achieve high conversion efficiency, the power switch switching must achieve the effect of single-stage power flow. Thus, we propose an isolated high step-down converter. The optimized design of single-stage signal-driven power switches in buck and half-bridge cascading topologies enables synchronous power flow from the input stage to the output stage within one switching period, allowing efficient energy conversion.

2. Integrated Buck and Asymmetrical Half-Bridge (IBAHB) Converter

The integrated buck and asymmetrical half-bridge (IBAHB) converter is shown in Figure 2. There are two elements, $C_1$ and $C_{\mathit{pT}}$, for reducing the energy of the leakage inductance, which enables the suppression of the peak voltage on the power switches, thus allowing power switches with lower $R_{\mathit{DS}\left(\mathit{on}\right)}$ to be utilized; consequently, the reduced voltage stress improves its efficiency. A buck-type circuit is added to the primary side, which makes the voltage on the transformer unequal to $V_i$ Therefore, the turns ratio of the transformer can be reduced to increase the coupling rate, which decreases the leakage inductance. The proposed topology uses four signals that are created by a pair of push–pull signals and a pair of complementary signals to control the power switches. The half-bridge ones are used for the main switches, and the complementary ones are used for synchronous rectification. The secondary side employs a dual-winding center-tapped rectifier circuit to double the frequency of the output inductor current, which can reduce the output current ripple. Therefore, the output inductor and the output capacitor can both be designed with a smaller volume.

2.1. Operating Principles

The equivalent circuit of the IBAHB is shown in Figure 3. The $L_1$ and $L_2$ represent the energy-storing inductor and the output inductor, respectively. Switches $S_1$, $S_2$, and $S_3$ are the main switches of this topology, and switches ${\mathit{SR}}_1$ and ${\mathit{SR}}_2$ are the synchronous rectifiers.

Diode $D_{fw}$ is a flywheel diode, $C_1$ and $C_{\mathit{DS}}$ are the switching capacitors, and $C_O$ is the filter capacitor. The primary side of the transformer is defined as $N_p$, and the secondary side is defined as $N_{s1}$ and $N_{s2}$. The turns ratio is defined as $n$ ($n$ = $N_{s1}/N_p$ = $N_{s2}/N_p$). The transient-state waveforms in CCM are shown in Figure 4. There are eight transient states, which are depicted as follows.

Mode 1 [t₀~t₁]

In Figure 5a, in this interval, the main switches $S_1$ and $S_2$ and the synchronous rectifier ${\mathit{SR}}_1$ are in the turned-on state. Voltage source $V_i$ transfers the energy to the inductor $L_1$ and capacitor $C_{pT}$ through the main switch $S_2$. At the same time, capacitor $C_1$ discharges the energy stored by the previous cycle to $C_{pT}$ also through $S_2$. The transformer starts to send energy from the primary side to the secondary side. The current of the output inductor $L_2$ maintains its freewheeling state while passing through $S{R}_1$ and the body diode of $S{R}_2$. However, the current passing through $S{R}_2$ decreases, and the current of $S{R}_1$ increases. The inductor currents $i_{L1}$, $i_{Np}$, $i_{Lm}$ and $i_{L2}$ are given, respectively, by

$$i_{L1\left(Mode1\right)}=i_{L1}\left(t_0\right)+\frac{V_i-V_{C_1}}{L_1}\times \left(t_1-t_0\right)$$

(1)

$$i_{N_p\left(Mode1\right)}=\frac{N_{s1}}{N_p}\times \left[i_{SR1\left(Mode1\right)}-i_{SR2\left(Mode1\right)}\right]$$

(2)

$$i_{L_m\left(Mode1\right)}=\left[i_{L1\left(Mode1\right)}+i_{C1\left(Mode1\right)}\right]-i_{N_p\left(Mode1\right)}$$

(3)

$$i_{L2\left(Mode1\right)}=i_{SR1\left(Mode1\right)}+i_{SR2\left(\mathrm{M}\mathrm{o}\mathrm{d}\mathrm{e}1\right)}$$

(4)

Mode 2 [t₁~t₂]

In Figure 5b, in this interval, the main switches $S_1$ and $S_2$ and one of the synchronous rectifier switches, ${\mathit{SR}}_1$, remain in the turned-on state. The voltage source $V_i$ continues transferring the energy to the energy-storage inductor $L_1$ and capacitor $C_{pT}$, and the capacitor $C_1$ is still discharging to $C_{pT}$. The transformer continues transferring the energy to the secondary side, and output inductor $L_2$ and output capacitor $C_O$ are storing the energy provided by the transformer. The inductor currents $i_{L1}$, $i_{Np}$, $i_{Lm}$ and $i_{L2}$ are given, respectively, by

$$i_{L1\left(Mode2\right)}=i_{L1\left(Mode2\right)}+\frac{V_i-V_{C1}}{L_1}\times \left(t_2-t_1\right)$$

(5)

$$i_{N_p\left(Mode2\right)}=\frac{N_{s1}}{N_p}\times i_{SR1\left(Mode2\right)}$$

(6)

$$i_{L_m\left(Mode2\right)}=\left[i_{L1\left(Mode2\right)}+i_{C1\left(Mode2\right)}\right]-i_{N_p\left(Mode2\right)}$$

(7)

$$i_{L2\left(Mode2\right)}=i_{L2\left(Mode2\right)}+\frac{\frac{N_{s1}}{N_p}\times \left(V_{C1}-V_{CpT}\right)-V_o}{L_2}\times t_2$$

(8)

Mode 3 [t₂~t₃]

In Figure 5c, in this interval, the main switches $S_1$, $S_2$, and $S_3$ are in the turned-off state, while the switches of the synchronous rectifier, ${\mathit{SR}}_1$ and $S{R}_2$, are in the turned-on state. The parasitic body diode of switch $S_3$ turns ON due to the freewheeling characteristic of leakage inductance. Additionally, the energy of leakage inductance can be retrieved by capacitor $C_{pT}$. Inductor $L_1$ releases energy through $D_{fw}$ to capacitor $C_1$ by its freewheeling state; moreover, the output inductor $L_2$ starts releasing the energy passing through ${\mathit{SR}}_1$ and $S{R}_2$ to provide the load $R_L$. The inductor currents $i_{L1}$, $i_{Np}$, $i_{Lm}$ and $i_{L2}$ are given, respectively, by

$$i_{L1\left(Mode3\right)}=i_{Dfw\left(Mode3\right)}$$

(9)

$$i_{N_p\left(Mode3\right)}=\frac{N_{s1}}{N_p}\times \left[i_{SR1\left(Mode3\right)}-i_{SR2\left(Mode3\right)}\right]$$

(10)

$$i_{L_m\left(Mode3\right)}=i_{Lk\left(Mode3\right)}$$

(11)

$$i_{L2\left(Mode3\right)}=i_{SR1\left(Mode3\right)}+i_{SR2\left(Mode3\right)}$$

(12)

Mode 4 [t₃~t₄]

In Figure 5d, in this interval, the main switches $S_1$, $S_2$, and $S_3$ remain in the turned-off state. Inductor $L_1$ continues releasing energy to $C_1$ through $D_{fw}$. Output inductor $L_2$ also keeps releasing energy to $R_L$, through ${\mathit{SR}}_1$ and $S{R}_2$. The inductor currents $i_{L1}$, $i_{Np}$, $i_{Lm}$ and $i_{L2}$ are given, respectively, by

$$i_{L1\left(Mode4\right)}=i_{Dfw\left(Mode4\right)}$$

(13)

$$i_{N_p\left(Mode4\right)}=i_{L_m\left(Mode4\right)}=0$$

(14)

$$i_{L2\left(Mode4\right)}=i_{SR1\left(Mode4\right)}+i_{SR2\left(Mode4\right)}$$

(15)

Mode 5 [t₄~t₅]

In Figure 5e, in this interval, the main switch $S_3$ and one of the synchronous rectifiers $S{R}_2$ are in the turned-on state; the other switches are turned off. The inductor $L_1$ keeps releasing energy to the capacitor $C_1$. When $S_3$ turns on, the capacitor $C_{pT}$ starts to release the stored energy, which can transfer to $N_{s2}$ on the secondary side. Because the $C_{pT}$ releases energy, the current passing through ${\mathit{SR}}_1$ can decrease to zero, and the current passing through $S{R}_2$ can increase. The inductor currents $i_{L1}$, $i_{Np}$, $i_{Lm}$ and $i_{L2}$ are given, respectively, by

$$i_{L1\left(Mode5\right)}=i_{Dfw\left(Mode5\right)}$$

(16)

$$i_{N_p\left(Mode5\right)}=\frac{N_{s2}}{N_p}\times \left[i_{SR1\left(\mathrm{M}\mathrm{o}\mathrm{d}\mathrm{e}5\right)}-i_{SR2\left(\mathrm{M}\mathrm{o}\mathrm{d}\mathrm{e}5\right)}\right]$$

(17)

$$i_{L_m\left(Mode5\right)}=i_{L_k\left(Mode5\right)}-i_{N_p\left(Mode5\right)}$$

(18)

$$i_{L2\left(Mode5\right)}=i_{SR1\left(Mode5\right)}+i_{SR2\left(Mode5\right)}$$

(19)

Mode 6 [t₅~t₆]

In Figure 5f, in this interval, switch $S_3$ and the switch of the synchronous rectifier $S{R}_2$ remain in the turned-on state; the other switches are turned off. This mode is similar to mode 5. However, the current is no longer passing through switch SR₁. The inductor currents $i_{L1}$, $i_{Np}$, $i_{Lm}$ and $i_{L2}$ are given, respectively, by

$$i_{L1\left(Mode6\right)}=i_{Dfw\left(Mode6\right)}$$

(20)

$$i_{N_p\left(Mode6\right)}=\left(-\frac{N_{s2}}{N_p}\right)\times i_{SR2\left(Mode6\right)}$$

(21)

$$i_{L_m\left(Mode6\right)}=i_{L_k\left(Mode6\right)}-i_{N_p\left(Mode6\right)}$$

(22)

$$i_{L2\left(Mode6\right)}=i_{L2\left(Mode6\right)}+\frac{\frac{N_{s2}}{N_p}\times V_{C_{pT}}-V_o}{L_2}\times t_6$$

(23)

Mode 7 [t₆~t₇]

In Figure 5g, in this interval, the main switches $S_1$, $S_2$, and $S_3$ are in the turned-off state, while the switches of the synchronous rectifier ${\mathit{SR}}_1$ and $S{R}_2$ are in the turned-on state. The switching capacitor $C_1$ can recover the leakage inductor energy. In this interval, the load energy is absorbed by the output inductor. The inductor currents $i_{L1}$, $i_{Np}$, $i_{Lm}$ and $i_{L2}$ are given, respectively, by

$$i_{L1\left(Mode7\right)}=i_{Dfw\left(Mode7\right)}=i_{C1\left(Mode7\right)}-i_{L_k\left(Mode7\right)}$$

(24)

$$i_{N_p\left(Mode7\right)}=\frac{N_{s2}}{N_p}\times \left[i_{SR1\left(Mode7\right)}-i_{SR2\left(Mode7\right)}\right]$$

(25)

$$i_{L_m\left(Mode7\right)}=i_{L_k\left(Mode7\right)}-i_{N_p\left(Mode7\right)}$$

(26)

$$i_{L2\left(Mode7\right)}=i_{SR1\left(Mode7\right)}+i_{SR2\left(Mode7\right)}$$

(27)

Mode 8 [t₇~t₈]

In Figure 5h, in this interval, the main switches $S_1$, $S_2$, and $S_3$ are in the turned-off state and the switches of the synchronous rectifier ${\mathit{SR}}_1$ and $S{R}_2$ are in the turned-on state. Same as Mode 4, inductors $L_1$ and $L_O$ release the energy to the switching capacitor $C_1$ and the load, respectively. The inductor currents $i_{L1}$, $i_{Np}$, $i_{Lm}$ and $i_{L2}$ are given, respectively, by

$$i_{L1\left(Mode8\right)}=i_{Dfw\left(Mode8\right)}$$

(28)

$$i_{N_p\left(Mode8\right)}=i_{L_m\left(Mode8\right)}=0$$

(29)

$$i_{L2\left(Mode8\right)}=i_{SR1\left(Mode8\right)}+i_{SR2\left(Mode8\right)}$$

(30)

2.2. Steady-State Analysis

In order to simplify the analysis, the proposed architecture is presumed to operate in continuous conduction mode (CCM), the method of control is shown in Figure 6. The characteristics of the transient state over the circuit will be ignored, and the currents passing through all of the components will be considered in DC. In addition, there are some assumptions listed as follows:

(1)

All components possess ideal characteristics.

(2)

The coupling coefficient of the transformer is unity.

(3)

The duty cycle is low, under 50%.

(4)

The subscript “pft” denotes the average current in the corresponding mode.

Mode 1 [0, DT]

The main switches S₁ and S₂ are in the turned-on state. The input voltage source transfers energy to the inductor L₁ and capacitor C_pT. At the same time, the capacitor C₁ also provides energy to C_pT through S₂. On the secondary side, the output inductor L₂ and the output capacitor C_o are charging from the transformer and the C_o supplies energy to load R_L. The equivalent circuit is shown in Figure 7 and the formulas can be expresses as:

$$V_{L1\left(Mode1\right)}=V_i-V_{Lm}-V_{CpT}=V_i-V_{C1}$$

(31)

$$V_{L2\left(Mode1\right)}=V_{Ns1}-V_o=n\cdot \left(V_{C1}-V_{CpT}\right)-V_o$$

(32)

$$I_{C1\left(Mode1\right)}=I_{L1}-I_{CpT}=I_i-n\cdot I_{SR1}+I_{Lm}$$

(33)

$$I_{CpT\left(Mode1\right)}=n\cdot I_{SR1}+I_{Lm}$$

(34)

$$I_{Co}=I_{SR1}-I_{R_L}$$

(35)

Mode 2 [DT, 0.5T]

The main switches S₁, S₂ and S₃ are in the turned-off state. Inductor L₁ changes into the freewheeling state to release energy to the capacitor C₁. Output inductor L_o also turns into the freewheeling state to release energy to the capacitor C_o and load R_L. The equivalent circuit is shown in Figure 8 and the formulas can be expressed as:

$$V_{L1\left(Mode2\right)}=-V_{C1}$$

(36)

$$V_{L2\left(Mode2\right)}=-V_o$$

(37)

$$I_{C1\left(Mode2\right)}=I_{L1}$$

(38)

$$I_{CpT\left(Mode2\right)}=0$$

(39)

$$I_{Co\left(Mode2\right)}=I_{SR1}+I_{SR2}-I_{R_L}$$

(40)

Mode 3 [0.5T, (0.5+D)T]

The main switch S₃ is in the turned-on state. Capacitor C_pT starts to release energy through the transformer to the secondary side. Inductor L₁ still keeps releasing energy to the capacitor C₁. The output inductor L₂ and the output capacitor C_o are charging using the transformer, and the C_o supplies energy to load R_L. The equivalent circuit is shown in Figure 9 and the formulas can be expressed as:

$$V_{L1\left(Mode3\right)}=-V_{C1}$$

(41)

$$V_{L2\left(Mode3\right)}=V_{Ns2}-V_o=n\cdot V_{CpT}-V_o$$

(42)

$$I_{C1\left(Mdoe3\right)}=I_{L1}$$

(43)

$$I_{CpT\left(Mode3\right)}=n\cdot I_{SR2}+I_{Lm}$$

(44)

$$I_{Co\left(Mode3\right)}=I_{SR2}-I_{R_L}$$

(45)

Mode 4 [(0.5+D)T, T]

Mode 4 is similar to Mode 2. The main switches S₁, S₂ and S₃ are in the turned-off state. Inductor L₁ still keeps the freewheeling state to release energy to the capacitor C₁. Output inductor L_o turns into the freewheeling state to release energy to the capacitor C_o and load R_L. The equivalent circuit is shown in Figure 10 and the formulas can be expressed as:

$$V_{L1\left(Mode4\right)}=-V_{C1}$$

(46)

$$V_{L2\left(Mode4\right)}=-V_o$$

(47)

$$I_{C1\left(Mode4\right)}=I_{L1}$$

(48)

$$I_{CpT\left(Mode4\right)}=0$$

(49)

$$I_{Co\left(Mode4\right)}=I_{SR1}+I_{SR2}-I_{R_L}$$

(50)

2.3. Voltage Gain

All the voltages of the capacitors can be derived using the charge balance. The relative equations of the energy-storage inductors L₁ and L₂ are given as

$${{\displaystyle \int }}_0^{DT}{v}_{L1\left(Mode1\right)}dt+{{\displaystyle \int }}_{DT}^{0.5T}{v}_{L1\left(Mode2\right)}dt+{{\displaystyle \int }}_{0.5T}^{\left(0.5+D\right)T}{v}_{L1\left(Mode3\right)}dt+{{\displaystyle \int }}_{\left(0.5+D\right)T}^T{v}_{L1\left(Mode4\right)}dt=0$$

(51)

Substituting (31), (36), (41) and (46) into (51), the voltage of the capacitor C₁ can be given by

$$v_{C1}=D\cdot V_i$$

(52)

Because the proposed circuit is an asymmetric architecture, the volt-second balance equation of the output inductor L₂ will be divided into two parts of derivations:

$${{\displaystyle \int }}_0^{DT}{v}_{L2\left(Mode1\right)}dt+{{\displaystyle \int }}_{DT}^{0.5T}{v}_{L2\left(Mode2\right)}dt=0$$

(53)

$${{\displaystyle \int }}_{0.5T}^{\left(0.5+D\right)T}{v}_{L2\left(Mode3\right)}dt+{{\displaystyle \int }}_{\left(0.5+D\right)T}^T{v}_{L2\left(Mode4\right)}dt=0$$

(54)

Substituting Equations (32) and (37) into (53) will give

$$v_o=2nD\cdot \left(v_{C1}-v_{CpT}\right)$$

(55)

Substituting Equations (42) and (47) into (54) will give

$$v_o=2nD\cdot v_{CpT}$$

(56)

Equations (55) and (56) will be equal, and substitute (52). The voltage of the capacitor C_pT can be obtained by

$$v_{CpT}=\frac{1}{2}D\cdot V_i$$

(57)

Finally, use Equations (56) and (57) to obtain the ideal voltage gain of the proposed architecture. The ideal voltage gain curve is shown in Figure 11:

$$\frac{v_o}{V_i}=n\cdot D^2$$

(58)

2.4. Voltage Stress

The voltage stresses of semiconductor devices can be derived by the known voltage of all the capacitors. Therefore, when the main switches S₁ and S₂ are in the turned-on state, the voltage stress of switch S₃ will be equal to the voltage of the capacitor C₁, as shown in Figure 7.

$$v_{DS3}=v_{C1}=D\cdot V_i$$

(59)

The voltage stress of the freewheeling diode D_fw can be given by

$$v_{Dfw}=V_i$$

(60)

Additionally, the voltage stress of the synchronous rectifier switch SR₂ will be equal to the sum of V_Ns1 and V_Ns2, which is also equal to V_C1 minus V_CpT and then multiplied two times by the turns ratio 2n.

$$v_{SR2}=v_{Ns1}+v_{Ns2}=2n\cdot \left(v_{C1}-v_{CpT}\right)=nD\cdot V_i$$

(61)

when the switch S₃ is turned on, switches S₁ and S₂ are turned off. As shown in Figure 9, the voltage stress of the S₁ is equal to the sum of the input voltage V_i and the capacitor C₁. The voltage stress of S₂ is equal to the capacitor C₁ and the voltage stress can be given by

$$v_{DS1}=V_i+V_{C1}$$

(62)

$$v_{DS2}=v_{C1}=D\cdot V_i$$

(63)

Because the secondary winding structure is symmetrical, the voltage stress of the synchronous rectifier SR₁ is the same as SR₂. The voltage stress can be given by

$$v_{SR1}=v_{Ns1}+v_{Ns2}=2n\cdot \left(v_{C1}-v_{CpT}\right)=nD\cdot V_i$$

(64)

when the input voltage and the turns ratio n equal 380V and $\frac{1}{12}$, respectively, the relationship between the voltage stress and the duty cycle is shown in Figure 12. It can be seen from Equations (53) and (57) that S₂ and S₃ have relatively lower voltage stress. Hence, low-voltage-stress power devices, such as MOSFETs with low R_DS(on), can be employed. Similar to switches S₂ and S₃, SR₁ and SR₂ can also adapt low-voltage-stress power devices with low R_DS(on) to reduce the loss of semiconductors to improve efficiency.

2.5. Current Stresses

Due to the law of conservation of energy, the output current I_Ro is equal to the input current I_i divided by the voltage gain, which can be expressed as

$$i_{R_L}=\frac{i_i}{n\cdot D^2}$$

(65)

The main switches S₁ and S₂ are in the turned-on state and S₃ is in the turned-off state, which is shown in Figure 7. The current through S₁ and S₂ can be expressed as

$$i_{DS1\left(ptf\right)}=i_{i\left(ptf\right)}=i_{L1\left(ptf\right)}=\frac{i_{i\left(avg\right)}}{D}=nD\cdot i_{R_L\left(avg\right)}$$

(66)

$$i_{DS2\left(ptf\right)}=n\cdot i_{SR1\left(ptf\right)}$$

(67)

$$i_{SR1\left(ptf\right)}=i_{R_L\left(avg\right)}$$

(68)

The main switches S₁, S₂ and S₃ are in the turned-off state, as shown in Figure 8. During this period, the current stresses through other semiconductor devices can be expressed as

$$i_{Dfw\left(ptf\right)}=i_{L1\left(ptf\right)}=nD\cdot i_{R_L\left(avg\right)}$$

(69)

$$i_{SR1\left(ptf\right)}=i_{SR2\left(ptf\right)}=\frac{i_{R_L\left(avg\right)}}{2}$$

(70)

As shown in Figure 9, the switch S₃ turns into the ON state, while the main switches S₁ and S₂ remain turned off. The current through the semiconductor devices can be expressed as

$$i_{Dfw\left(ptf\right)}=i_{L1\left(ptf\right)}=nD\cdot i_{R_L\left(avg\right)}$$

(71)

$$i_{DS3\left(ptf\right)}=n\cdot i_{SR2\left(ptf\right)}=n\cdot i_{R_L\left(avg\right)}$$

(72)

$$i_{SR2\left(ptf\right)}=i_{R_L\left(avg\right)}$$

(73)

when the main switches S₁, S₂ and S₃ are in the turned-off state again, the current flowing through the semiconductor devices would be the same as the previous operation mode.

The highest current flowing through each semiconductor element is the criterion for selecting current stress. The current stress of all the semiconductor devices would be reorganized and expressed below

$$i_{DS1\left(stress\right)}=nD\cdot i_{R_L\left(peak\right)}$$

(74)

$$i_{Dfw\left(stress\right)}=nD\cdot i_{R_L\left(peak\right)}$$

(75)

$$i_{DS2\left(stress\right)}=n\cdot i_{R_L\left(peak\right)}$$

(76)

$$i_{DS3\left(stress\right)}=n\cdot i_{R_L\left(peak\right)}$$

(77)

$$i_{SR1\left(stress\right)}=i_{R_L\left(peak\right)}$$

(78)

$$i_{SR2\left(stress\right)}=i_{R_L\left(peak\right)}$$

(79)

When the output current and the turns ratio n equal 40A and $\frac{1}{12}$, respectively, the relationship between the average current stress and the duty cycle is shown in Figure 13.

2.6. Conduction Loss Analysis

The equivalent circuit for analyzing the conduction loss of inductors and semiconductor devices is shown in Figure 14, in which $r_{L1}$ and $r_{L2}$ are the copper resistance of the inductors, $r_{Dfw}$ and $V_{Dfw}$ are the on-resistance and the forward voltage of the diode, respectively, $r_{DS\_S1}$, $r_{DS\_S2}$, $r_{DS\_S3}$, $r_{DS\_SR1}$ and $r_{DS\_SR2}$ are the on-resistances of the switches.

Mode 1 [0, DT]

The main switches S₁ and S₂ are in turned-on state. The voltage source V_i transfers energy to the inductors L₁ and the capacitor C_pT receives energy from V_i and the capacitor C₁.

Simultaneously, the output inductor L₂ and capacitor C_o are charging through the transformer, and then C_o supplies energy to the load R_L. The equivalent circuit is shown in Figure 15 and the formulas are expressed as follows:

$$\begin{array}{c}{v}_{L1\left(Mode1\right)}=V_i-v_{C1}-i_{L1}\cdot \left(r_{DS\_S1}+r_{L1}\right)\hfill \\ \hfill \hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}=V_i-[v_{CpT}+v_{Np}+i_{L1}\cdot \left(r_{DS\_S1}+r_{L1}\right)+n\cdot i_{L2}\cdot r_{DS\_S2}]\end{array}$$

(80)

$$v_{L2\left(Mode1\right)}=n\cdot \left(v_{C1}-v_{CpT}-n\cdot i_{L2}\cdot r_{DS\_S2}\right)-i_{L2}\cdot \left(r_{SR1}+r_{L2}\right)-v_o$$

(81)

$$v_{Np\left(Mode1\right)}=\frac{1}{n}\cdot \left[v_o+v_{L2}+i_{L2}\cdot \left(r_{SR1}+r_{L2}\right)\right]$$

(82)

Mode 2 [DT, 0.5T]

The main switches S₁, S₂ and S₃ are in the turned-off state. In this interval, the inductor L₁ releases energy to the capacitor C₁, and the output inductor L₂ changes into the freewheeling state, releasing energy to the output load R_L. The equivalent circuit is shown in Figure 16 and the formulas are expressed as follows:

$$v_{L1\left(Mode2\right)}=-\left[v_{C1}+V_{Dfw}+i_{L1}\cdot \left(r_{Dfw}+r_{L1}\right)\right]$$

(83)

$$v_{L2\left(Mode2\right)}=-\left(v_o+\frac{i_{L2}}{2}\cdot r_{SR1}+i_{L2}\cdot r_{L2}\right)$$

(84)

Mode 3 [0.5T, (0.5+D) T]

In this interval, the main switch S₃ is in the turned-on state. The inductor L₁ keeps releasing energy to the capacitor C₁, and the capacitor C_pT sends the energy to the output inductor L₂ and output capacitor C_o through the transformer. Then, C_o provides energy to the output load R_L. The equivalent circuit is shown in Figure 17 and the formulas are expressed as follows:

$$v_{L1\left(Mode3\right)}=-\left[v_{C1}+V_{Dfw}+i_{L1}\cdot \left(r_{Dfw}+r_{L1}\right)\right]$$

(85)

$$v_{L2\left(Mode3\right)}=n\cdot (v_{CpT}-n\cdot i_{L2}\cdot r_{DS\_S3})-i_{L2}\cdot \left(r_{SR2}+r_{L2}\right)-v_o$$

(86)

$$v_{Np\left(Mode3\right)}=\left(-\frac{1}{n}\right)\cdot \left[v_o+v_{L2}+i_{L2}\left(r_{SR2}+r_{L2}\right)\right]$$

(87)

Mode 4 [(0.5+D) T, T]

Similar to the Mode 2 state, the main switches S₁, S₂ and S₃ are all in the turned-off state. The inductor L₁ keeps releasing energy to the capacitor C₁ and the output inductor L₂ changes into the freewheeling state, releasing energy to the output load R_L. The equivalent circuit is shown in Figure 18 and the formulas are expressed as follows:

$$v_{L1\left(Mode4\right)}=-\left[v_{C1}+V_{Dfw}+i_{L1}\cdot \left(r_{Dfw}+r_{L1}\right)\right]$$

(88)

$$v_{L2\left(Mode4\right)}=-\left(v_o+\frac{i_{L2}}{2}\cdot r_{SR2}+i_{L2}\cdot r_{L2}\right)$$

(89)

First, through volt-second balance, the equation of the inductor L₁ can be expressed as

$${{\displaystyle \int }}_0^{DT}{v}_{L1\left(Mode1\right)}dt+{{\displaystyle \int }}_{DT}^{0.5T}{v}_{L1\left(Mode2\right)}dt+{{\displaystyle \int }}_{0.5T}^{\left(0.5+D\right)T}{v}_{L1\left(Mode3\right)}dt+{{\displaystyle \int }}_{\left(0.5+D\right)T}^T{v}_{L1\left(Mode4\right)}dt=0$$

(90)

By substituting Equations (80), (83), (85) and (88) into Equation (90), the voltage of the capacitor C₁ which is in the non-ideal state can be derived as

$$v_{C1}=D\cdot V_i-\left(1-D\right)\cdot V_{Dfw}-i_{L1}\cdot \left[D\cdot r_{DS\_S1}+\left(1-D\right)\cdot r_{Dfw}+r_{L1}\right]$$

(91)

Second, the proposed circuit is an asymmetric topology, so the volt-second balance equation of the output inductor L₂ should be divided into two parts of derivations:

$${{\displaystyle \int }}_0^{DT}{v}_{L2\left(Mode1\right)}dt+{{\displaystyle \int }}_{DT}^{0.5T}{v}_{L2\left(Mode2\right)}dt=0$$

(92)

$${{\displaystyle \int }}_{0.5T}^{\left(0.5+D\right)T}{v}_{L2\left(Mode3\right)}dt+{{\displaystyle \int }}_{\left(0.5+D\right)T}^T{v}_{L2\left(Mode4\right)}dt=0$$

(93)

Substitute Equations (81) and (84) into (92) and simplify it. Then, replace $r_{SR1}$ with $r_{SR}$, which is shown below.

$$2nD\cdot \left(v_{C1}-v_{CpT}\right)-2n^{2}D\cdot i_{L2}\cdot r_{DS\_S2}-i_{L2}\cdot \left(D\cdot r_{SR}+\frac{1}{2}{r}_{SR}+r_{L2}\right)-v_o=0$$

(94)

Substitute Equations (86) and (89) into (93) and simplify it. Then, replace $r_{SR2}$ with $r_{SR}$, which is shown below.

$$2nD\cdot v_{CpT}-2n^{2}D\cdot i_{L2}\cdot r_{DS\_S3}-i_{L2}\cdot \left(D\cdot r_{SR}+\frac{1}{2}\cdot r_{SR}+r_{L2}\right)-v_o=0$$

(95)

It is known that the summation and subtraction of Equations (94) and (95) are equal to zero, which are expressed as follows, respectively:

$$nD\cdot v_{C1}-n^{2}D\cdot i_{L2}\cdot \left(r_{DS\_S2}+r_{DS\_S3}\right)-i_{L2}\cdot \left(D\cdot r_{SR}+\frac{1}{2}{r}_{SR}+r_{L2}\right)-v_o=0$$

(96)

$$v_{C1}=2v_{CpT}$$

(97)

Substitute $v_{C1}$ of Equation (97) with Equation (91) and simplify it. Then, into Equation (95), as follows:

$$\begin{gathered} v_o=n{D}^2\cdot V_i-nD\cdot \left(1-D\right)\cdot V_{Dfw}+n^2{D}^3\cdot i_{L2}\cdot \left(r_{Dfw}-r_{D{S}_{S1}}\right) \\ -n^2{D}^2\cdot i_{L2}\cdot \left(r_{Dfw}+r_{L1}\right)-n^{2}D\cdot i_{L2}\cdot \left(r_{D{S}_{S2}}+r_{D{S}_{S3}}\right) \\ \hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}-D\cdot i_{L2}\cdot r_{SR}-i_{L2}\cdot \left(r_{L2}+\frac{1}{2}{r}_{SR}\right) \end{gathered}$$

(98)

Then, transfer Equation (98) into an equivalent circuit module, as shown in Figure 19.

$$r_a=n^2{D}^3\cdot \left(r_{Dfw}-r_{D{S}_{S1}}\right)$$

(99)

$$r_b=n^2{D}^2\cdot \left(r_{Dfw}+r_{L1}\right)$$

(100)

$$r_c=n^{2}D\cdot \left(r_{D{S}_{S2}}+r_{D{S}_{S3}}\right)$$

(101)

$$r_d=D\cdot r_{SR}$$

(102)

$$r_e=r_{L2}+\frac{1}{2}{r}_{SR}$$

(103)

Divide Equation (98) by V_i to obtain the voltage gain of the non-ideal state, which is expressed as

$$\frac{v_o}{V_i}=\left[n\cdot D^2-nD\left(1-D\right)\cdot K\right]\times \frac{R_L}{R_L+r_a+r_b+r_c+r_d+r_e}$$

(104)

Equation (98) multiplied by $\frac{i_{R_L}}{i_i}$ is the efficiency equation of the non-ideal state, which is expressed as follows:

$$\eta =\left[1-\left(\frac{1-D}{D}\right)\cdot K\right]\times \frac{R_L}{R_L+r_a+r_b+r_c+r_d+r_e}$$

(105)

where

$$K=\frac{V_{Dfw}}{Vi}$$

(106)

$$r_a=n^2{D}^3\cdot \left(r_{Dfw}-r_{D{S}_{S1}}\right)$$

(107)

$$r_b=n^2{D}^2\cdot \left(r_{Dfw}+r_{L1}\right)$$

(108)

$$r_c=n^{2}D\cdot \left(r_{D{S}_{S2}}+r_{D{S}_{S3}}\right)$$

(109)

$$r_d=D\cdot r_{SR}$$

(110)

$$r_e=r_{L2}+\frac{1}{2}{r}_{SR}$$

(111)

After calculating, the non-ideal voltage gain and the efficiency curve are shown below, as Figure 20 and Figure 21.

3. Design Considerations

3.1. Inductances

In order to achieve high step-down conversion, the proposed power topology requires components that can store energy and stabilize potential. Thus, this section analyzes and discusses the ripple characteristics of the energy storage elements.

First, the corresponding equation of inductance and current ripple can be expressed as follows:

$$L\cdot \Delta i_L=v_L\cdot \Delta t$$

(112)

Substituting Equation (31) into (112) would deduce the relationship between the inductor L₁ and current ripple, which is expressed as follows:

$$L_1=\frac{v_{L1}}{\Delta i_{L1}}\cdot \left(1-D\right)\cdot T=\frac{-v_{C1}}{\Delta i_{L1\left(-\right)}}\cdot \left(1-D\right)\cdot T$$

(113)

The condition of the L₁ working in the boundary conduction mode (BCM) is expressed below:

$$\left|\Delta i_{L1\left(-\right)}\right|=2\times i_{L1}$$

(114)

Obtain the equation of the L₁ working in BCM with (113) and (114), which is shown below:

$$L_{1\left(BCM\right)}=\frac{\left(1-D\right)\cdot R_L}{2\cdot {\left(nD\right)}^2\cdot f}=\frac{\left(1-D\right)\cdot v_o{}^2}{2\cdot {\left(nD\right)}^2\cdot f\cdot P_o}$$

(115)

As shown in Figure 22, the curve shows the value of L₁ working in BCM at each duty cycle with a switching frequency of 50kHz and $\frac{1}{12}$ turns ratio.

Next, derivate the equation of the output inductor L₂ in BCM. Substitute Equation (37) into Equation (112), and the relationship between L₂ and its current ripple would be derived as follows:

$$L_2=\frac{v_{L_2}}{\Delta i_{L2\left(-\right)}}\cdot \left(\frac{1}{2}-D\right)\cdot T=\frac{-v_o}{\Delta i_{L2}}\cdot \left(\frac{1}{2}-D\right)\cdot T$$

(116)

The condition of L₂ working in BCM is expressed as follows:

$$\left|\Delta i_{L2\left(-\right)}\right|=2\times i_{L2}$$

(117)

Obtain the equation of the L₂ working in BCM with Equations (116) and (117), as follows:

$$L_{2\left(BCM\right)}=\frac{\left(\frac{1}{2}-D\right)\cdot v_o{}^2}{2\cdot f\cdot P_o}$$

(118)

As shown in Figure 23, the curve shows the value of inductor L₂ working in BCM at each duty cycle with a switching frequency of 50 kHz and $\frac{1}{12}$ turns ratio.

3.2. Capacitors

The equation of the relationship between all capacitors and voltage ripple in the proposed topology can be expressed as:

$$\Delta Q=C\cdot \Delta v=I\cdot \Delta t$$

(119)

According to Equation (119), the relationship between the value of each capacitor and its voltage ripple can be expressed as follows:

$$C_1=\frac{v_{C_1}\cdot {\left(1-D\right)}^2}{L_1\cdot f^2\cdot \Delta v_{C_1}}=\frac{{\left(1-D\right)}^2}{L_1\cdot f^2\cdot \frac{\Delta v_{C_1}}{v_{C_1}}}$$

(120)

$$C_{pT}=\frac{D^2\cdot \left(n\cdot v_{CpT}-v_o\right)}{L_2\cdot f^2\cdot \Delta v_{C_{pT}}}=\frac{n{D}^2\cdot \left(1-2D\right)}{L_2\cdot f^2\cdot \frac{\Delta v_{C_{pT}}}{v_{C_{pT}}}}$$

(121)

$$C_o=\frac{v_o\cdot \left(\frac{1}{2}-D\right)}{16\cdot L_2\cdot f^2\cdot \Delta v_o}=\frac{\left(\frac{1}{2}-D\right)}{16\cdot L_2\cdot f^2\cdot \frac{\Delta v_o}{v_o}}$$

(122)

3.3. Control Block Diagram

As shown in Figure 24, after feedback voltage V_FB is calculated and processed, a group of output signals V_GS1,2 is generated through the comparison result with the sawtooth wave, and then V_GS3 and the secondary side synchronous rectification control signal V_{GS_SR1} and V_{GS_SR2} are generated through the delay and the reversed signal.

3.4. Design of Storage Elements

The turns ratio of the transformer n is preset to $\frac{1}{12}$, so the duty cycle is almost equal to 0.4 (0.397). The derivation of the duty cycle is shown below.

$$D=\sqrt{\frac{V_o}{V_i}\times \frac{1}{n}} \cong 0.397$$

(123)

The design of the inductance value operating in boundary mode is divided into two parts: the inductor L₁ and the output inductor L₂. Assume the inductor L₁ working in the boundary conduction mode (BCM) is at 20% of full load and use the parameters in Equation (115). The inductance value of L₁ in BCM is shown below:

$$L_{1\left(BCM\right)}=\frac{\left(1-D\right)\cdot V_o{}^2}{2\cdot {\left(nD\right)}^2\cdot f\cdot P_o} \cong 3.443 \mathrm{mH}$$

(124)

In addition, the output inductance L₂ is preset working in BCM at 5% of full load and use the parameters in Equation (118), which is shown below:

$$L_{2\left(BCM\right)}=\frac{\left(\frac{1}{2}-D\right)\cdot v_o{}^2}{2\cdot f\cdot P_o}=2.575 \mathsf{\mu }\mathrm{H}$$

(125)

Additionally, the number of turns N_p is calculated as follows:

$$N_p=\frac{V_{Np}\cdot dt}{\Delta B\cdot A_e}=\frac{\left(\frac{1}{2}\cdot D\cdot V_i\right)\cdot D}{2\cdot B_{max}\cdot A_{e\left(ETD49\right)}\cdot f}\cong 12 Turns$$

(126)

At full load, the allowable voltage ripple of the output capacitor C_o would be designed to be less than 0.5%, and the capacitors C₁ and C_pT would be designed to be less than 1%. Use the parameters in Equations (120) to (122), and the capacitance value is calculated as follows:

$$C_1=\frac{v_{C_1}\cdot {\left(1-D\right)}^2}{L_1\cdot f^2\cdot \Delta v_{C_1}}=\frac{{\left(1-D\right)}^2}{L_1\cdot f^2\cdot \frac{\Delta v_{C_1}}{v_{C_1}}} \cong 16 \mathsf{\mu }\mathrm{F}$$

(127)

$$C_{pT}=\frac{D^2\cdot \left(n\cdot v_{C_{pT}}-v_o\right)}{L_2\cdot f^2\cdot \Delta v_{C_{pT}}}=\frac{n{D}^2\cdot \left(1-2D\right)}{L_2\cdot f^2\cdot \frac{\Delta v_{C_{pT}}}{v_{C_{pT}}}} \cong 54 \mathsf{\mu }\mathrm{F}$$

(128)

$$C_o=\frac{v_o\cdot \left(\frac{1}{2}-D\right)}{16\cdot L_2\cdot f^2\cdot \Delta v_o}=\frac{\left(\frac{1}{2}-D\right)}{16\cdot L_2\cdot f^2\cdot \frac{\Delta v_o}{v_o}} \cong 250 \mathsf{\mu }\mathrm{F}$$

(129)

Using Equations (52) and (57), the voltage generated by the capacitors C₁ and C_pT is calculated as follows, respectively.

$$V_{C_1}=D\cdot V_i=150.86\mathrm{V}$$

(130)

$$V_{C_{pT}}=\frac{1}{2}\cdot D\cdot V_i=75.43\mathrm{V}$$

(131)

At full load, the reverse voltage and forward current of the diode can be calculated by (60) and (69), respectively.

$$V_{D_{fw}}=V_i=380\mathrm{V}$$

(132)

$$I_{D_{fw}}=nD\cdot I_{R_L}=1.323\mathrm{A}$$

(133)

The voltage stress of the power switches can be calculated using Equations (59) and (61)–(64), and the average current of the ones can be calculated using (74), (76)–(79), which is shown as follows:

$$V_{DS1}=V_i+V_{C1}=V_i+D\cdot V_i=\left(1+D\right)\cdot V_i=530.86\mathrm{V}$$

(134)

$$V_{DS2}=V_{DS3}=V_{C1}=D\cdot V_i=150.86\mathrm{V}$$

(135)

$$V_{D_{SR1}}=V_{D_{SR2}}=V_{Ns1}+V_{Ns2}=2n\cdot \left(V_{C1}-V_{CpT}\right)=nD\cdot V_i=12.57\mathrm{V}$$

(136)

$$I_{DS1}=nD\cdot I_{R_L}=1.323\mathrm{A}$$

(137)

$$I_{DS2}=I_{DS3}=n\cdot I_{R_L}=3.333\mathrm{A}$$

(138)

$$I_{SR1}=I_{SR2}=I_{R_L}=40\mathrm{A}$$

(139)

4. Experimental Results

The specification and component parameters of the proposed topology are shown in

Table 1. Prototype specification of the proposed IBAHB.

Experimental Specifications
Input Voltage (Vin)	380 V
Output Voltage (Vo)	5 V
Switching Frequency (fs)	50 kHz
Maximum Power (Po)	200 W

and

Table 2. The component parameters of the proposed topology.

Components	Parameters
Power Switch (S1)	IXFK 55N50 (500 V/55 A)
Power Switches (S2, S3)	FDA38N30 (300 V/38 A)
Synchronous Rectification Switches (SR1, SR2)	IRFP4668 (200 V/130 A)
Diode (Dfw)	DSEI 30-06A
Inductor (L1)	259 μH
Inductor (L2)	10 μH
Capacitor (C1)	120 μF/420 V
Capacitor (CpT)	330 μF/200 V
Capacitor (Co)	1500 μF/15 V
Turns (Np: Ns1: Ns2)	12:1:1

, respectively. Additionally, Figure 25 shows the presented converter and marks the main components. Experimental waveforms for the proposed topology at a full load of 200 W are shown in Figure 26. Figure 26a shows the voltage stress of the main switch S₁ and freewheeling diode D_fw, and it can be seen from the waveform that the withstand voltage of the main switch and the flywheel diode D_fw is very small. Figure 26b shows the voltage and current stress of S₂, the voltage and current stress of S₂ are reasonable. Figure 26c shows the voltage and current stress of S₃, the voltage stress and current stress of S₃ are reasonable. Figure 26d shows the voltage of C_pT and the current through the transformer i_Lk, from the i_Lk current waveform. It can be seen that the current flowing through the transformer is balanced and symmetrical, and no bias phenomenon occurs. Figure 26e shows the voltage and current stress of SR₁ and SR₂; the voltage and current of the synchronous rectification in the waveform are correct. Figure 26f shows i_L1 and i_L2, respectively, the current of L₂ is twice the switching frequency, effectively reducing the ripple of the output current.

Figure 27 shows the reality of the measured data for the proposed converter, obtained by a power analyzer of HIOKI 3390.

The maximum efficiency and full-load efficiency of the proposed topology are 86.65% and 85.17%, respectively. The experimental results confirm that the proposed topology is effective and feasible. When the circuit has a full load of 200 W, maximum efficiency occurs at 140 W, as shown in Figure 28.

In

Table 3. Performance comparison between Ref. [1] and the proposed topology.

	Reference [1]	Proposed Topology
Voltage Gain	$\frac{N_s}{N_p}\times D^2$	$\frac{N_s}{N_p}\times D^2$
Quantities of MOSFETs	3	5
Quantities of Diodes	3	1
Quantities of Inductors	2	2
Quantities of Transformers	1	1
Quantities of Capacitors	3	3
Control Strategy	Easy	Normal
Output Current Ripple	Small	Small
Voltage Stress of S1	$V_i+V_{C1}$	$V_i$
Peak Efficiency	84.45%	86.65%

, the proposed topology is compared with the number of MOSFETs and the number of diodes in Ref. [1]. It is shown that in the proposed topology, the main switch is a half-bridge and the synchronous rectification is complementary. The full load (250 W) efficiency of Ref. [1] is 81.44%, while the peak efficiency is 84.45%. Our proposed topology is 85.17% efficient at a full load of 200 W, but the maximum efficiency (86.65%) occurs at 140 W. In the voltage stress comparison, our proposed topology has lower voltage stress.

The power switch signals are divided into two parts, as shown in Figure 24: the push–pull control type signal and its complementary signals. The push–pull control type signal enables the core of the transformer to be reset without additional reset circuits. The frequency of the current ripple is double the switching frequency, which is helpful for reducing the volume of the inductor L₂ and capacitor C_o. The frequency of the current ripple is twice the switching frequency. Additionally, it is helpful to reduce the volume of the inductor L₂ and capacitor C_o. Simultaneously, if the semiconductor component possesses a low R_DS(on), it would help improve efficiency.

5. Conclusions

We propose a new high step-down conversion prototype through references, theoretical analysis and experimental results. The proposed topology has active clamping to recover the energy of leakage inductance, which would reduce the spike voltage. Hence, it could employ a semiconductor component with lower voltage stress. The proposed topology has the following advantage: by adding a step-down conversion architecture on the primary side, the potential of the transformer could be effectively reduced. Then, it could obtain a high step-down conversion ratio without an extremely low duty cycle or a high turns ratio.

The power switch signals are divided into two parts: the push–pull control type signal and its complementary signals. Additionally, the push–pull control type signal could reset the core of the transformer without additional reset circuits. The core of the transformer operates in quadrants I and III, so the utilization rate of the core is high which could reduce the volume of the whole transformer.