Compact Model for L-Shaped Tunnel Field-Effect Transistor Including the 2D Region
Round 1
Reviewer 1 Report
In this manuscript, authors developed a compact model for L-shaped TFET. The manuscript is recommended publish before some issues addressed.
Page 2, line 77, please define x and y directions on the figure. Page 3, line 89-94, please justify assumption 2. Page 3, line 89-94, the source region is very heavily doped to 10e20. Please justify the assumption that the source is completely depleted. Section 2.2 1D model: a device schematic figure with all the parameters on it will be helpful. Clarify what is channel region. In Fig. 4 and 5, what does the inset tend to show? The characters on the inset are too small to read. In Fig. 4, which dimension is x? Does the device has a dimension of 10 um long? Which dimension? 4 (d) (e) (f), the caption in the figure are wrong. Tj should be 4, 5 and 6 nm instead of all 4 nm. Page 6 line 147, what is Wt? 5, the green data points are Ev instead of qφ. The figure legend are mislabelled. What are the red data points? 7 line 203 to 208, all the “donate” are typos and they should be “denote”.Author Response
Page 2, line 77, please define x and y directions on the figure.
Fig. 1 has been updated, and x and y directions have been added.
Page 3, line 89-94, please justify assumption 2.
The justification of assumptions 2 and 3 have been added on L. 95-104, P. 3 and P. 4 in the revised manuscript.
Page 3, line 89-94, the source region is very heavily doped to 1e20. Please justify the assumption that the source is completely depleted.
Depletion length is inversely proportional to doping concentration as can be seen from (7). Since the source is very heavily doped, the depletion length comes out to be very small, that is less than 2 nm as can been seen from Figs. 5 (d), (e), and (f). For the 2D model, the additional tunneling length which has been neglected in this work, does not result in significant inaccuracy of the calculated Ids-Vgs characteristics. We changed and added L. 101-104, P. 3 and P.4.
Section 2.2 1D model: a device schematic figure with all the parameters on it will be helpful. Clarify what is channel region.
Fig. 4(a) has been added in the revised manuscript. Fig. 4(a) shows a device schematic of the magnified source, and channel regions with all the important parameters used in the 1D model mentioned in the figure. Channel region considered in the 1D model is the Coverlap region. We added L. 131-139, P. 5 and Fig. 4(a).
In Fig. 4 and 5, what does the inset tend to show? The characters on the inset are too small to read.
The inset has been removed from Figs 4 (d), (e), and (f), and 5 (a), and (b) (renumbered as Fig. 5, and 6, respectively, in the revised manuscript). Instead, a new figure, Fig. 4(b) has been added, showing the black cutline where the data in Figs. 5(d), (e), and (f), and Figs. 6(a), and (b) (in the revised manuscript) has been extracted/calculated.
In Fig. 4, which dimension is x? Does the device has a dimension of 10 um long? Which dimension?
In Fig. 4 (Fig. 5 in the revised manuscript), the x dimension can be seen by the black cutline in the now added Fig. 4(b).
The x-axis label in Figs. 5 (d), (e), and (f) has been corrected from µm to nm.
It has been mentioned that data in Figs. 5 (d), (e), and (f), and Figs. 6(a) and (b) are along the black cutline shown in Fig. 4(b) in the description of respective figures.
Fig. 4 (d) (e) (f), the caption in the figure are wrong. Tj should be 4, 5 and 6 nm instead of all 4 nm.
The caption in Figs 4 (d), (e), and (f) (now renumbered as Fig. 5 (d), (e), and (f) in the revised manuscript) has been corrected. It now reads Tj=4, 5 and 6 nm for Fig. 5 (d), (e), and (f), respectively.
Page 6 line 147, what is Wt?
Wt represents tunneling length. This has been added on L. 92, P. 3 in the revised manuscript.
In Fig. 5, the green data points are Ev instead of qφ. The figure legend are mislabeled. What are the red data points? 7 line 203 to 208, all the “donate” are typos and they should be “denote”.
The corrections have been made. Figure legends have been corrected. The red data points is the potential, and the green data points are is the Ev. Figure legends are mentioned on L.164-169, P.7. We corrected L.225 and 226, P.8, and 9 as “denote”.
Reviewer 2 Report
The structure of LTFET is very difficult to fabricate experimentally. In this study, comparisons are just between TCAD and compact model. Is it possible to benchmark experimental results from other references? TFET was proposed for low subthreshold slope. Could the authors explain that the mechanisms that LTFET could prevail in subthreshold slope and on current as compared with other TFET structures?Author Response
The structure of LTFET is very difficult to fabricate experimentally. In this study, comparisons are just between TCAD and compact model. Is it possible to benchmark experimental results from other references? TFET was proposed for low subthreshold slope. Could the authors explain that the mechanisms that LTFET could prevail in subthreshold slope and on current as compared with other TFET structures?
LTFET has been experimentally fabricated in [4]. The experimental device, however, owing of its fabrication difficulties, demonstrated significant trap-assisted-tunneling (TAT) induced degradation of the Ids-Vgs characteristics. The model presented in this manuscript is ideal, that is, it does not consider the effect TAT on Ids-Vgs characteristics. TAT model for line TFETs is a significant topic and deserves a dedicated paper. We are currently working on TAT model for line TFETs. This has been mentioned on L. 255-260, P.10 and added References [15,16].
The benefits of the LTFET over planar TFET have been mentioned on L. 235-242, P. 10.
Round 2
Reviewer 2 Report
no comments
Author Response
According to Reviewer's comments, English style and typos in the manuscript were corrected. The modifications were marked as highlight.
