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Appl. Sci. 2017, 7(10), 1047; https://doi.org/10.3390/app7101047

The Challenges of Advanced CMOS Process from 2D to 3D

1,2,3,†,* , 1,†
,
1,†
,
1,†
,
1,†
,
1,†
,
1,†
,
1,†
and
1,2,†,*
1
Key Laboratory of Microelectronics Devices & Integrated Technology, Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China
2
Microelectronics Institute, University of Chinese Academy of Sciences, Beijing 100049, China
3
School of ICT, KTH Royal Institute of Technology, Isafjordsgatan 22, 16440 Stockholm, Sweden
The authors have equally contributed in this article.
*
Authors to whom correspondence should be addressed.
Received: 29 August 2017 / Revised: 21 September 2017 / Accepted: 25 September 2017 / Published: 13 October 2017
(This article belongs to the Section Nanotechnology and Applied Nanosciences)

Abstract

The architecture, size and density of metal oxide field effect transistors (MOSFETs) as unit bricks in integrated circuits (ICs) have constantly changed during the past five decades. The driving force for such scientific and technological development is to reduce the production price, power consumption and faster carrier transport in the transistor channel. Therefore, many challenges and difficulties have been merged in the processing of transistors which have to be dealed and solved. This article highlights the transition from 2D planar MOSFETs to 3D fin field effective transistors (FinFETs) and then presents how the process flow faces different technological challenges. The discussions contain nano-scaled patterning and process issues related to gate and (source/drain) S/D formation as well as integration of III-V materials for high carrier mobility in channel for future FinFETs. View Full-Text
Keywords: FinFETs; CMOS; device processing; integrated circuits FinFETs; CMOS; device processing; integrated circuits
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Radamson, H.H.; Zhang, Y.; He, X.; Cui, H.; Li, J.; Xiang, J.; Liu, J.; Gu, S.; Wang, G. The Challenges of Advanced CMOS Process from 2D to 3D. Appl. Sci. 2017, 7, 1047.

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