Design of Novel HG-SIQBC-Fed Multilevel Inverter for Standalone Microgrid Applications

Abstract

The growth of distributed power generation using renewable energy sources has led to the development of new-generation power electronic converters. This is because DC–DC converters and inverters form the fundamental building blocks in numerous applications, which include renewable integrations, energy harvesting, and transportation. Additionally, they play a vital role in microgrid applications. The deployment of distributed energy resources (DERs) with renewable sources such as solar has paved the way for microgrid support systems, thus forming an efficient electric grid. To enhance the voltage of such sources and to integrate them into the grid, high-gain DC–DC converters and inverter circuits are required. In this paper, a novel single-switch high-gain converter (HG-SIQBC) with quadratic voltage gain and wide controllable range of load is proposed, the output of which is fed to a modified multilevel inverter for conversion of voltage. The overall performance of the newly designed converter and inverter is analyzed and compared with the existing topologies. A prototype of the investigated multilevel inverter is designed and tested in the laboratory. Development and testing of such novel topologies have become the need of the hour as the grid becomes smarter with increased penetration of distributed resources.

1. Introduction

Conventional power systems are getting degraded due to the gradual reduction in fossil fuels, poor energy efficiency, and low reliability. This leads to the development of new power generation systems at the distribution level using various nonconventional and renewable energy sources such as solar energy, wind power, fuel cells, and biogas [1]. These energy sources are integrated into a utility distribution network; the power generated using this network is termed as distributed power generation, and the energy sources incorporated in this network are known as distributed energy resources (DERs). The penetration of DERs in the worldwide electrical distribution leads to the formation of power clusters which are known as microgrids. This provides an opportunity to utilize renewable energy sources for a green and clean environment [2,3]. Furthermore, the DC microgrid has advantages such as high reliability, uninterruptible power supply, no reactive power, reduced losses, higher efficiency, simpler connection with DC bus, no need of synchronization, and no frequency aspects. Despite advantages over alternating current microgrids, the output voltage of these DC power generators is low. Therefore, high-gain DC–DC converters are needed for a DC microgrid [4]. Moreover, the use of multilevel inverters has become predominant in the fields of power systems, solid-state transformers, power quality conditioning, renewable energy applications, and many more industrial applications. Among these, PV-based power generation systems are gaining popularity and are widely used in distribution-side networks. The process of power generation is classified into on-grid and off-grid systems, and the role of inverters is inevitable in all grid-connected networks. Initially, two-level inverters are employed in grid operation for the conversion of voltage from PV arrays to the grid network. However, the efficiency and conversion gain of these conventional inverters is much lower, which results in poor power quality issues and harmonics. To overcome these problems, multilevel converters have been introduced for combining PV arrays with the distribution grid [5,6]. Multilevel inverters possess better characteristics when compared to conventional two-level inverters [7,8,9]. The merits of MLI topologies include a better harmonic profile, reduced filter size, modular structure, improved load sharing capabilities, and reduction in voltage stress levels across the switches [10]. Many researchers working in this domain are trying to contribute a novel configuration with improved efficiency, power density, and reliability at a low cost. The studies published by many researchers working in this field have proven that the modifications of NPC (neutral point clamped), cascaded H-bridge topologies give greater efficiency with reduced harmonic content [11].

The types of multilevel inverter are illustrated as a schematic in Figure 1.

Overall, this work focuses on power electronic converters such as DC–DC converters and inverters for applications associated with the DC microgrid. An illustration of the proposed system is shown in Figure 2. The input is fed from a PV array and is given to a novel single-switch non-isolated high-gain DC–DC converter to match with the DC bus voltage level. It can also supply AC loads via the modified 11-level inverter proposed in this work. The switching logic of the proposed multilevel inverter can also be extended to higher-level configurations and is verified in the simulation environment. To match the output voltage of this converter with the DC bus voltage, a suitable PI controller is designed, providing a better control operation. The analysis is performed and the results are obtained with the help of MATLAB simulations. To validate the simulation results of the multilevel inverter, a prototype for five-level configuration is developed and tested in the laboratory.

2. Proposed Converter—I: Novel Non-Isolated High-Gain Switched Inductor Quadratic Boost Converter with High Voltage Conversion Ratio (HG-SIQBC)

The proposed HG-SIQBC comprises a switched inductor cell and a quadratic converter configuration. The first part of the converter comprises a switched inductor cell formed with the combination of inductors L₁ and L₂, as well as diodes D₁₁, D₁₂, and D₁. The latter part of the circuit comprises a switch ‘S’, as well as combinations of inductor L₃ and capacitors C₁, C₂, C₃, and C₀, along with the diodes D₂–D₆. The circuit diagram of the proposed HG-SIQBC topology is displayed in Figure 3.

The circuit operates in two modes as a function of the switching sequence of the active switch present in the converter. According to the relationships between current and voltage in the different operating modes, the theoretical waveforms of the proposed topology are illustrated in Figure 4. The waveforms drawn from top to bottom correspond to the gate pulse of the switch, currents of L₁, L₂, and L₃, and voltages of C₁, C₂, C₃, and C₀.

2.1. HG-SIQC—Mode I: Switch ‘S’ in ON State

During this switching interval, the switch ‘S’ is kept in the ON state, and the diodes D₁, D₂, and D₅ are simultaneously forward-biased, as presented in Figure 5.

The voltage across the inductor L₁ and L₂ becomes equal to V_in/2, and the voltage across L₃ is equal to the difference between the voltage in C₁ and C₂. The capacitor C₂ is discharged, and it charges C₁ and C₃. Similarly, the capacitor C₀ is discharged to the load. The following equations are obtained when Kirchhoff’s voltage law (KVL) is applied to Figure 5:

$$\left\{\begin{array}{l}{V}_{in}-V_{L_1}-V_{L_2}=0\\ V_{C_2}-V_{C_1}-V_{L_3}=0\\ V_{C_2}-V_{C_3}=0\end{array}\right..$$

(1)

From Equation (1), the voltage across the inductors L₁, L₂, and L₃ can be written as

$$\left\{\begin{array}{l}{L}_1\frac{d{i}_{L_1}}{dt}=\frac{V_{in}}{2}\\ L_2\frac{d{i}_{L_2}}{dt}=\frac{V_{in}}{2}\\ L_3\frac{d{i}_{L_3}}{dt}=V_{C_2}-V_{C_1}\end{array}\right.,$$

(2)

where V_in is the input voltage, and V_C1 and V_C2 are the voltages across the capacitors C₁ and C₂, respectively.

Similarly, Kirchhoff’s current law (KCL) is applied to the circuit shown in Figure 5 to obtain the current flowing through the capacitors.

$$\left\{\begin{array}{l}{I}_{C_1}=I_{L_3}\\ I_{C_2}=-\left[I_{C_3}+I_{C_1}\right]\\ I_{C_3}=I_{C_2}-I_{C_1}\\ I_{C_0}=-I_0\end{array}\right..$$

(3)

2.2. HG-SIQC—Mode II: Switch ’S’ in OFF State

During this switching interval, the switch ‘S’ is kept in the OFF state, as shown in Figure 6.

The inductors connected at the input side discharge and transfer energy to capacitor C₂. Meanwhile, capacitor C₃ is discharged and supplies output capacitor C₀. The voltage equations of the proposed converter during the OFF state of the switch can be obtained by applying the KVL to Figure 6.

$$\left\{\begin{array}{l}{V}_{in}-V_{L_2}+V_{C_3}-V_{C_0}=0\\ V_{in}-V_{L_1}+V_{C_1}-V_{C_2}=0\\ V_{in}-V_{L_2}-V_{L_3}-V_{C_2}=0\end{array}\right..$$

(4)

From Equation (4), the voltage across the inductors L₁, L₂, and L₃ can be written as

$$\left\{\begin{array}{l}{L}_1\frac{d{i}_{L_1}}{dt}=V_{in}+V_{C_1}-V_{C_2}\\ L_2\frac{d{i}_{L_2}}{dt}=V_{in}+V_{C_3}-V_0\\ L_3\frac{d{i}_{L_3}}{dt}=-V_{C_1}\end{array}\right.,$$

(5)

where V_in is the input voltage, V₀ is the output voltage, and V_C1 and V_C3 are the voltages across the capacitors C₁ and C₃, respectively.

Similarly, KCL is applied to the circuit shown in Figure 6 to yield the current equations.

$$\left\{\begin{array}{l}{I}_{C_1}=-\left[I_{C_2}-I_{L_3}\right]\\ I_{C_2}=I_{C_1}+I_{L_3}\\ I_{C_3}=I_{C_0}=I_0\end{array}\right..$$

(6)

The total volt-seconds applied to the inductor L₃ over one switching period are as follows [12]:

$${\displaystyle \underset{0}{\overset{T}{\int }}{V}_{L_3}(t)dt=(V_{C_2}-V_{C_1})DT+}(-V_{C_1})(1-D)T,$$

(7)

where D is the duty cycle, and T is the switching period.

The following equation can be obtained by equating Equation (7) to zero:

$$(V_{C_2}D)-(V_{C_1}D)-V_{C_1}+(V_{C_1}D)=0.$$

(8)

Therefore,

$$V_{C_2}=\frac{V_{C_1}}{D}.$$

(9)

The total volt-seconds applied to inductor L₁ over one switching period are calculated as

$${\displaystyle \underset{0}{\overset{T}{\int }}{V}_{L_1}(t)dt=\left(\frac{V_{in}}{2}\right)DT+}\left(V_{in}+V_{C_1}-V_{C_2}\right)(1-D)T.$$

(10)

By equating Equation (10) to zero, the following equations can be obtained:

Substituting $V_{C_2}=\frac{V_{C_1}}{D}$,

$$\left(\frac{V_{in}}{2}\right)D+\left(V_{in}+V_{C_1}-\frac{V_{C_1}}{D}\right)(1-D)=0,$$

(11)

$$\left(\frac{V_{in}D+2V_{in}-2V_{in}D}{2}\right)+\left(\frac{2V_{C_1}D-V_{C_1}{D}^2-V_{C_1}}{2}\right),$$

(12)

$$V_{C_1}\left(\frac{2D-D^2-1}{D}\right)=\frac{V_{in}(D-2)}{2}.$$

(13)

Therefore,

$$V_{C_1}=\frac{V_{in}D(D-2)}{2{(1-D)}^2}.$$

(14)

Substituting the value of V_C1 into Equation (9) yields

$$V_{C_2}=\frac{V_{C_1}}{D}=\frac{V_{in}(D-2)}{2{(1-D)}^2}.$$

(15)

Similarly, V_C3 is calculated using the following equation:

$$V_{C_3}=\frac{V_{in}(D-2)}{2{(1-D)}^2}.$$

(16)

Subsequently, the voltage gain of the proposed converter can be obtained by applying the volt-sec principle to inductor L₂.

$${\displaystyle \underset{0}{\overset{T}{\int }}{V}_{L_2}(t)dt=\left(\frac{V_{in}}{2}\right)DT+}\left(V_{in}+V_{C_3}-V_0\right)(1-D)T.$$

(17)

By equating Equation (17) to zero, the following equations can be obtained:

$$\left(\frac{V_{in}}{2}\right)\ast D+V_{in}-V_{in}D+V_{C_3}(1-D)=V_0(1-D),$$

(18)

$$\frac{V_{in}(2-D)(D-1)+V_{in}(D-2)}{2(D-1)}=V_0(1-D),$$

(19)

$$\therefore G=\frac{V_0}{V_{in}}=\frac{{(D-2)}^2}{2{(1-D)}^2},$$

(20)

where G is the voltage gain of the proposed HG-SIQBC converter, and D is the duty cycle of the converter switch.

The plot between the voltage gain vs. duty cycle of the proposed topology and a comparison of proposed HG-SIQBC converter with other quadratic converters are shown in Figure 7a,b, respectively. The graph between voltage gain (G) and duty cycle (D) is drawn according to Equation (20).

The input and output voltages for the proposed HG-SIQBC were considered as 75 V and 400 V, respectively. The converter should be operated at a duty cycle of 55.8% to achieve the required output voltage. The following expression can determine this:

$$\frac{400}{75}=\frac{{(D-2)}^2}{2{(1-D)}^2}.$$

(21)

Therefore, $D=0.558=55.8\%$.

Other existing quadratic boost topologies with high voltage gain [13,14,15,16,17,18,19,20] were compared to the proposed HG-SIQBC topology. The proposed topology had better results in terms of voltage stress and voltage gain. A comparison of topologies is shown in

Table 1. Comparison of proposed HG-SIQBC converter with other quadratic converters.

Topology	No. of Switches	No. of Diodes	No. of Inductors	No. of Capacitors	Voltage Gain (G)	Voltage Stress
[13]	1	3	2	2	$\frac{D\left(2-D\right)}{{\left(1-D\right)}^2}$	$\frac{1}{{\left(1-D\right)}^2}$
[14]	1	3	2	2	$\frac{1}{{\left(1-D\right)}^2}$	$\frac{1}{{\left(1-D\right)}^2}$
[15]	1	4	2	4	$\frac{3+D}{2\left(1-D\right)}$	$\frac{1}{\left(1-D\right)}$
[16]	1	3	1	3	$\frac{1+D}{1-D}$	$\frac{1+D}{1-D}$
[17]	1	3	4	6	$\frac{3D}{1-D}$	$\frac{1}{1-D}$
[18]	1	2	2	3	$\frac{1+D}{1-D}$	$\frac{1}{1-D}$
[19]	1	3	2	3	${\left(\frac{D}{1-D}\right)}^2$	${\left(\frac{1}{D}\right)}^2$
[20]	1	3	3	3	$\frac{D}{{\left(1-D\right)}^2}$	$\frac{D}{{\left(1-D\right)}^2}$
Proposed HG-SIQBC	1	8	3	4	$\frac{{\left(D-2\right)}^2}{2{\left(1-D\right)}^2}$	$\frac{\left(D-2\right)}{2{\left(1-D\right)}^2}$

.

To determine the power loss of each component connected in the converter circuit, it is necessary to determine the current flowing through it. Therefore, by applying the ampere-seconds balance on capacitor C₀, the current flowing through the capacitor C₃ can be determined as follows:

$$(I_{C_0})D+(I_{C_0})(1-D)=0,$$

(22)

$$-I_{0}D+(I_{C_3})(1-D)=0.$$

(23)

Therefore,

$$I_{C_3}=\frac{I_{0}D}{(1-D)}.$$

(24)

Similarly, by applying the ampere-seconds balance, the current flowing through the capacitors can be determined as follows:

$$\left\{\begin{array}{l}{I}_{C_1}=\left(\frac{D(4D^2+D-6)+4}{2{(D-1)}^2(2D-1)}\right)\frac{V_0}{R}\\ I_{C_2}=\left(\frac{7D-6}{4{(D-1)}^3}-1\right)\frac{V_0}{R}\end{array}\right..$$

(25)

2.3. Voltage Stress of Switches and Diodes for HG-SIQBC

The voltage and current stress calculations of the power semiconductor switch are essential for ensuring proper component selection and reduced power loss of the converter [21]. The voltage stress across the power switch can be determined as shown in Figure 8.

$$V_{sw}-V_{C_2}=0.$$

(26)

Substituting, the value of V_C2 from Equation (15) into Equation (26) yields

$$V_{sw}=\frac{V_{in}(D-2)}{2{(1-D)}^2}.$$

(27)

Applying KVL to Figure 5 and Figure 6, the voltage stress across the diodes can be obtained. For example, the voltage stress across the diode D₁ can be determined from the equivalent circuit shown in Figure 9.

$$V_{D_1}=V_{L_1}=V_{in}+V_{C_1}-V_{C_2}$$

(28)

$$=V_{in}+\frac{V_{in}D(D-2)}{2{(1-D)}^2}-\frac{V_{in}(D-2)}{2{(1-D)}^2}$$

(29)

$$=V_{in}+V_{in}\frac{D(D-2)}{2{(1-D)}^2}\left[D-1\right].$$

(30)

Therefore,

$$V_{D1}=V_{in}\left[\frac{3D-4}{2(D-1)}\right].$$

(31)

Similarly, the voltage stress across other diodes is determined using the following expressions:

$$\left\{\begin{array}{l}{V}_{D_{11}}=\frac{V_{in}}{2}\\ V_{D_{12}}=\frac{V_{in}}{2}\\ V_{D_2}=\left(\frac{D(D-2)}{2{(1-D)}^2}\right)V_{in}\\ V_{D_3}=\left(\frac{D-2}{2(1-D)}\right)V_{in}\end{array}\right.\left\{\begin{array}{l}{V}_{D_4}=\left(\frac{(D-2)}{2{(1-D)}^2}\right)V_{in}\\ V_{D_5}=\left(\frac{D-2}{2(1-D)}\right)V_{in}\\ V_{D_6}=\left(\frac{(D-2)(D-3)}{2{(1-D)}^2}\right)V_{in}\end{array}\right..$$

(32)

2.4. Current Stress of Switches and Diodes for HG-SIQBC

The current of the switch is given by the following equation [18]:

$$I_{sw}=\left(I_{in}+I_{C_2}\right)D.$$

(33)

Similarly, the current stress of the diodes can be calculated by applying KCL to Figure 5 and Figure 6. For example, the current stress of the diode D₁ is given as

$$I_{D_1}=I_{in}=D\left(\frac{{(D-2)}^2}{2{(1-D)}^2}\right)\frac{V_0}{R}.$$

(34)

Similarly,

$$I_{D_2}=I_{in}+I_{C_3}$$

(35)

$$=\left(\frac{{(D-2)}^2}{2{(1-D)}^2}\right)\frac{V_0}{R}+\left(\frac{D}{1-D}\right)\frac{V_0}{R}.$$

(36)

Therefore,

$$I_{D_2}=\left(\frac{4-D(D+2)}{2{(D-1)}^2}\right)\left(\frac{V_0}{R}\right).$$

(37)

In the same manner, the current stress on other diodes is determined as given below.

$$\left\{\begin{array}{l}{I}_{D_{11}}=\frac{{(D-2)}^2}{4{(1-D)}^2}\left(\frac{V_0}{R}\right)\\ I_{D_{12}}=\frac{{(D-2)}^2}{4{(1-D)}^2}\left(\frac{V_0}{R}\right)\\ I_{D_3}=\left(\frac{D(-7D^2+8D-4)}{4D^2-6D+2}\right)\frac{V_0}{R}\end{array}\right.,\left\{\begin{array}{l}{I}_{D_4}=\left(\frac{3(D-2)D+4}{2-4D}\right)\frac{V_0}{R}\\ I_{D_5}=\left(\frac{D^2}{1-D}\right)\frac{V_0}{R}\\ I_{D_6}=D\frac{V_0}{R}\end{array}\right..$$

(38)

2.5. Design Consideration of HG-SIQBC Configuration

2.5.1. Current Ripple of Inductors for HG-SIQBC

The current of all inductors increases as the input voltage is applied. The peak-to-peak ripple in the current of inductors L₁, L₂, and L₃ can be derived as follows:

$$\left\{\begin{array}{l}\Delta I_{L_1}=\frac{V_{L_1}}{L_1}D{T}_s=\frac{D{V}_{in}}{2L_1{f}_s}\\ \Delta I_{L_2}=\frac{V_{L_2}}{L_2}D{T}_s=\frac{D{V}_{in}}{2L_2{f}_s}\\ \Delta I_{L_3}=\frac{V_{L_3}}{L_3}(1-D)T_s=\frac{D(D-2)V_{in}}{2(1-D)L_3{f}_s}\end{array}\right.,$$

(39)

where f_s is the switching frequency of the power switches.

The design values of inductors are calculated with the known values of D, V_in, and f_s.

2.5.2. Voltage Ripple of Capacitors for HG-SIQBC

The voltage ripple of the capacitors C₁, C₂, C₃, and C₀ is calculated using the current given in Equations (3) and (6); substituting the values of I_C1, I_C2, I_C3, and I_C0, we get

$$\left\{\begin{array}{l}\Delta V_{C_1}=\frac{I_{C_1}}{C_1}(1-D)T_s=\frac{V_0(3D^2+6D-4)}{R\ast 2{(1-2D)}^2{C}_1{f}_s}\\ \Delta V_{C_2}=\frac{I_{C_2}}{C_2}D{T}_s=\frac{V_{0}D(3D^2+6D-4)}{R\ast 2{(1-2D)}^2(D-1)C_2{f}_s}\\ \Delta V_{C_3}=\frac{I_{C_3}}{C_3}(1-D)T_s=\frac{V_0{D}^2}{R{C}_3{f}_s}\\ \Delta V_{C_0}=\frac{I_{C_0}}{C_0}D{T}_s=\frac{V_{0}D}{R{C}_0{f}_s}\end{array}\right..$$

(40)

2.6. Efficiency Analysis of HG-SIQBC Configuration

To determine the efficiency of the proposed HG-SIQBC converter, the power losses due to the inductors, capacitors, diodes, and switch are calculated as described below.

The power losses of the inductor can be derived as

$${\displaystyle \sum _{i=1}^3{P}_{L_i}}=R_{L_1}\ast I^2{}_{L_i,rms}.$$

(41)

The power losses of the capacitor can be derived as

$${\displaystyle \sum _{i=0}^3{P}_{C_i}}=R_{C_1}\ast I^2{}_{C_i,rms}.$$

(42)

The power losses of the capacitor can be derived as

$${\displaystyle \sum _{i=1}^6{P}_{D_i}}={\displaystyle \sum R_F{}_{D_1}\ast I^2{}_{D_i,rms}+{\displaystyle \sum V_{F{D}_1}\ast I_{D_i}}}.$$

(43)

The total power loss of the converter is given by

$$P_{Total}=P_{R_{DS}}+P_{SW},$$

(44)

$$P_{R_{DS}}=I^2{}_{sw}\ast R_{DS},$$

(45)

$$P_{SW}=V^2{}_{sw}\ast C_s\ast f_s,$$

(46)

where P_RDS is the conduction loss, P_SW is the switching loss, V_sw is the voltage stress of the switch, I_sw is the current stress of the switch, f_s is the switching frequency, R_DS is the ON state resistance of the switch, and C_s is the parasitic switch capacitance.

Then, the efficiency of the proposed HG-SIQBC converter can be calculated as follows:

$${\eta }_{\mathrm{Proposed}\mathrm{HG}\text{-}\mathrm{SIQBC}}=\frac{P_0}{P_0+P_L+P_C+P_D+P_{Total}}.$$

(47)

The converter loss breakdown chart for the HG-SIQBC topology is shown in Figure 10.

2.7. Simulation Results of Proposed HG-SIQBC

To observe the performance of the converter, simulations were performed using the MATLAB/SIMULINK tool. The following parameters were considered for the simulation: for a 1 kW system, DC input voltage = 75 V, output voltage = 400 V, inductor L₁ = L₂ = 2.8 mH, L₃ = 50 µH, capacitor C₁ = 100 µF, C₂ = C₃ = 50 µF, C₀ = 470 µF, load resistance R_L = 160 Ω, and switching frequency f_s = 10 kHz.

The closed-loop control system for the proposed HG-SIQBC with a PI-based voltage controller is presented in Figure 11. The PI controller parameters K_p and K_i were chosen as 0.001 and 0.1 respectively. The output voltage (V₀) was compared with the reference voltage, generating an error signal. This error (e₁) was processed in the PI controller. The output of this controller was compared with a high-frequency repeating sequence signal, and the required PWM signal for the switch was generated. To match with the rating of the DC bus voltage, the reference voltage (V_ref) was considered as 400 V. The performance of the converter was analyzed in terms of rise time, settling time, overshoot (%), and regulation (%), corresponding to the load variation for three different values of input voltages. The plot for output voltage response and load current of the converter concerning variations in load resistance is shown in Figure 12.

At t = 0.5 s, an undershoot of 7.5% of V₀ occurred with a step increase in load from 2.5 A to 5 A. The output voltage returned to the steady state within 0.04 s. Similarly, an overshoot of 5% of V₀ occurred at t = 1.2 s with a step decrease in load from 5 A to 2.5 A. The output voltage returned to the steady state within 0.06 s. Thus, the proposed converter is well suited for integrating PV with the DC grid. Hence, the performance was analyzed by considering the change in input voltage due to a change in irradiance. For each input voltage range, the load was varied from 160 Ω to 320 Ω with a step increase of 20 Ω. The performance parameters for the proposed HG-SIQBC are calculated and presented in

Table 2. Performance parameters of proposed HG-SIQBC for V_in = 75 V.

Vin = 75 V			Vref = 400 V
R (Ω)	Rise Time (s)	Setting Time (s)	Overshoot (%)	Regulation (%)	Measured Output (V)
160	0.035	0.15	10	0.05	399.8
180	0.035	0.15	10.5	0	400
200	0.035	0.155	10.875	0.025	399.9
220	0.035	0.16	11.125	0.25	399
240	0.034	0.17	11.45	0.25	399
260	0.032	0.175	11.625	0	401.3
280	0.032	0.175	11.95	0.175	399.3
300	0.032	0.178	12.075	0	401.6
320	0.033	0.178	12.2	0.05	399.8
80	0.04	0.13	5.5	0.1	399.6

,

Table 3. Performance parameters of proposed HG-SIQBC for V_in = 150 V.

Vin = 150 V			Vref = 400 V
R (Ω)	Rise Time (s)	Setting Time (s)	Overshoot (%)	Regulation (%)	Measured Output (V)
80	0.004	0.03	1.375	0.075	399.7
160	0.00346	0.05	3.4	0.05	399.8
180	0.00346	0.0535	3.5	0	400
200	0.00346	0.006	3.575	0.025	399.9
220	0.00335	0.066	3.75	0.05	399.8
240	0.00334	0.0662	4.2	0.05	399.8
260	0.00335	0.07	4.375	0.05	399.8
280	0.0034	0.08	4.55	0.05	399.8
300	0.0035	0.085	4.55	0.05	399.8
320	0.0033	0.085	4.75	0	400

and

Table 4. Performance parameters of proposed HG-SIQBC for V_in = 250 V.

Vin = 250 V			Vref = 400 V
R (Ω)	Rise Time (s)	Setting Time (s)	Overshoot (%)	Regulation (%)	Measured Output (V)
160	0.0012	0.008	6.25	0.275	398.9
180	0.00119	0.009	6.35	0.2	399.2
200	0.0011	0.016	6.4375	0	400
220	0.00116	0.018	6.5	0.075	399.7
240	0.00112	0.12	6.56	0.175	399.3
260	0.00115	0.12	6.56	0.175	399.3
280	0.00119	0.125	6.625	0.175	399.3
300	0.00119	0.125	6.6875	0.2	399.2
320	0.0012	0.125	6.725	0.2	399.2
80	0.00115	0.1	5.35	0.2	399.2

.

From the above tables, it can be observed that the output voltage of the converter is well regulated, becoming settled earlier for wide range of load variations. The output voltage response corresponding to input voltage variation is shown in Figure 13.

During the time interval of t = 0 to 0.6 s, the input voltage was maintained at 75 V. At t = 0.6 s, an overshoot of 17.5% of V₀ occurred with a step increase in input voltage from 75 V to 150 V, and it settled down to 400 V within 0.04 s. Similarly, an overshoot of 14% of V₀ occurred with a step increase in input voltage from 150 V to 250 V, and the output voltage returned to the steady state within 0.04 s. The respective changes are depicted in Figure 13. Despite the input voltage variation, the output voltage became regulated and returned to the desired level within a fraction of seconds. The output voltage response for a step change in load resistance is given in Figure 14.

During the time interval of t = 0 to 0.5 s, the output voltage V₀ was in the range of 400 V for a rated load current of 2.5 A. When the load was changed from the rated value, there was a step increase in load current from 2.5 A to 5 A at t = 0.5 s. An undershoot occurred for a minimum duration of 0.04 s before returning to the steady-state value. Again, at t = 0.8 s, the load current increased to 7.5 A with an undershoot of 4.5% of V₀ for 0.045 s. Finally, the load decreased from 7.5 A to 2.5 A at t = 1.1 s. There was an overshoot of 9.5% of V₀ for a duration of 0.06 s. For the step increase/decrease in load current, V₀ quickly settled down to nominal value. The respective changes are depicted in Figure 14.

From Table 2, Table 3 and Table 4, it is evident that the proposed converter can operate for a wide range of load variations. It can also operate at the desired conditions for input voltage variations. The parameters such as rise time, settling time, overshoot, and regulation were analyzed. A graphical representation of these parameters with respect to load resistance change is given in Figure 15a–c.

3. Modified Multilevel Inverter

The proposed inverter is a combination of a cascaded H-bridge inverter and symmetrical semiconducting switches. The switches in the H-bridge topology operate with a frequency of 50 Hz, while other switches operate with a frequency of 100 Hz. Two different frequencies are used, and the stepped voltage waveform is obtained. Thus, it can also be called a hybrid switching inverter. The circuit configuration is shown in Figure 16.

The switching sequence for the proposed MLI is given in

Table 5. Switching sequence for proposed MLI.

Voltage Levels	S1	S2	S3	S4	S5	S6	S7	S8	S9
5 Vdc	1	0	1	0	1	1	1	1	1
4 Vdc	1	0	1	0	1	1	1	1	0
3 Vdc	1	0	1	0	1	1	1	0	0
2 Vdc	1	0	1	0	1	1	0	0	0
Vdc	1	0	1	0	1	0	0	0	0
0	0	1	0	1	0	0	0	0	0
−Vdc	0	1	0	1	1	0	0	0	0
−2 Vdc	0	1	0	1	1	1	0	0	0
−3 Vdc	0	1	0	1	1	1	1	0	0
−4 Vdc	0	1	0	1	1	1	1	1	0
−5 Vdc	0	1	0	1	1	1	1	1	1

.

Modes of Operation

For the positive cycle, to obtain a voltage level of 5 V_dc, the switches S₁ and S₃ of the H-bridge are kept in the ON state, and the switches S₅–S₉ are also turned on to produce the positive level of the output voltage. The equivalent circuit for this mode is shown in Figure 17a. Figure 17b shows the equivalent circuit of stage II operation of a multilevel inverter. In this stage, to obtain the voltage level of 4 V_dc, the switches S₁ and S₃ of the H-bridge are kept in the ON state, and the switches S₅–S₈ are also turned ON. Here, the diode connected in an antiparallel manner with S₉ is forward-biased, and the current flows through it. From Figure 17c, a voltage of 3 V_dc is obtained by turning ON the switches S₁ and S₃ of the H-bridge and the switches S₅–S₇. The current flows through the diodes associated with S₈ and S₉ switches. To obtain the voltage of 2 V_dc, the switches S₁ and S₃ of the H-bridge are in the ON state, and the bidirectional switches S₅–S₆ are also turned ON. The diodes connected in antiparallel with S₇, S₈, and S₉ become forward-biased due to the flow of current passing through it. The equivalent circuit for this mode is shown in Figure 17d. To obtain a positive level voltage V_dc, the switches S₁ and S₃ of the H-bridge are in the ON state and the bidirectional switch S₅ is also turned on to produce a positive level of the output voltage. The diodes connected with the switches S₆, S₇, S₈, and S₉ are in conduction mode due to the flow of current through them. The equivalent circuit for this mode is shown in Figure 17e.

Similarly, the negative cycle operation occurs with S₂ and S₄ in the ON condition. The equivalent circuit for this mode is shown in Figure 18a–e.

The pulse pattern waveform and the output voltage waveform simulated in MATLAB/SIMULINK are given in Figure 19.

The pulse pattern for switches S₁–S₄ is shown on the first four axes of the figure, followed by the pulse patterns of switches S₅–S₉. The waveform shown on the last axis describes the output voltage of the 11-level inverter.

4. Hardware Results of Five-Level Modified Multilevel Inverter

The design of a modified multilevel inverter with a single source was carried out for delivering five levels of output voltage. To generate the required output voltage level, the circuit diagram shown in Figure 16 was modified with a single DC source with an H- bridge comprising switches S₁–S₄ and power semiconductor switches S₅ and S₆. To verify the theoretical results and to analyze the performance of the system, the proposed inverter was tested experimentally for the following input and output data specifications: V_dc = 60 V, V_ac = 60 V, with a fundamental switching frequency of 50 Hz for H-bridge and 100 Hz for the switches S₅ and S₆. The value of the capacitors C1, C₂, and C₃ was 0.1 F. The hardware setup of the multilevel inverter with five levels is shown in Figure 20. The proposed design was fed with a DC supply voltage of 60 V using a regulated power supply (RPS), and an output of 60 V AC was generated. The SPARTAN FPGA controller provided the necessary gating signals for the MOSFETs connected to the inverter circuit. The gate pulse waveforms of different switches are shown in Figure 21. The output values were also measured and analyzed with the help of a digital storage oscilloscope.

Figure 22 shows that the proposed inverter produced an output voltage two times greater than the given input. This reduced switch multilevel inverter is highly recommended for PV, grid-connected, and EV applications.

5. Conclusions

In this paper, different configurations of power electronic converters were proposed and analyzed with the controllers. A novel HG-SIQBC topology was designed and developed in a MATLAB/SIMULINK environment. The voltage stress across the main switch was low and found to be 4.25% of the total losses. The efficiency calculation of the proposed topology shows that the proposed converter had a better efficiency of 91.31%. The HG-SIQBC topology investigated in this paper was tested for a change in input voltage, as well as for a change in load conditions. The controller performance was also analyzed for a wide range of loads. The equivalent output level of the novel converter topology was fed to a modified five-level inverter using a regulated power supply and tested experimentally. It can be extended for higher-level configurations. Thus, suitable configurations for microgrid applications were designed and tested under different conditions.