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Article

THD Reduction of Distribution System Based on ASRFC and HVC Method for SVC under EV Charger Condition for Power Factor Improvement

Department of Electrical Engineering, Yeungnam University, Gyeongsan 38541, Korea
*
Author to whom correspondence should be addressed.
Symmetry 2016, 8(12), 156; https://doi.org/10.3390/sym8120156
Submission received: 31 October 2016 / Revised: 12 December 2016 / Accepted: 13 December 2016 / Published: 20 December 2016
(This article belongs to the Special Issue Symmetry in Systems Design and Analysis)

Abstract

:
Electric vehicles (EVs) have been gaining popularity in recent years due to growing concerns about fuel depletion and increasing petrol prices. Random uncoordinated charging of multiple EVs at residential distribution feeders with moderate penetration levels is expected in the near future. This paper describes a high performance voltage controller for the EVs charging system, and proposes a scheme of asymmetric synchronous reference frame controller (ASRFC) in order to compensate for the voltage distortions and unbalance distribution system due to EVs charger. This paper explores the power factor of distribution and residential network under random EVs charger on the bus load. ASRFC and harmonic voltage compensator (HVC) are employed for static VAR compensator (SVC) in this paper. The proposed scheme can improve the power factor and total harmonic distortion (THD) of the smart grid due to the EVs charger in grid. The effectiveness of the scheme was investigated and verified through computer simulations of a 22.9-kV grid.

1. Introduction

Electric vehicles (EVs) could be an important contributor to the reduction of greenhouse gases in the transport sector. EVs are expected to have a large share in future transportation systems, which will cause an additional load on the electric grid. Concerns have been raised about the impacts of a large fleet of EVs on the electricity distribution grid. The main problem is the peak load of charging [1]. Since a majority of EVs will be charged at home, it is expected that vehicles will be plugged in when their owners arrive at home at the end of the afternoon. The simultaneous charging of several EVs will lead to a considerable additional load that can overload the grid.
To mitigate these problems, the charging cycle of EVs must be managed. The concept of coordinated charging is being explored through smart grids, where the exchange of information using several communication technologies can improve the efficiency, reliability, economics, and sustainability of the production and distribution of electricity [1]. The impacts of EVs are determined through regional grid analysis based on the number of vehicles, vehicle demand profile, and the effect of supply and demand. High penetration of plug-in EVs will likely be envisioned by the transportation and energy authorities in many parts of the world, such as European countries, Japan, Korea, and the USA.
It is well known that random deployment and charging of EVs in a distribution network causes many problems, such as overloading of distribution transformers, bus voltage fluctuations, and unbalanced loading [2,3,4,5,6,7,8,9,10,11].
Among the various compensation devices available, controllers based on voltage source converters (VSCs) can have an extremely fast response to reactive power demand and thus can be effectively used for correcting the power factor and for voltage regulation. One such controller called the distribution static compensator (DSTATCOM) is a viable alternative to the conventional static VAR compensator (SVC) [12]. The SVC is an important component of a flexible alternate current (AC) transmission system. It provides an effective approach to correct and increase the power factor, enhance voltage stability, and increase the power transfer capability when an unbalanced load happens in the power system (for example, when an electric vehicle (EV) is connected to the grid for charging).
The SVC has fast dynamic characteristics that can support the effective system voltage following disturbances. Keeping a reactive power reserve in an SVC during steady-state operation is always needed to satisfy the reactive power requirements during system dynamics [13]. In this area, one concept that has been proposed to control SVCs is a delta-connected thyristor controlled reactor-fixed capacitor (TCR-FC) using a proportional integral derivative (PID) controller for power factor correction. However, a PID controller is complicated in comparison to a proportional integral (PI) controller in a power system. In addition, in an SVC (TCR-FC) system, a capacitor is constant in the system, and controlling the capacitor value is impossible, so it is not a good idea for achieving the best power factor correction [14]. Using an automatic capacitor to achieve the best power factor in the grid is recommended because it is very flexible for any loads that change in the grid.
The basis for the algorithm that is used in this paper to calculate the compensation susceptances associated with each phase of a delta connected three-phase SVC for power factor correction. A fuzzy logic SVC for power factor correction was presented by Hagh et al. [15]. This method is one of the best and most successful techniques among expert control strategies. It is an important tool to control nonlinear, complex, vague, and ill-defined systems, but it is slower than when a PI controller that is used for SVC.
Using more power electronics and nonlinear loads such as EVs causes harmonic problems in the power system. These loads generate harmonic currents that incur many undesirable effects, such as voltage distortion, higher losses, and disturbances of communication equipment [16]. Shunt active filters have been proposed to mitigate harmonic contamination in a power system. The use of shunt active power filters (APFs) is based on the principle underlying the shunt harmonic current compensation approach, in which harmonic currents are injected into an AC system through a current-controlled voltage source inverter to compensate for harmonic currents drawn by a distorting load [17].
The active resonance damper (ARD) mitigates the effects of harmonic distortion (the resonance along the distribution line) rather than addressing the cause of such distortion (the current harmonics) [18,19]. The HVC is an active power filter that compensates for harmonic voltage by injecting harmonic currents to compensate for those of a distorting load. The HVC generates harmonic voltages to compensate for those at the point of common coupling (and at the neighbor buses) [17].
Different approaches have been proposed to diminish the voltage distortion in loads when EVs are connected with a point of common coupling (PCC). A selected harmonic compensation method that uses the discrete Fourier transforms (DFT) and a synchronous reference frame controller (SRFC) has been proposed [20]. However, the DFT method requires too much computation and it is not feasible. In addition, using the ASRFC requires knowledge of the leading angle, which compensates for the system delay. The effectiveness of the proposed scheme has been investigated and verified through computer simulations of a 22.9-kV grid.

2. Static VAR Compensator (SVC)

Static VAR systems are applied by utilities in transmission applications for several purposes. The primary purpose is usually the rapid control of voltage at weak points in a network. Installations may be at the midpoint of transmission interconnections or at the line ends for compensation of irregular load, voltage, and source power factors in the power system. SVCs are shunt connected static generators/absorbers whose outputs are varied to control the voltage and power factor of the electric power systems. In its simple form, an SVC is connected as a thyristor switch capacitor-thyristor controlled reactor (TSC-TCR) configuration, as shown in Figure 1. The SVC is connected to a coupling transformer that is connected directly to the AC bus whose voltage/power factor source is to be regulated.

2.1. SVC (V-I) Characteristics

The SVC can be operated in two different modes: voltage regulation mode (where the voltage is regulated within limits as explained below) and VAR control mode (where the SVC susceptance is kept constant). When the SVC is operated in voltage regulation mode, it implements the following V-I characteristics. SVC steady-state control characteristics in its simple form are shown in Figure 2. As long as the SVC susceptance B stays within the maximum and minimum susceptance values imposed by the total reactive power of capacitor banks (Bcmax) and reactor banks (Blmax), the voltage is regulated at the reference voltage Vref. However, a voltage drop is normally used (usually between 1% and 4% of the maximum reactive power output), and the V-I characteristic curve has the slope indicated in Figure 2.
The V-I characteristic is described by the following three equations:
V = V ref + X s I    SVC   is   regulation   rang   ( B c max < B < B l max )
V = 1 B c max    SVC   is   fully   capacitive   ( B = B c max )
V = 1 B l max     SVC   is   fully   indutive   ( B = B l max )
where
  • V:  Positive sequence voltage (p.u.)
  • I:   Reactive current (p.u./Pbase) (I > 0 indicates an inductive current)
  • Xs:  Slope or droop reactance (p.u./Pbase)
  • Bcmax:  Maximum capacitive susceptance (p.u./Pbase) with all TSCs in service, no TSR or TCR
  • Blmax:  Maximum inductive susceptance (p.u./Pbase) with all TSRs in service or TCRs at full conduction, no TSC
  • Pbase:  Three-phase base power specified in the block dialog box

2.2. SVC Dynamic Response

When the SVC is operating in voltage regulation mode, its response speed for a change of system voltage depends on the voltage regulator gains (proportional gain Kp and integral gain Ki), the droop reactance Xs, and the system strength (short-circuit level). For an integral-type voltage regulator (Kp = 0), if the voltage measurement time constant Tm and the average time delay Td due to valve firing are neglected, the closed-loop system consisting of the SVC and the power system can be approximated by a first-order system with the following closed-loop time constant:
T c = 1 K i ( X s + X n )
where
  • Tc: Closed loop time constant
  • Ki: Proportional gain of the voltage regulator (p.u._B/p.u._V/s)
  • Xs: Slope reactance p.u./Pbase
  • Xn: Equivalent power system reactance (p.u./Pbase)
This equation demonstrates that the response is faster when the gain is increased or when the system short-circuit level decreases (higher Xn values).

3. Analysis of EVs Connected Phase Voltage

Large loads in the power system are mostly three-phase symmetrical loads. Unbalance is mainly caused by single-phase loads, such as single-phase electric railways, single-phase electric furnaces (induction or arc furnaces), and single-phase charging of electrical vehicle. Unbalance can also occur under fault conditions in a power system (short circuits) as a result of incorrect operation of switching devices, conductor abruptions, etc. All these cases usually have a short duration (excluding single-line-to-ground faults in systems with neutral not grounded or grounded via impedance). Unbalance is also caused by voltage and current harmonics.
The Fortes cue method of symmetrical components is used in calculations of unbalanced load-connected phase voltage:
[ X 0 X + X ] = 1 3 [ 1 1 1 1 a a 2 1 a 2 a ] [ X A X B X C ]
where XA, XB, and XC are the phasors of the unbalanced phasor system; X0, X+, and X are the phasors of symmetrical components (zero, positive, and negative sequence, respectively); and a = 1 < 120° is a unit complex operator.

Unbalance Caused by EVs in the Phase Voltage

A. EVs connected to single-phase voltage
Consider one EV connected as in Figure 3 to phase voltage VA.
The currents in the line’s conductors according to the figure are:
I A , I B = 0 , I C = 0
The phasors of symmetrical components can be determined using Equation (5):
I 0 = 1 3 ( I A + I B + I C ) = 1 3 I A I + = 1 3 ( I A + a I B + a 2 I C ) = 1 3 I A I = 1 3 ( I A + a 2 I B + a I C ) = 1 3 I A
The neutral conductor is loaded by the following current:
I N = 3 I 0 = I A
As shown in Equation (7), zero sequence components are created in the line for this load, and phasors of all symmetrical components have equal amplitudes. Unbalanced current flowing in a one-phase conductor and the neutral conductor creates voltage drops, and the balanced voltage system is distorted [21].
B. EVs connected to two single-phase voltages
Two single-phase EVs are connected as in Figure 4 to two different phase voltages VA and VB.
The currents in the line’s conductors according to the figure are:
I A , I B , I C = 0
Phasors of symmetrical components can again be determined using Equation (5):
I 0 = 1 3 ( I A + I B + I C ) = 1 3 ( I A + I B ) I + = 1 3 ( I A + a . I B + a 2 . I C ) = 1 3 ( I A + a . I B )    I = 1 3 ( I A + a 2 I B + a I C ) = 1 3 ( I A + a 2 I B )
In addition, for two loads connected this way, zero sequence components are created. The neutral conductor is loaded by the following current:
I N = 3 I o = I A I B
C. EVs connected to three single-phase voltages
EVs connected to three single-phase voltages (Figure 5) can often be found in low voltage (LV) networks in residential areas. Three-phase connected loads are symmetrical, and can only operate as asymmetrical in the case of failure (for a certain period of time). The three-phase load’s neutral may or may not be connected with the transformer’s neutral.
The negative and zero sequence current unbalance factors have non-zero values in the case of three different single-phase loads in Figure 5 and for an asymmetrical three-phase load with its neutral connected to a neutral conductor. When a load is connected to a source with sufficiently firm voltages, line voltages will stay unchanged. The positions of phase voltage phasors will be shifted due to the voltage drop on the neutral conductor, which is loaded by the current IN = −3.I0. When unbalanced voltage drops in phase conductors of the line are also taken into account, the line voltages at the point of common coupling will be unbalanced too.

4. Description of System

This fundamental network used for this paper is IEEE 14-node test feeder [22], as shown in Figure 6. The network is downscaled from 22.9 kV to 230 V based on the Korea standard so this grid topology shows residential fundamental network. Each node is connected to residential load and some nodes choose randomly for charging EVs.
Assume that an SVC comprising one TCR bank and three TSC banks is connected to a 22.9-kV bus via a 333-MVA, 22.9/16-kV transformer on the secondary side with Xk = 15%. The voltage drop of the regulator is 0.01 pu/100 VA (0.03 pu/300 VA). When the SVC operating point changes from fully capacitive to fully inductive, the SVC voltage varies between 1 − 0.03 = 0.97 pu and 1 + 0.01 = 1.01 pu.

5. Assumptions and Modeling EV Charging

5.1. Specification of EVs

The batteries contained in EVs have a superlative capacity of 11 kWh [23]. Thus, 80% of battery capacity can be used to recuperate the life presumption which gives an available capacity of 8.8 kWh, while 10 kWh is required from the utility grid. The energy conversion efficiency from AC energy absorbed from utility grid to direct current (DC) energy stored in the battery of vehicle is assumed to be 88% [24]. Because the battery can only be charged and discharged which means the energy flow is unidirectional and so vehicle to grid is not designed yet. Charge of 4 kW is considered because maximum out power of standard single phase 230 V outlet is 4.6 kW and can be easily used at home without reinforcing the wiring.
Fast charging is not supported because it require higher shot circuit power, not available at standard electric outlet in household also indispensable at high voltage level [25].

5.2. Mathematical Models

In cases where the behavior of humans has an impact on a given system, it becomes inevitable to consider that any involvement of individuals includes some uncertainty and modeling such a system mathematically introduces challenges. Mathematical models include stochastic models, Markov models and multinomial logit models. Markov models are more advantages in comparison other models in order to find estimates of the random variables. Moreover, the future behavior of EV users can be estimated using simulations with stochastic models in order to estimate the impact to the electric system a large-scale EV introduction would lead to [26].

Stochastic Models

In the case where random systems are modeled and uncertainty exists, stochastic models can be used where the expected value would be the mean value for an infinite number of observations of the stochastic variable. Deterministic models could be less complicated and require less simulation time than stochastic models. However, with stochastic models it may be possible to describe a complex system more realistic than with a deterministic model. With Monte Carlo methods it is possible to estimate expected values by running simulations for a number of random observations of any stochastic variable and using these observations to estimate the expected value of the output variable by calculating the mean value [27]:
E [ W ]    w ¯ = 1 N j = 1 N W j
For these observations, it is also possible to estimate the standard deviation:
S [ W ]    1 N j = 1 N ( W j w ¯ ) 2
The estimate of any expected value is likely to be closer to the expected value E[W] the more observations N of the random variable that is used for calculating the mean value w ¯ [26].

5.3. Modeling of Static VAR Compensator in Power System Studies

The SVC provides an excellent source of rapidly controllable reactive shunt compensation for dynamic voltage control through its utilization of high-speed thyristor switching/controlled reactive devices. In general, the concepts of TCRs and TSCs are used in SVCs. The TSC provides a “stepped” response, and the TCR provides a “smooth” or continuously variable susceptance. Figure 7 illustrates a TCR/TSC including the operating process concept.
The control objective of the SVC is to maintain the desired voltage in a high voltage bus. In steady state, the SVC will provide some steady-state control of the voltage to impound it the highest condition at a pre-defined level. When the load is changed in the power system, the power factor is decreased. For improvement of the power factor, the SVC will inject reactive power into the system (within its control limits) to increase the power factor of the system.
When 1.5 times the load is connected between A-phase, like when EVs are plugged into the system, it causes an unbalanced load. Figure 8 illustrates the power factor of the system when EVs are plugged into the grid without an SVC.
As can be seen in Figure 8, the average power factor of the system is 0.83 or 83%, and the upper and lower distortion in the power factor curve is 0.14 or 14%. For improvement of the power factor, an SVC is suggested for this system. After putting an SVC in the system (Figure 7), the power factor of the system is improved. Figure 9 illustrates the power factor of the system when EVs are plugged into the grid with an SVC.
As can be seen in Figure 9, the average power factor of the system is 0.915 or 91.5%, and the upper and lower distortion in the power factor curve is 0.09 or 9%. The problem of distortion occurring in the power factor because of plugging EVs into the system has not been solved.
The power factor of the system is improved by using the SVC and a PI controller, but it is not feasible for the system. For obtaining the best power factor, it should be direct line of power factor without distortion. To solve this problem, another controller in the system of the SVC is needed for the best result. For this reason, a synchronous frame controller is suggested for the system.

6. Description of ASRFC & HVC in the System

6.1. Asymmetric Synchronous Reference Frame Controller

In three-phase, three-wire systems (delta connected sources and loads), unbalanced loads create negative sequence currents and negative sequence voltage distortion. An unconventional control technique has been proposed by Pokorny et al. [28] to compensate for the negative sequence voltage distortion due to unbalanced loads in three-phase, three-wire systems. In addition, the construction of an Asymmetric synchronous reference frame rotating at the fundamental frequency in the direction opposite that of the positive sequence.
V c = [ v c a , v c b , v c c ] T V c ( + ) = [ v c a ( + ) , v c b ( + ) , v c c ( + ) ] T V c ( ) = [ v c a ( ) , v c b ( ) , v c c ( ) ] T V c ( 0 ) = [ v c a ( 0 ) , v c b ( 0 ) , v c c ( 0 ) ] T
Thus, fundamental components of the output voltage will become DC quantities in the negative sequence reference frame dq. With a parallel controller in dq, the negative sequence distortion can be attenuated or even eliminated if an integral controller is used.
Asymmetric Synchronous reference frame controller is one of the best solutions for the control of grid connected converters. This technique is based on the implementation of controllers that lies on rotating reference frames which are synchronized with the frequency component to be injected. If the fundamental component of the grid current must be injected, the asymmetric synchronous reference frame (ASRF) is synchronized with the fundamental positive-sequence voltage phase angle (θ+). The main advantage of using an ASRF is that the measured ac currents and voltages of the proper sequence are transformed into DC magnitudes, in the so-called dq frame, by using Park’s transformation [27].
As long as DC magnitudes are involved, classical control techniques can be used so that a PI controller can be designed in order to achieve the desired performance
e j θ = [ cos ( θ ) sin ( θ ) sin ( θ ) cos ( θ ) ] ;            j = [ 0 1 1 0 ]
However, under unbalanced grid-voltage conditions, negative sequence voltage appears and the control of negative-sequence currents may become necessary. In this case, two dq synchronous controllers synchronized with the respective angular position of each sequence (θ+ and θ−) would be needed [29].
Figure 10 shows the structure of ASRF-PI voltage controller. The objective of this controller is to maintain the three-phase voltage at a certain magnitude, regardless of the loading condition have shown the feasibility of an ASRFC, which can eliminate the effects of both non-linear and unbalanced loads if each strategy is combined. Figure 11 shows a concept of an ASRFC for unbalanced load compensation [21,28,30]. The negative sequence controller in the scheme compensates the negative voltage distortion due to unbalanced load with the asymmetric synchronous reference frame rotating at the fundamental frequency in the opposite direction to the positive sequence.
In this scheme, the negative sequence components of the feedback voltage VNd and VNq are pulsating at two times the fundamental frequency under the unbalanced load, and PI controllers do not operate in a pure DC domain. Therefore, to ensure zero tracking error in this scheme, a voltage control bandwidth over 120 Hz and no delay in measuring the output voltages are required.

Negative-Sequence Voltage Compensator (NVC)

Any unbalanced output voltage can be expressed as three symmetrical components of positive, negative, and zero sequence components as follows:
V c = V c ( + ) + V c ( ) + V c ( 0 )
Figure 11 shows block diagram of NVC.
Then, the positive and negative components are obtained as:
[ v c a ( + ) v c b ( + ) v c c ( + ) ] = 1 3 [ 1 1 2 1 2 1 2 1 1 2 1 2 1 2 1 ] [ v c a v c b v c c ] 1 j 2 3 [ 0 1 1 1 0 1 1 1 0 ] [ v c a v c b v c c ]
[ v c a ( ) v c b ( ) v c c ( ) ] = 1 3 [ 1 1 2 1 2 1 2 1 1 2 1 2 1 2 1 ] [ v c a v c b v c c ] + 1 j 2 3 [ 0 1 1 1 0 1 1 1 0 ] [ v c a v c b v c c ]
where “j” is a 90° phase shift, which is accomplished by an all-pass filter as:
Y ( s ) = s 2 b s + c s 2 + b s + c X ( s )
In this scheme, the Negative Sequence Computation block (NSC) shown in Equation (19) is accomplished as shown in Figure 12. The positive sequence computation block can be similarly accomplished. Note that the NSC and positive sequence computation block (PSC) transform the unbalanced output voltage into symmetrical balanced sets, which are transformed into perfect DC quantities by the Park’s transformation:
[ v c d v c q ] = 2 3 [ cos θ cos ( θ 2 π / 3 ) cos ( θ + 2 π / 3 ) sin θ sin ( θ 2 π / 3 ) sin ( θ + 2 π / 3 ) ] [ v c a v c b v c c ]
where
  • vcd is the d-axis voltage in the synchronous reference frame.
  • vcq is the q-axis voltage in the synchronous reference frame.
Therefore, PI controllers in NVC are operated with pure DC control variables. The output contributes to the zero steady-state error for the compensation of a negative sequence component voltage distortion, regardless of the voltage control bandwidth or phase lag due to system delay with the LC filter. The zero-sequence voltage distortion is compensated by the output transformer with Delta-Wye winding. Figure 12 shows a block diagram of the negative sequence computation.

6.2. Asymmetric Synchronous Reference Frame Controller for SVC Connected to the Grid

Figure 13 shows the proposed scheme. The proposed NVC compensates the negative voltage distortion due to an EV that causes an unbalanced load. The proposed controller was added to the controller of the SVC where an unbalanced load is happening in the system because of external conditions such as when charging an EV. The NVC compensates the voltage distortion. In this method, the negative sequence of the system is computed after the EV is connected to the system for charging. The voltage reference commands are calculated according to Equations (21) and (22).
V N d * = V m cos 2 ω t
V N q * = V m sin 2 ω t
The current commands are calculated according to Equation (23). Definitions of the variables used in Equation (23) are given in Table 1 and Equations (24) and (25).
[ I N d c m d I N q c m d ] = K p I [ V N d e r r V N q e r r ]
V N d e r r = V m cos 2 ω t V N d
V N q e r r = V m cos 2 ω t V N q
In Equations (24) and (25), VNderr and VNqerr are represented by two sinusoidal functions with arbitrary magnitude (VNderr and VNqerr) and phase (ϴNd and ϴNq). It is clear that if VNderr = VNqerr and ωtNd = ωtNq (i.e., balanced load conditions), negative sequence terms will not contribute to INdcmd and INqcmd.
The main feature of the scheme is that NVC can provide zero steady state error, even if the bandwidth of the voltage control loop is not wide enough.

6.3. Asymmetric Synchronous Reference Frame Control Scheme

After using the ASRFC, the power factor of the system is improved to 0.99 or 99%, although there is some distortion in the curve of the power factor, which is illustrated in Figure 14.
As can be seen in Figure 14, the power factor of the system using the ASRFC is improved from 91.5% (average power factor) in Figure 9 to 99%, whereas some harmonic can be seen in the curve of the power factor after using the ASRFC with the PI controller in the SVC. Therefore, another controller is needed to solve this problem. One of the concepts for removing harmonics from the power factor is an HVC. This method is suggested to obtain the best power factor.

6.4. Harmonic Voltage Compensator

Consider the SVC topology represented in Figure 15, composed by three delta-connected TSC branch (CTSC) and three delta-connected TCR branches (LTCR). This is the simplest SVC topology and it is suitable for distribution grid applications, due to their reduced number of switching components. The SVC is fed by a three-phase three-wire voltage source through three balanced line impedances Zs = Rs + jωLs.
As the voltages in distribution grids may be distorted, unbalanced and asymmetrical, the source voltages are generically defined from the fundamental frequency to a determined harmonic order Kh as:
u m = k = 1 k h 2 U m k sin ( k ω t + Φ m k )            m = 1 , 2 , 3
On the SVC side, the line voltages can be written as
u s v c , 1 = u 1 R s i S V C , 1 L s d d t i S V C , 1
u s v c , 2 = u 2 R s i S V C , 2 L s d d t i S V C , 2
u s v c , 3 = u 3 R s i S V C , 3 L s d d t i S V C , 3
On which d d t i S V C , m   is the time-derivative of   i S V C , m , m = 1, 2, 3. Considering that the sum of the line voltages and currents is zero at any instant (which is also valid for their time derivatives and integrals) on the proposed circuit, the line currents can be written in terms of the currents of each SVC branch as:
i S V C , 1 = i S V C , 12 i S V C , 31
i S V C , 2 = i S V C , 23 i S V C , 12
i S V C , 3 = i S V C , 31 i S V C , 23
Thus, the SVC line-to-line voltages can be expressed as:
u S V C , 12 = u S V C , 1 u S V C , 2 = u 1 u 2 R s ( i S V C , 1 i S V C , 2 ) L S ( d d t i S V C , 1 d d t i S V C , 2 ) = u 12 ( 3 R s i S V C , 12 + 3 L S d d t i S V C , 12 )
u S V C , 23 = u 23 ( 3 R s i S V C , 23 + 3 L S d d t i S V C , 23 )
u S V C , 31 = u 31 ( 3 R s i S V C , 31 + 3 L S d d t i S V C , 31 )
From Equations (34)–(35), one may observe that in case of unbalanced line impedances, their delta-equivalent can be obtained by using a wye-delta transformation and then used in Equations (33)–(35) and in the following formulation.
By using the superposition theorem, the current of the SVC branches mn = 12, 23, 31 can be split into i S V C , m n T S C and i S V C , m n T C R in order to determine each of these components separately. Therefore, the current of each RSC branch can be expressed by:
i S V C , m n T S C = k = 1 k h 2 I T S C , m n k sin ( k ω t + ϕ T S C , m n k )
Correspondingly, the current of each TSC branch valid in the interval ta,mnttb,mn is expressed by:
I T S C , m n k = U m n k ( 3 R s ) 2 + ( 3 k ω L s 1 k ω C S V C ) 2
ϕ T S C , m n k = ϕ m n k arctan ( 3 k ω L S 1 k ω C S V C 3 R s )
From the SVC capacitor’s equivalent impedance, the resonant frequency between CSVC and Ls is calculated by:
f 0 = 1 2 π 3 L s C S V C
Correspondingly, the current of each TCR branch valid in the interval ta,mnttb,mn is expressed by:
i S V C , m n T C R = k = 1 k h 2 I T C R , m n k sin ( k ω t + ϕ T C R , m n k ) C m n
I T C R , m n k = U m n k ( 3 R s ) 2 + ( k ω ( L T C R + 3 L S ) ) 2
ϕ T C R , m n k = ϕ m n k arctan ( k ω ( L T C R + 3 L s ) 3 R s )
Terms ta and tb are the instants that delimit the conduction time interval of each TCR and TSC thyristor. If a phase reference signal synchronized with the fundamental-frequency line-to-line voltages is used to control the thyristors switching, the TCR and TSC current semi-cycles are symmetrical.
t a , m n = α m n ω ,         t b , m n = t i 0 , m n α m n π / 2 ω
Thus, the conduction time interval of each TCR and TSC thyristor is the same and on which αmn is the conduction angle of the TCR and TSC branch mn and ti0,mn may be determined iteratively for each semicycle of i S V C , m n T C R   and   i S V C , m n T S C by incrementing t until reach the following conditions: i S V C , m n T C R = 0   and   i S V C , m n T S C = 0 and d d t i S V C , m n T C R < 0   &   d d t i S V C , m n T S C < 0 For the positive semicycle and i S V C , m n T C R = 0   and   i S V C , m n T S C = 0 and d d t i S V C , m n T C R > 0   &   d d t i S V C , m n T S C > 0 For the negative semicycle.
Additionally, i S V C , m n T C R = 0 and i S V C , m n T S C = 0 for t < ta,mn and t > tb,mn. Term Cmn is the integration constant and may be determined for each ta as:
C m n = k = 1 k h 2 I T C R , m n k sin ( k ω t + ϕ T C R , m n k )
Finally, the current of SVC branches are expressed by:
i S V C , 12 = i S V C , 12 T S C + i S V C , 12 R C R
i S V C , 23 = i S V C , 23 T S C + i S V C , 23 R C R
i S V C , 31 = i S V C , 31 T S C + i S V C 31 R C R
The SVC line currents can be determined by using Equations (30)–(32) [31].
The HVC in the proposed scheme is designed to compensate the selected harmonic voltage distortion due to nonlinear loads. The scheme shows a sample of 5th and 7th harmonic compensation the symmetrical balanced harmonic component of the output voltage can be obtained by a dedicated bandpass filter with characteristic frequency corresponding to the selected harmonic frequency to be compensated. The bandpass filters in the scheme output symmetrical balanced sets of the 5th and 7th harmonic components, which can be transformed into DC quantities by the Park transformation. Likewise, PI controllers in HVC are used with pure DC control variables, which can provide zero steady-state errors for a selected harmonic frequency. The HVC does not require knowledge of the system parameters, the leading angle to compensate for system delay with an LC filter, or a fast switching frequency. In conclusion, the NVC and HVC operate as feed-forward controllers for the compensation of voltage distortion. Figure 16 shows the HVC’s block diagram.
Using the SRFC in the power system causes some distortion to be created in the grid and affects the power factor system. To solve this problem, the HVC is needed to obtain the best power factor. Figure 17 shows the HVC in the proposed scheme.
When using the proposed control scheme in a system when EVs are connected to power for charging, it will be possible for the power factor to be improved close to unity. Bad effects of unbalanced loads in the system are resolved, and the total efficiency of the system is increased. Figure 18 shows the power factor of the system with the proposed schemes.
Table 2 shows intervals of the power factor in the system when EVs are connected to the grid with different conditions of the SVC and controllers.
As can be seen in Table 2, when using the proposed controller, the average power factor is increased by 16%, and the interval of the upper and lower power factor is reduced by 2%.

7. Total Harmonic Distortion and Simulation

Harmonics are voltage and current caused by some sort of electrical load. When a nonlinear load such as a rectifier is connected to a power system, it causes a stream that is not exactly sinusoidal. Depending on the load, the current waveform can counter the effects of other components of the system, which is quite complex. Regardless of the complexity of the current waveform, Fourier analysis can be used for simple wave analysis for the power system frequencies that occur at integer multiples of the fundamental frequency. Other examples of nonlinear loads are office equipment such as computers and printers, as well as adjustable speed drives.
For a steady-state waveform with equal positive and negative half-cycles, the Fourier series can be expressed as follows:
f ( t ) = n = 1 A n sin ( n Π t / T )
where
  • f(t): The time domain function.
  • n: The harmonic number (only odd values of n are required).
  • An: The amplitude of the nth harmonic component.
  • T: The length of one cycle in seconds.
A common term that is used in relation to harmonics is the THD. It can be used to describe a voltage or current distortion and is calculated as follows:
T H D ( % ) = ( I D 1 ) 2 + ( I D 2 ) 2 + .... + ( I D n ) n
where IDn is the magnitude of the nth harmonic as a percentage of the fundamental (individual distortion).
The control objective of the SVC is to maintain the desired voltage in a high-voltage bus. In steady state, the SVC provides steady-state control of the voltage to give it the highest condition at a pre-defined level. When the load is changed in the power system, the power factor is decreased. For improvement of the power factor, the SVC injects reactive power into the system (within its control limits). When 1.5 times the load is connected between the A-phase, like when EVs are plugged into the system, it causes an unbalanced load.
As shown in Figure 8, the average power factor of the system is 0.83, and the upper and lower distortion in the power factor curve is 0.14. For improvement of the power factor, an SVC is suggested for this system.
As shown in Figure 14, the proper power factor is not achieved with this method and the problem of distortion has not been solved. For obtaining the best power factor, it should be a direct line of power factor without distortion. When EVs are connected to the grid for charging, they affect the source current of the system. Figure 14 shows the source current with the SVC and SRFC without using the HVC.
As shown in Figure 19, the current source of the grid is not symmetrical and sinusoidal. Figure 20 shows the THD of the current source, which is not stable, and it is not going to a constant value.
To solve this problem, another controller is needed for the best result. For this reason, an HVC is suggested. The power factor of the system becomes constant without distortion. Figure 21 illustrates the source current when using the HVC.
After putting the HVC in the controller system, the source current became symmetrical and sinusoidal. Battery chargers are one of examples of nonlinear loads. Nonlinear loads are causing to make nonlinear currents. As nonlinear currents flow through a facility's electrical system and the distribution-transmission lines, additional voltage distortions are produced due to the impedance associated with the electrical network. Normally, current distortions produce voltage distortions. However, when there is a stiff sinusoidal voltage source (when there is a low impedance path from the power source, which has sufficient capacity so that loads placed upon it will not affect the voltage and no harmonic for voltage source), one need not be concerned about current distortions producing voltage distortions.
Figure 22 shows the THD of the system. The THD of the current system is reduced to almost 0.7. Table 3 shows the intervals of the power factor in the system when EVs are connected to the grid with different conditions of the SVC and ASRFC.

8. Conclusions

This paper proposed an ASRFC scheme and HVC for an unbalanced load (EVs charger) with a SVC connected to the grid. The proposed ASRFC (without HVC) can perfectly improve the power factor of the system, but using this controller for improving power factor of source, harmonics are created in the source current.
To solve this problem and achieve IEEE standard for THD, a HVC was suggested for the system. When connecting an EV charger to the grid, the power factor of the system is reduced and unstable. Applying the ASRFC and HVC improves the power factor and stability. The HVC and ASRFC caused the power factor of the system to increase from 83% to 99% and THD of the system was reduced to 1%.

Acknowledgments

This work was supported by the 2014 Yeungnam University Research Grant.

Author Contributions

Saeid Gholami Farkoush, Chang-Hwan Kim and Sang-Bong Rhee contributed to the literature review, the power factor correction study, control models study and manuscript preparation.

Conflicts of Interest

The authors declare no conflict of interest.

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Figure 1. Configuration of SVC.
Figure 1. Configuration of SVC.
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Figure 2. SVC steady-state control characteristics.
Figure 2. SVC steady-state control characteristics.
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Figure 3. EV connected to single-phase voltage.
Figure 3. EV connected to single-phase voltage.
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Figure 4. EVs connected to two single-phase voltages.
Figure 4. EVs connected to two single-phase voltages.
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Figure 5. EVs are connected to three single-phase voltages.
Figure 5. EVs are connected to three single-phase voltages.
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Figure 6. IEEE 14-node test feeder.
Figure 6. IEEE 14-node test feeder.
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Figure 7. Single-line diagram of SVC and control system.
Figure 7. Single-line diagram of SVC and control system.
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Figure 8. Power factor of system when EVs are plugged into the grid without SVC.
Figure 8. Power factor of system when EVs are plugged into the grid without SVC.
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Figure 9. Power factor of the system when EVs are plugged into the grid with SVC.
Figure 9. Power factor of the system when EVs are plugged into the grid with SVC.
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Figure 10. Proposed voltage controller.
Figure 10. Proposed voltage controller.
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Figure 11. Block diagram of NVC.
Figure 11. Block diagram of NVC.
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Figure 12. Block diagram of NSC.
Figure 12. Block diagram of NSC.
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Figure 13. Proposed control scheme for unbalanced load compensation for SVC connected to the grid.
Figure 13. Proposed control scheme for unbalanced load compensation for SVC connected to the grid.
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Figure 14. Power factor of grid with ASRFC.
Figure 14. Power factor of grid with ASRFC.
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Figure 15. SVC circuit for harmonic current analysis.
Figure 15. SVC circuit for harmonic current analysis.
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Figure 16. Block diagram of HVC.
Figure 16. Block diagram of HVC.
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Figure 17. Proposed control schemes for unbalance load (EVs charger).
Figure 17. Proposed control schemes for unbalance load (EVs charger).
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Figure 18. Power factor with ASRFC and HVC.
Figure 18. Power factor with ASRFC and HVC.
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Figure 19. Source current without HVC.
Figure 19. Source current without HVC.
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Figure 20. THD of source current without HVC.
Figure 20. THD of source current without HVC.
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Figure 21. The source current with HVC.
Figure 21. The source current with HVC.
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Figure 22. THD of source current with HVC.
Figure 22. THD of source current with HVC.
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Table 1. Variable names and their definitions.
Table 1. Variable names and their definitions.
Variable NamesMeaning
KPIProportional and integral gain constant
ϴωt
INdcmd, INqcmdStationary frame current command
Table 2. Intervals of power factor in the system when EVs are connected to the grid.
Table 2. Intervals of power factor in the system when EVs are connected to the grid.
Without SVCWith SVCSVC with ASRFC & HVC
Average of power factor (%)8391.599
Interval of upper and lower of power factor (%)1492
Table 3. Intervals of power factor in the system when EVs are connected to the grid.
Table 3. Intervals of power factor in the system when EVs are connected to the grid.
Without SVCWith SVCSVC with ASRFC & HVC
Average of power factor (%)8391.599
(No distortion)

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MDPI and ACS Style

Farkoush, S.G.; Kim, C.-H.; Rhee, S.-B. THD Reduction of Distribution System Based on ASRFC and HVC Method for SVC under EV Charger Condition for Power Factor Improvement. Symmetry 2016, 8, 156. https://doi.org/10.3390/sym8120156

AMA Style

Farkoush SG, Kim C-H, Rhee S-B. THD Reduction of Distribution System Based on ASRFC and HVC Method for SVC under EV Charger Condition for Power Factor Improvement. Symmetry. 2016; 8(12):156. https://doi.org/10.3390/sym8120156

Chicago/Turabian Style

Farkoush, Saeid Gholami, Chang-Hwan Kim, and Sang-Bong Rhee. 2016. "THD Reduction of Distribution System Based on ASRFC and HVC Method for SVC under EV Charger Condition for Power Factor Improvement" Symmetry 8, no. 12: 156. https://doi.org/10.3390/sym8120156

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