The DC-link voltage controller is usually based on a PI controller along with an antiwindup mechanism. However, this scheme may not be sufficient in the case of weak grids. Due to the compensation of the negative sequence voltage at the PCC, an oscillation of frequency 2ω₁ appears in u_DC. If u_DC is not filtered, this oscillation propagates through the control system, appearing in P* and, therefore, in the reference currents. The oscillation of frequency 2ω₁ in dq-axes is transformed into an oscillation of frequency 3ω₁ in the abc-axes.

In short, if u_DC is not filtered, the PCC currents will be affected by the appearance of a 3rd order harmonic (this being no zero-sequence harmonic). To eliminate this harmonic, the 2nd order oscillation is removed from the measured u_DC by means of a band-pass filter centered at ω₀ = 2ω₁. This filter is implemented with a Second Order Generalized Integrator for Quadrature Signal Generation (SOGI-QSG) [11], using the output in phase with the input since its transfer function behaves as a band-pass filter centered at ω₀. This way, the dynamics of the mean value of the DC-link voltage is not altered.

The block diagram of the DC-link voltage controller is shown in Figure 6, where k_px is the proportional gain, k_ix is the integral gain and k_awx is the antiwindup gain. The DC-link model based on the energy stored in the capacitor has been used [12]. As mentioned before, the basis of the DC-link voltage control is a PI controller and its parameters are tuned without taking into account the inner current controller. To do so, the Zero-Order Hold (ZOH) method has been applied to the plant to obtain its discrete time version, where C_DC = (C_DC1·C_DC2)/(C_DC1+C_DC2): (5) G D C ( z ) = 2 T s C D C ( z − 1 )

The PI controller can be expressed in pole-zero form as: (6) C ( z ) = k p x z − α z − 1where α = 1 − (k_ixT_s/k_px). The open-loop transfer function has two poles placed at z_p = 1 and a zero placed at z_z = α. Depending of the controller gain, the closed loop system G_CL(z) can have two conjugate poles as shown. In this case, the general form of the denominator polynomial of G_CL(z) is: (7) den { G C L ( z ) } = ( z − ρ e j ϑ ) ( z − ρ e − j ϑ ) = z 2 − ( 2 ρ cos ϑ ) z + ρ 2where ρ = e − ξ ω n T s, ϑ = ω n T s 1 − ξ 2, ω_n is the natural pulsation and ξ is the damping coefficient. To avoid a large overvoltage in u_DC, the damping coefficient has to be chosen as ξ ≥ 1 / 2. From settling time and damping coefficient values, ω_n can be calculated with the expression t_s ≈ 4.6/ξω_n for a second order system. To verify these conditions, k_px and α have to take the next values: (8) k p x = ( 1 − ρ cos ϑ ) C D C T S (9) α = 1 − ρ 2 2 ( 1 − ρ cos ϑ )and then k_ix = (1 − α)k_px/T_S. The antiwindup gain is chosen as k_awx = 1/k_px.

This is a controller associated to variables that modify the reactive power at the PCC. In this case, this block specifies the reactive power reference Q*, which is an output to the block “Calculation of i d q + ∗ & i d q − ∗”. Another variable that could be used to modify the reactive power at the PCC is the power factor.

This controller is regulated by the equation system in Equation (10). It relates active power, reactive power, PCC voltage and current in dq-axes and it is usually employed in active and reactive power control, as well as in power factor control. Active and reactive powers are divided into three parts: average power (P and Q), oscillating power with cosine terms [P_2ω(c) and Q_2ω(c)] and oscillating power with sine terms [P_2ω(s) and Q_2ω(s)]. If grid conditions are balanced, these four oscillating powers are zero and there are only positive sequence voltages and currents. Multiplying by the inverse matrix, the corresponding expressions for the calculation of the reference currents are obtained ( i d q + ∗ and i d q − ∗). To do so, P_2ω(c) and P_2ω(s) are set to zero to compensate the unbalance caused by negative sequence voltage and Q_2ω(c) and Q_2ω(s) are not controlled, therefore their corresponding rows are eliminated from Equation (10). Trying to control these oscillating reactive powers only deteriorates the control performance, therefore they are allowed to run freely: (10) [ P 0 P 2 ω ( c ) P 2 ω ( s ) Q 0 Q 2 ω ( c ) Q 2 ω ( s ) ] = [ u d + u q + u d − u q − u d − u q − u d + u q + u q − − u d − − u q + u d + u q + − u d + u q − − u d − u q − − u d − u q + − u d + − u d − − u q − u d + u q + ] ⋅ [ i d + i q + i d − i q − ]

The block diagram of the PCC voltage controller is shown in Figure 7 and it is implemented in dq-axes. This stage is formed by three “individual voltage controllers” in parallel, whose outputs are i d + ∗, i d − ∗, and i q − ∗, plus the calculation of i d + ∗ by means of Equation (11). This equation is obtained from Equation (10). The minus sign that goes with u q + is due to the current direction. These four outputs are the references for the current controller. In this figure, ε represents the error signal and the subscript “lim” stands for “limited”. The reference voltages u d − ∗ and u q − ∗ are set to zero in order to eliminate the PCC voltage negative sequence, whereas the reference voltage u q + ∗ should be equal to the PCC fundamental voltage.

The inner structure of each “individual voltage controller” is depicted in Figure 8. As mentioned, it is mainly formed by a PI controller with a forward Euler integrator. The constant δ is 1 for the voltage controllers of u q + and u d −, and -1 for the voltage controller of u q − due to the minus sign in Equation (4b). It is a first order system and, considering the cascaded system of Figure 5, the tuning goal is to achieve a settling time larger than ten times the settling time of the current controller (t_s|_vc > 10 · t_s|_cc, where t_s is the settling time, “vc” means voltage control and “cc” means current control). This constraint affects the position of the closed-loop pole introduced by the PI controller. The integral constant (k_i) helps achieve zero steady-state error in the event of model mismatch and disturbances. Therefore, the parameter tuning is focused on settling time and controller bandwidth. The resulting parameters are k_p = 0.05 and k_i = 350. (11) i q + ∗ = P ∗ u q + ( u d − ) 2 + ( u q − ) 2 − ( u d + ) 2

In order to prevent the windup of the integrator, an antiwindup mechanism has been added to each PI controller. It is characterized by the antiwindup constant, which has been set as k_aw = 0.1. High values for this parameter cause system instability. When using an antiwindup technique, an important detail to be taken into account is that its contribution should not be added to the integral branch of the PI controller until the whole control system starts. Otherwise, the control system would be forced to start with a non-zero error.

The linear operating range of a STATCOM with given maximum capacitive and inductive ratings can be extended if a regulation “droop” is allowed. Regulation “droop” means that the terminal voltage is allowed to be smaller than the nominal no-load value at full capacitive compensation and, conversely, it is allowed to be higher than the nominal value at full inductive compensation [13]. It also ensures automatic load sharing with other voltage compensators. Perfect regulation (zero droop or slope) could result in poorly defined operating point, and a tendency of oscillation, if the system impedance exhibited a “flat” region (low impedance) in the operating frequency range of interest [13]. It should be mentioned that this possible regulation makes sense in scenarios where there are several converters connected in parallel trying to control the PCC voltage. This droop control has been added to the voltage controller as shown in Figure 8, characterized by the constant droop = 0.01. Similarly to k_aw, high values for this parameter cause system instability. The expression in Equation (11) is obtained from Equation (10).

The outputs of the first stage of the control scheme are i d q + ∗ and i d q − *. These current references have to be transformed to αβ-axes, since the current controller is implemented in stationary reference frame. The reason for this is that a resonant controller tuned at ω in αβ-axes is able to compensate both positive and negative sequences, whereas in dq-axes two controllers would be necessary, a PI controller and a resonant controller tuned at 2ω₁. The fact of increasing the number of controllers connected in parallel endangers the system stability and increases the settling time of the controller.

Positive and negative sequence current references in αβ-axes are calculated as shown in Equation (12a) and (12b). The estimated phase angle θ̂) of the positive sequence voltage vector is obtained with a PLL, whose bandwidth is 20 Hz. This results in a good tradeoff between selectivity, steady-state error and response speed. Afterwards, the final current references are calculated according to Equation (13a) and (13b): (12a) [ i α + ∗ i β + ∗ ] = [ cos θ ^ − sin θ ^ sin θ ^ cos θ ^ ] ⋅ [ i d + ∗ i q + ∗ ] (12b) [ i α − ∗ i β − ∗ ] = [ cos θ ^ sin θ ^ − sin θ ^ cos θ ^ ] ⋅ [ i d − ∗ i q − ∗ ] (13a) i α ∗ = i α + ∗ + i α − ∗ (13b) i β ∗ = i β + ∗ + i β − ∗

The third stage of the control scheme is the current controller. The harmonics present in power systems are those of order 6k ± 1 (k ∈ ℤ), which turn into 6k (k ∈ ℤ) when changing the reference frame from stationary (abc or αβ) to synchronous (dq). This allows halving the number of resonant controllers needed to implement the current controller [14]. Therefore, since the 5th (negative sequence) and 7th (positive sequence) harmonics are usually present in the grid, the current control scheme of Figure 9 has been used to obtain the simulation results. It consists of two resonant controllers (SOGIs) tuned at ω₁ and 6ω₁ (the blocks labeled as “ω₁” and “6ω₁” are composed of an integral gain k_i connected in series with a SOGI), a feedforward of the positive sequence PCC voltage, and αβ to dq and dq to αβ transformations. A feedforward of the total PCC voltage (including negative sequence) would introduce non-desired harmonics in the control. The error signals in αβ-axes and dq-axes are ε_αβ and ε_dq, respectively.

In general, the resonant frequency of the SOGI is represented by ω₀. The discrete SOGI transfer function is given by Equation (14) and, if ω 0 2 T s 2 ≪ 2, which is verified for T_s < 1.4 ms (supposing that ω 0 2 T s 2 = 0.2 is small enough, i.e., a factor of 10) and if ω₀ = 2π50 rad/s, Equation (14) can be approximated by Equation (15): (14) G SOGI ( z ) = ω 0 T s z ( z − 1 ) ( z − 1 ) 2 + ω 0 2 T s 2 z (15) G SOGI ( z ) ≈ ω 0 T s z z − 1

The SOGI is combined with a proportional and integral gain (k_p and k_i, respectively) to form the current controller. The resulting transfer function can be expressed as: (16) G P + SOGI ( z ) = k p + k i ω 0 T s z z − 1 = K p z − α z − 1where K_p = k_p + k_iω₀T_s and α = k p k p + k i ω 0 T s. It is important to notice that the approximation made for Equation (15), i.e., if ω 0 2 T s 2 ≪ 2, will not be valid for every frequency and for every sampling period. The current controller parameters take the following values: (17a) K p = 1 + a − 2 ρ cos ϑ b (17b) α = a − ρ 2 b K pwhere ρ = e − ξ ω n T s, ϑ = ω_nT_s, ω_n is the natural pulsation, ξ is the damping factor, a = e − R T s L and b = (1 − a)/R. Then, k_p = αK_p and k_i = (k_p − k_p)/ω₀T_s.

To help decreasing the computational burden, the trigonometric functions employed in the calculation of these transformations can be implemented by means of look-up tables if the digital platform has enough memory.

The NPC converter, whose scheme is shown in Figure 10, has some drawbacks such as the additional clamping diodes, a more complicated PWM switching pattern design and possible deviation of neutral point (NP) voltage [15]. The capacitors can be charged or discharged by neutral current i_NP, causing NP voltage deviation. It might appear a ripple of frequency three times the fundamental in u_DC1 and u_DC2 that can destroy components if both DC-link voltages are not balanced.

To minimize this effect, a carrier-based PWM strategy with zero-sequence voltage injection [16] is applied to the three-level NPC converter. Using this technique, the locally averaged NP current is kept to zero, and consequently, the locally averaged voltages on the DC-link capacitors are constant [17].

A simulation has been carried out with MATLAB/Simulink^® in order to test the performance of the proposed voltage controller. The ideal grid voltage of Figure 2 has been considered, along with the system parameters of Table 1. The NPC rated power is 100 kVA and the DC-link capacitors have a value of C_DC1 = C_DC2 = 4.5 mF. No load is connected to the PCC. The proposed voltage controller is enabled at t = 0.5 s.

Figure 14 shows the temporary evolution of the filtered PCC voltage in abc-axes. Its non-filtered waveform presents a high ripple due to the high grid impedance and, in order to appreciate the effect of the PCC voltage controller, its filtered waveform is the one represented. In the following figures, the corresponding control activation time is marked with a dashed black line. It is clear that, when the voltage control is enabled, the PCC voltage is balanced. This is corroborated by decomposing this voltage in their positive and negative sequences as shown in Figure 15. The positive sequence u d q + remains equal because its reference voltage corresponds to the value it had before enabling the PCC voltage control. The negative sequence u d q − becomes almost zero since its reference voltage is set to zero for both d and q components, as well as the VUF.

The current flowing from the VSC to the grid is represented in Figure 16a in abc-axes. Since no load is connected to the PCC, the current before enabling the voltage control is zero. Afterwards, the VSC provides an unbalanced current in order to compensate the negative sequence component. This is better observed in Figure 16b, which is a representation of Figure 16a between t = [0.45 0.65] s. Figure 16c is the equivalent of Figure 16b if the resonant controller 2ω is not included in the DC-link voltage controller, showing a PCC current with a 3rd order harmonic.

Since the PCC voltage is no longer unbalanced due to the effect of the voltage controller, the unbalance now appears in u_DC. Figure 17a shows that a large oscillation appears in u_DC, reaching nearly ±150 V. Besides, the DC-link voltage unbalance, calculated as the difference between positive and negative DC-link voltages (u_DC1 − u_DC2), also increases. If the oscillation level is not permissible, the reference for the negative sequence voltage can be set with a value different from zero but still low enough to satisfy regulations when it comes to maximum PCC voltage unbalance. In any case, it is worth remembering that the high level of unbalance applied to carry out these tests is usually not found in a real power system, so that in practice the amplitude of the oscillation will be much smaller. According to current regulations, a VUF greater than 2% in the worst case (e.g., IEC 61000-3-13 regulation) and 3% in the best case (e.g., ENTSO-E regulation) requires the disconnection of the converter from the grid, which can be avoided with the proposed PCC voltage controller.

In order to test the performance of the proposed PCC voltage controller in a more realistic situation, 5th and 7th order harmonics have been included in the grid voltage with a level of A₅ = 0.01 · A₁ and A₇ = 0.03 · A₁, respectively. Furthermore, a higher level of negative sequence has been chosen (VUF = 10%). Figure 18 shows the temporal evolution of the PCC voltage waveform, validating as well the proper operation of the PCC voltage controller by compensating its negative sequence. The performance of the proposed controller is also observed in Figure 19, which collects the evolution of u d q + (Figure 19a), u d q − (Figure 19b) and the VUF (Figure 19c).