A Single-Phase Buck and Boost AC-to-AC Converter with Bipolar Voltage Gain: Analysis, Design, and Implementation

Abstract

In this research, a new single-phase direct AC-to-AC converter, operating in buck and boost mode, with a bipolar voltage gain, is proposed. The operation is accomplished through high frequency direct and indirect PWM control of a single switch with low voltage stresses. This reduces, not only the control effort, but also the switching losses. The low voltage stresses across the high frequency switches, reduce the dv/dt problem significantly without any loss and bulky voltage snubber arrangement. The operation, in its all-operating modes, has a low inductor ripple current and switching current. The proposed converter may be employed as an AC voltage restorer in a power distribution system to cope with the voltage sag and swell issues. The detailed analysis of the proposed converter is carried out in order to compare its performance with the existing converters. The simulation results obtained using the MATLAB/Simulink environment are verified through experimental results.

1. Introduction

Traditionally, in variable AC power system, load voltage and frequency regulation are accomplished with indirect AC-to-AC power converters as reported in [1,2,3]. They are dual converters, having bulky DC linked capacitor to suppress the ripples in the output voltage of the first conversion stage. This arrangement generates harmonics in the input current, thus causing poor power quality. A filtering inductor filter is employed at the input side to mitigate the generated harmonics. Extra circuit elements (two inductors and capacitors) are employed in z-source arrangement [4] to solve the short problem of the second conversion stage. Indirect AC power converters are complex and have high conversion losses, thus causing poor efficiency. Their reliability is also low, due to an intermediate DC link capacitor [5].

In direct AC-to-AC power converters [6,7,8], the variable output voltage and the frequency are obtained through a single stage power conversion. These can be implemented as AC voltage controllers and direct frequency changers (DFC). They offer many advantages, such as simple circuit implementation, easier control, small size, and low price. AC voltage controllers are used to control the dynamic voltage variation in AC power systems. Voltage sags and swells are major disturbances of the power system [9], which degrade the system’s performance severely. The end users have to use power-conditioning units and controllers, as reported in [10], to cope with such problems for the safe and proper operation of their equipment. Dynamic voltage restorer (DVR), presented in [11,12], can also be used to solve this problem. They are voltage source inverters (VSI), and can mitigate the voltage sag problem, by injecting ac power through a series connected transformer. They only maintain the amplitude of the input voltage, thereby ignoring the problem of harmonic distortion and phase delay. Therefore, this approach is inefficient and has low reliability.

Single phase direct AC voltage controllers, as proposed in [13], are implemented with PWM control by using a DC-DC complement approach, where a bi-directional current conduction capability is achieved by using bi-directional controlled switches, instead of uni-directional switches. The converters realized with this approach in [14,15], only perform buck, and boost operations, respectively. They have a current commutation problem, due to the overlapping intervals caused by the complementary switches. The filtering capacitors or voltage sources get short-circuited during these intervals, causing a generation of voltage and current surges. This problem increases the power rating of the controlled switches and may cause their failure. The problems caused by the overlapping times are mitigated by inserting the dead-time in the gating sequences of the complementary switches. But this approach limits their switching speed, voltage gain, and hence degrades their power quality. It also makes the switching arrangement complex. The current commutation problems are also solved in [16], by using a coupled inductor approach. This approach only improves the current continuity without improving the voltage gain. This results in an increased power rating of the controlled and uncontrolled devices. The z-source and quasi-z-source converters in [17,18] solve these problems caused by the current commutation. Z-source AC voltage controllers with buck-boost characteristics, as reported in [19,20], mitigate the voltage sag problem up to 25% in depth. AC voltage controllers to mitigate the voltage sag up to 50% depth are developed by using inter-phase power conversion approach [21], where the power in faulty phase is injected from other two healthy phases with the help of series connected transformers. All z-source converters require extra circuit elements to solve the problem of current commutation.

The non-z-source AC voltage controllers, in [22,23,24,25,26], eliminate the extra circuit elements but their inverting buck-boost operation requires high voltage switching stresses, high inductor ripple current and high switching currents. This results in high switching, conduction, and filtering of the inductor’s DCR resistance losses. High voltage switching stresses also result in high dv/dt problem; so, it increases the voltage rating of the switching devices. Such devices have high internal resistances or forward voltage that also increase the conduction losses. Also, the operation in buck-boost mode has a high voltage and current ripples, thus causing high filtering losses. So, the overall conversion efficiency in these converters is low, due to high conduction and switching losses.

In this research, a novel AC voltage converter is proposed that has 50% low switching stresses across the high frequency switching devices, in the inverting buck and boost mode, with a duty ratio of 0.5. This results in 50% low switching losses. The other highlights of this research are no short through problem, caused by the complementary switching devices, low switching, and inductor ripple current. The control effort is reduced by controlling one switch as a direct PWM (DPWM) and the other one as an indirect PWM (IDPWM) control. A detailed analysis is carried out to compare the performance of the proposed topology with existing converters. A hardware setup is developed to validate the simulation results obtained by modelling of proposed converter in the MATLAB/Simulink environment.

2. The Proposed AC-to-AC Voltage Converter Circuit Configuration

The proposed converter’s circuit consists of one filtering inductor, two capacitors, and eight MOSFET-diode series connected pairs (see Figure 1). All its operating modes are accomplished through one high frequency DPWM control, one IDPWM control, and two low frequency switches. The remaining four switches are off throughout the operation of the converter. The DPWM switch controls the switching state of IDPWM switch. No voltage develops across the series connected diodes of DPWM control switch, due to the negative voltage at its cathode. So, the reverse voltage is developed across the MOSFET. In IDPWM control switch, as MOSFET remains in a conduction state to avoid the current interruption problem of the inductor, so its series connected diode has to withstand the reverse voltage. The proposed topology comes with the advantage that both the buck and the boost operating modes with non-inverting and inverting characteristics can be realized with the help of just changing the switching states mechanism. The series connection of diode, with MOSFET, eliminates the possible short through of input voltage, output voltage, and paralleling of input and output voltages. For example, the antiparallel arrangement of diodes D_S2, D_S3 and D_S5, D_S6, avoids the short circuiting of the input, and output voltage, respectively. In the same way, D_S1 and D_S4 avoid the paralleling of input and output voltages.

2.1. Non-Inverting and Inverting Buck Operation

The non-inverting and inverting buck operation of the suggested topology is explored in modes ‘A’ to ‘D’ depending upon sequence of switching signals. The voltage gain is positive and negative in non-inverting and inverting operation respectively as demonstrated in PWM scheme shown in Figure 2. It also depicts their switching sequences for its various operating modes. For example, in non-inverting buck mode (see Figure 2a), the switching signals g₁, g₄, g₅, g₆, g₇, g₈ and g₂, g₃ are the low, and high frequency signals, respectively. Its inverting mode may be realized only by changing the connection of the gating signals to switching devices, as depicted in Figure 2b. The detail of its various operating modes is given below through the power transfer path.

2.1.1. Operating Mode A

In mode ‘A’, the output is non-inverted for a positive input voltage. Figure 2a illustrates the switching signals to achieve the required target. During this operating mode, the switch M₂ is controlled in a high frequency PWM manner; the switching devices M₃, M₅, M₄, D_S2, D_S4, and D_S5 are in on-state, while M₁, M₆, M₇, M₈, D_S1, D_S6, D_S7, and D_S8 are in off-state. The controlled switch M₃ cannot conduct, due to reverse biasing of its series connected diode D_S3. During the turn-on interval of the switch M₂, the input power is delivered to load via the current conduction path, formed by the switching devices M₂, D_S2, filtering inductor L, M₅, D_S5, M₄ and D_S4, as highlighted in Figure 3a. In this period, the switching voltages across the DPWM and IDPWM switches are ‘0’, and ‘V_i’, respectively. Once the switch M₂ turns off, the input power is removed from the load and the series-connected diode D_S3 becomes forward biased. The energy stored in the inductor is now supplied to load through the current conduction path of the switching devices M₃, M₅, M₄, D_S3, D_S5, D_S4, as exposed is Figure 3b. In this period, the switching voltage of the DPWM, and IDPWM switches are changed from ‘0’, ‘V_i’ to ‘−V_i’, ‘0’, respectively. The dynamic state equations of inductor voltage and capacitor current are framed in Equations (1) and (2) during turn-on and -off periods of the PWM control by, applying the KVL and KCL in Figure 3a,b as established in [23]. The duty ratio during switching on and off intervals are represented as d, and $d^{\prime }$, respectively.

$$\{\begin{array}{l}L\frac{d{i}_L}{dt}=d(v_i-v_o)\\ C\frac{d{v}_o}{dt}=d(i_L-i_o)\end{array}$$

(1)

$$\{\begin{array}{l}L\frac{d{i}_L}{dt}=-d^{\prime }{v}_o\\ C\frac{d{v}_o}{dt}=d^{\prime }(i_L-i_o)\end{array}$$

(2)

The PWM dynamic average behavior of these state equations is obtained in Equation (3) by adding the right side of Equations (1) and (2).

$$\{\begin{array}{l}L\frac{d{i}_L}{dt}=d(v_i-v_o)-d^{\prime }{v}_o\\ C\frac{d{v}_o}{dt}=d(i_L-i_o)+d^{\prime }(i_L-i_o)\end{array}$$

(3)

2.1.2. Operating Mode B

During the negative half cycle of the input voltage, the positive voltage gain is obtained by applying the high frequency PWM control signal to switch M₃. In its on interval, the switching devices M₆, M₁, M₂, D_S6, D_S1 turn on to connect load with the source as shown in the power flow path shown in Figure 3c. The switch M₂ remain off, as its series, connected diode D_S2 is reverse bias by the ‘V_i’ volt. During the turn off period of its PWM control, the diode D_S2 changes it operating state from off to on as the source voltage is isolated from the load and energy stored in the inductor is delivered to load through the current flow path formed by M₁, M₂, M₆, inductor, D_S1, D_S2 and D_S6 as highlighted in Figure 3d. The PWM dynamic averaging of this mode is developed in Equation (4) by repeating the steps of mode ‘A’.

$$\{\begin{array}{l}L\frac{d{i}_L}{dt}=d(v_i-v_o)-d^{\prime }{v}_o\\ C\frac{d{v}_o}{dt}=d(i_L-i_o)+d^{\prime }(i_L-i_o)\end{array}$$

(4)

The voltage and current transfer ratios of mode ‘A’ and ‘B’ are obtained in Equation (5) by ignoring the right side of Equations (3) and (4) as they have low variation at low fundamental frequency.

$$\{\begin{array}{l}\frac{v_o}{v_i}=d\\ i_L=i_o\end{array}$$

(5)

2.1.3. Operating Modes C and D

Similarly, these modes are employed to have a negative voltage gain with any polarity of the input voltage. It is implemented by simply swapping the low frequency control signals g₅ with g₆, and g₄ with g₇, and g₁ with g₈, as can be investigated in its PWM modulation control, as shown in Figure 2b. There is no change in its high frequency PWM signals, g₂ and g₃. The detail of switching and inductor voltage in these operating modes is explored with the help of power flow paths in Figure 3e–h, for positive, and negative, input voltage, respectively. Similarly, the PWM dynamic equation, and the voltage and current transfer ratio of these operating modes are expressed in Equations (6) and (7), respectively.

$$\{\begin{array}{l}L\frac{d{i}_L}{dt}=d(v_i+v_o)+d^{\prime }{v}_o\\ C\frac{d{v}_o}{dt}=-d(i_L+i_o)-d^{\prime }(i_L+i_o)\end{array}$$

(6)

$$\{\begin{array}{l}\frac{v_o}{v_i}=-d\\ i_L=-i_o\end{array}$$

(7)

The operation of the proposed converter in mode ‘A’, ‘B’ and ‘C’, ‘D’ may realize as non-inverting, and inverting, AC voltage compensator, respectively.

2.2. Non-Inverting and Inverting Boost Operation

The bipolar voltage gain characteristics of the proposed topology in boost operation is explored in mode ‘E’ to ‘F’, with respect to the polarity of the input voltage. Their PWM switching modulation strategy is shown in Figure 4a,b for non-inverting, and inverting operation, respectively. It is clearly observed from these switching controls that boost operation can be obtained with the switching schemes, developed for the buck operation by changing the connection of the gating signals to the controlled switches. For example, the high frequency PWM signals g₂ and g₃ of non-inverting buck now become g₅, and g₆, of the none-inverting boost, respectively. The same is true for the reaming low frequency gating signals g₁, g₄, g₅, and g₆. The detail of operating modes with switching and inductor voltage, their corresponding dynamic averaging state equations, and voltage and current transfer ratio are realized in Figure 5,

Table 1. Operating modes in proposed circuit in boost mode.

Mode Name	Operating Modes	Switching States
		Low Frequency Switches	OFF Switches	DPWM Control Switch	IDPWM Control Switch
E	Non-Inverting Boost with Positive Input	$M_2$, $M_4$	$M_1$, $M_3$, $M_7$, $M_8$	$M_6$	$M_5$
F	Non-Inverting Boost with Negative Input	$M_1$, $M_3$	$M_2$, $M_4$, $M_7$, $M_8$	$M_5$	$M_6$
G	Inverting Boost with Positive Input	$M_2$, $M_7$	$M_1$, $M_3$, $M_4$, $M_8$	$M_5$	$M_6$
H	Inverting Boost with Negative Input	$M_3$, $M_8$	$M_1$, $M_2$, $M_4$, $M_7$	$M_6$	$M_5$

and

Table 2. PWM switching average modelling and corresponding transfer ratio for boost operation.

Non-Inverting Boost Operation	Inverting Boost Operation
$\begin{array}{l}\{\begin{array}{l}L\frac{d{i}_L}{dt}=d{v}_i+d^{\prime }(v_i-v_o)\\ C\frac{d{v}_o}{dt}=-d{i}_o+d^{\prime }(i_L-i_o)\end{array}\\ \{\begin{array}{l}\frac{v_o}{v_i}=\frac{1}{d^{\prime }}\\ \frac{i_o}{i_L}=d^{\prime }\end{array}\end{array}$	$\begin{array}{l}\{\begin{array}{l}L\frac{d{i}_L}{dt}=d{v}_i+d^{\prime }(v_i+v_o)\\ C\frac{d{v}_o}{dt}=-d{i}_o-d^{\prime }(i_L+i_o)\end{array}\\ \{\begin{array}{l}\frac{v_o}{v_i}=\frac{-1}{d^{\prime }}\\ \frac{i_o}{i_L}=-d^{\prime }\end{array}\end{array}$

respectively.

The AC voltage controller has non-inverting and inverting boost characteristics, which may be realized by operating the suggested converter in modes ‘E’, ‘F’, and ‘G’, ‘H’, respectively. The control of duty cycle regulates their voltage gains. The input current in boost operation is inherently continuous, having low THD than that of buck or buck-boost operation.

The controlling signals of Figure 2 and Figure 4 depict the low control effort as only one switch at any time instant regulates the positive and negative voltage gains with buck and boost characteristics through PWM control. This control also governs the switching states of the IDPWM controlled switches indirectly as their series connected diodes become forward during the turning off periods of the DPWM switches. These switching characteristics simplify the control algorithms. The switching losses of the high frequency devices are lower at any instant of time, as only one switch is operated at low switching voltage and hence it improves the conversion efficiency.

3. Performance Evaluation with Existing Converters

The performance parameters of the proposed converter are computed to compare its performance evaluation with the existing converters in terms of voltage stresses, switching losses, inductor ripple and peak switching current as discussed below.

3.1. Voltage Stresses Across Switching Devices

Bipolar voltage gain in proposed converter is obtained through the high frequency switching action of M₂, M₃ for buck and M₅, M₆ for boost operation. The peak switching voltage across the high frequency-controlled switches operating in non-inverting and inverting buck and boost are given in Equation (8).

$$\{\begin{array}{l}{V}_{M2,M3(peak)}=V_{DS2,DS3(peak)}=\sqrt{2}{V}_i\\ V_{M5,M6(peak)}=V_{DS5,DS6(peak)}=\sqrt{2}{V}_o\end{array}$$

(8)

Similarly, the maximum voltage stresses of the high frequency-controlled switches in inverting buck-boost mode of [22] are computed in Equation (9).

$$V_{M3,M4(peak)}=V_{DS3,DS4(peak)}=\sqrt{2}(V_{in}+V_o)$$

(9)

As can be seen from Equations (8) and (9) that the proposed converter has 50% low switching stresses with voltage gain of 0.5 and 2 for inverting buck and boost mode respectively. So, the proposed converter has low voltage rating, low dv/dt problem and low switching losses.

3.2. Inductor Ripple and Switching Currents

The comparison of inductor ripple and switching currents is carried for the voltage gain of 0.5 and 2 for buck and boost mode respectively.

$$\{\begin{array}{l}\Delta i_{Lpeak,proposed(Buck)}=0.25\left(\frac{\sqrt{2}{V}_{i,peak}}{L}T\right)\\ \Delta i_{Lpeak,proposed(Boost)}=0.5\left(\frac{\sqrt{2}{V}_{i,peak}}{L}T\right)\end{array}$$

(10)

$$\{\begin{array}{l}\Delta i_{Lpeak,[22](Buck)}=0.333\left(\frac{\sqrt{2}{V}_{i,peak}}{L}T\right)\\ \Delta i_{Lpeak,[22](Boost)}=0.667\left(\frac{\sqrt{2}{V}_{i,peak}}{L}T\right)\end{array}$$

(11)

$$\{\begin{array}{l}{I}_{Sw(peak)-proposed(Buck)}=\sqrt{2}\frac{P_0}{V_o}\\ I_{Sw(peak)-proposed(Boost)}=2\sqrt{2}\frac{P_0}{V_o}\end{array}$$

(12)

$$\{\begin{array}{l}{I}_{Sw(peak)-[22](Buck)}=3\frac{P_0}{\sqrt{2}{V}_o}\\ I_{Sw(peak)-[22](Boost)}=3\sqrt{2}\frac{P_0}{V_o}\end{array}$$

(13)

The analysis and comparison from Equations (10) to (13) explores that the proposed converter has low inductor ripple and switching current having low conduction losses and low losses in the DCR resistance of filtering inductor. These losses are proportional to the magnitude of the conducting currents. They also depend on their internal resistances and forward voltage drops. Low switching voltage devices have low on-state resistances and forward voltage drops. The proposed topology has low conduction losses due to low conduction current and switching voltage as can be observed from Equations (10) to (13). The quality of the output voltage depends on the ripple voltage that is improved due to low inductor ripple current. In addition, during the short through intervals, the output is distorted. Therefore, absence of short through problem and low ripples improve the power quality of the output voltage.

3.3. Switching Losses

The switching losses of a MOSFET depend on switching voltage, current, switching frequency, output capacitance, rise and fall time as reported in [23]. These losses in fast recovery diode depend on its reverse recovery characteristics as in [23]. They are also proportional to number of high-frequency switching devices and voltage gain. The switching losses of DPWM control switch only come from the switching of MOSFET as its series connected diode is forward biased due to negative reverse voltage. The switching losses of IDPWM controlled switch are only due to reverse biasing of diode as MOSFET is kept turned on to ensure the continuous conduction of inductor current.

The buck operation of the proposed circuit is implemented with high frequency PWM control of M₂(M₃) and D_S2(D_S3). The total switching losses of the proposed converter and the converter in [22] in inverting mode are computed by assuming same switching current and constant input voltage in Equations (14) and (15) respectively.

$$\{\begin{array}{l}{P}_{sw-buck(proposed)}=f_{sw}\left[\frac{1}{4}\left\{I_L{V}_i(t_{on}+t_{off})+C_{os}{V}_i^2\right\}+\frac{2Q_{RR}}{\pi }{V}_i\right]\\ P_{sw-boost(proposed)}=f_{sw}\left[\frac{1}{4}\left\{I_L{G}_V{V}_i(t_{on}+t_{off})+C_{os}{(G_V{V}_i)}^2\right\}+\frac{2Q_{RR}}{\pi }{G}_V{V}_i\right]\end{array}$$

(14)

$$P_{sw-buck-boost[21]}=f_{sw}\left[\frac{1}{4}\left\{I_L{V}_i(1+G_V)(t_{on}+t_{off})+C_{os}{V}_i^2{(1+G_V)}^2\right\}+\frac{2Q_{RR}}{\pi }{V}_i(1+G_V)\right]$$

(15)

where f_sw is switching frequency, I_L is the switching current, C_os is output capacitance of MOSFET, Q_RR is the reverse recovery charge of series connected fast recovery diode, V_i is the input voltages, and G_V is the voltage gain. The proposed converter has 50% low switching losses than that of converter in [22] during buck and boost operation with voltage gain of 0.5 and 2 respectively.

3.4. Conduction Losses

The conduction losses of a MOSFET-diode pair depend on their forward voltages and resistances. They also depend on their conduction currents. The conduction losses of the proposed topology and converter in [22] are realized in Equations (16) and (17) for voltage gain of ‘2’ respectively, where R_T and R_d are on-state resistances of MOSFET and diode respectively whereas V_d is the forward voltage of the diode.

$$P_{Cod(proposed)}=\frac{12V_d{I}_o}{\pi }+6I_o^2\left(R_T+R_d\right)$$

(16)

$$P_{Cod([22])}=\frac{18V_d{I}_o}{\pi }+13I_o^2\left(R_T+R_d\right)$$

(17)

The above comparison depicts that the proposed topology has low conduction losses.

In a summary, the comparison of the proposed topology with the existing converter in [22] is detailed in

Table 3. Comparison of performance parameters in buck mode.

Inverting Buck Operation with Voltage Gain of 0.5
Description	Proposed Converter	Converter in [22]	Comparision
Voltage stresses across high frequency switches	$\begin{array}{l}{V}_{M2,M3(peak)}=\sqrt{2}{V}_i\\ V_{DS2,DS3(peak)}=\sqrt{2}{V}_i\end{array}$	$\begin{array}{l}{V}_{M3,M4(peak)}=\frac{3\sqrt{2}{V}_i}{2}\\ V_{DS3,DS4(peak)}=\frac{3\sqrt{2}{V}_i}{2}\end{array}$	$\begin{array}{l}\frac{V_{M3,M4(peak)}}{V_{M2,M3(peak)}}=\frac{3}{2}\\ \frac{V_{DS3,DS4(peak)}}{V_{DS2,DS3(peak)}}=\frac{3}{2}\end{array}$
Peak inductor ripple current	$\Delta i_{Lpeak}=0.25\left(\frac{\sqrt{2}{V}_{i,peak}}{L}T\right)$	$\Delta i_{Lpeak}=0.334\left(\frac{\sqrt{2}{V}_{i,peak}}{L}T\right)$	$\frac{\Delta i_{Lpeak[22]}}{\Delta i_{Lpeak[\mathrm{Pr}oposed]}}=\frac{0.334}{0.25}$
Peak switching device current	$I_{Sw(peak)}=\sqrt{2}\frac{P_0}{V_o}$	$I_{Sw(peak)}=2\sqrt{2}\frac{P_0}{V_o}$	$\frac{I_{Sw(peak)[22]}}{I_{Sw(peak)[\mathrm{Pr}oposed]}}=\frac{3}{2}$
Switching power losses	$P_{sw}=f_{sw}\left[\begin{array}{l}\frac{1}{4}\left\{I_L{V}_i(t_{on}+t_{off})\right\}\\ +\frac{2Q_{RR}}{\pi }{V}_i\end{array}\right]$	$P_{sw}=\frac{3}{2}{f}_{sw}\left[\begin{array}{l}\frac{1}{4}\left\{I_L{V}_i(t_{on}+t_{off})\right\}\\ +\frac{2Q_{RR}}{\pi }{V}_i\end{array}\right]$	$\frac{P_{sw[22]}}{P_{sw[\mathrm{Pr}oposed]}}=\frac{3}{2}$

and

Table 4. Comparison of performance parameters in boost mode.

Inverting Boost Operation with Voltage Gain of 2
Description	Proposed Converter	Converter in [22]	Comparision
Voltage stresses across high frequency switches	$\begin{array}{l}{V}_{M5,M6(peak)}=2\sqrt{2}{V}_i\\ V_{DS5,DS6(peak)}=2\sqrt{2}{V}_i\end{array}$	$\begin{array}{l}{V}_{M3,M4(peak)}=3\sqrt{2}{V}_i\\ V_{DS3,DS4(peak)}=3\sqrt{2}{V}_i\end{array}$	$\begin{array}{l}\frac{V_{M3,M4(peak)}}{V_{M2,M3(peak)}}=\frac{3}{2}\\ \frac{V_{DS3,DS4(peak)}}{V_{DS2,DS3(peak)}}=\frac{3}{2}\end{array}$
Peak inductor ripple current	$\Delta i_{Lpeak}=0.5\left(\frac{\sqrt{2}{V}_{i,peak}}{L}T\right)$	$\Delta i_{Lpeak}=0.667\left(\frac{\sqrt{2}{V}_{i,peak}}{L}T\right)$	$\frac{\Delta i_{Lpeak[22]}}{\Delta i_{Lpeak[\mathrm{Pr}oposed]}}=\frac{0.667}{0.5}$
Peak switching device current	$I_{Sw(peak)}=3\frac{P_0}{\sqrt{2}{V}_o}$	$I_{Sw(peak)}=3\sqrt{2}\frac{P_0}{V_o}$	$\frac{I_{Sw(peak)[22]}}{I_{Sw(peak)[\mathrm{Pr}oposed]}}=\frac{3}{2}$
Switching power losses	$P_{sw}=2f_{sw}\left[\begin{array}{l}\frac{1}{4}\left\{I_L{V}_i(t_{on}+t_{off})\right\}\\ +\frac{2Q_{RR}}{\pi }{V}_i\end{array}\right]$	$P_{sw}=3f_{sw}\left[\begin{array}{l}\frac{1}{4}\left\{I_L{V}_i(t_{on}+t_{off})\right\}\\ +\frac{2Q_{RR}}{\pi }{V}_i\end{array}\right]$	$\frac{P_{sw[22]}}{P_{sw[\mathrm{Pr}oposed]}}=\frac{3}{2}$

for buck and boost mode respectively. For the sake of making comparison simple, terms involving C_os are neglected.

4. Simulation Results and Discussion

The validity of the proposed research is explored by modeling the proposed converter in MATLAB/Simulink environment to find the switching stresses across high frequency switching devices.

4.1. Voltage Stresses of Switching Devices

To find the voltage stresses across the high frequency switches in buck and boost modes with bipolar voltage gain, the proposed converter is simulated with peak input voltage, and frequency of 65 V, and 50 Hz respectively. In buck operation, the output voltage is half than the source voltage, both in non-inverting and inverting modes, as the duty cycle for PWM controlled switches is taken as 0.5. The situation is displayed in Figure 6a,b. Similarly, with duty ratio of 0.5 (thus, with voltage gain of 2) for boost operation, the output voltage becomes two times the input voltage as depicted in Figure 6c,d. This implies that output voltage is linearly related with the duty ratio. The output voltage is in phase and out of phase with the input voltage as voltage gain is positive and negative respectively.

In addition, from the analysis of Figure 7a–d, it is clear that voltage stresses in buck and boost modes are restricted to V_i, and V_o, respectively, as compared to the existing converters, which are V_i + V_o. The switching stresses are complementary, as when one switch operates as DPWM, the other as IDPWM. It ensures low switching losses and improved conversion efficiency.

4.2. Conversion Losses and Efficiency

The total conversion losses of the proposed topology come from switching and conduction losses of the high and low frequency switching devices respectively. The conversion losses of the proposed converter, and converter in [22], are compared through the simulation results. The system parameters (taken from the datasheet) considered for the simulation purposes are the followings: Q_RR = 1 uC, V_d = 1 V, R_T = 0.08 Ω, R_d = 0.006 Ω, t_r = 30 ns, t_f = 50 ns, and f_sw = 50 kHz. Figure 8 depicts the comparison of conversion losses and efficiency.

The proposed topology comes with the advantages of low voltages and currents in the switching devices. It ensures low switching and conduction losses that result in improved conversion efficiency, as can be observed from the simulation results depicted in Figure 8.

5. Practical Validation

An experimental setup (see Figure 9) is built for further verification of the proposed converter. It includes eight power MOSFETs (IRF840), eight fast recovery diodes (RHRG3040), one filtering inductor of 1 mH, and two capacitors of 4.7 µF, and 1 µF for output, and input filter respectively. A step-down 230/50 V 50 Hz transformer is used to bring the voltage at safe level for laboratory prototype. STM microcontroller generates the gating signals for the controlled switches. A zero-crossing detector synchronizes the gating signals with respect to the input voltage waveform. Six hybrid chips (EXB840), with six isolated DC supplies are used as gate drivers for MOSFETs. The input voltage is 65 V peak at supply frequency of 50 Hz for buck and boost operation. The duty cycle of the high frequency (50 kHz) switches is maintained at 50% both for the buck and boost mode.

Buck and Boost Operation

The non-inverting and inverting buck and boost modes of the proposed converter are implemented, using two high and four low frequency switches, during a complete cycle of the source voltage. So only six control signals can implement all operating modes of the proposed converter just by changing their position to the controlled switches. Figure 10a–d illustrate the practically recorded waveforms of the output voltage in buck and boost mode with inverting and non-inverting characteristics. The in phase and out of phase output voltage depicts the positive and negative voltage gain respectively. Figure 11 shows the switching voltage across the high frequency switching devices.

As in the simulation results, the experimental results presented in Figure 11a–d confirm that the switching stresses, in the buck and boost operation, do not exceed the input, and output voltage, respectively. The inductor current in the boost mode is larger than that of its buck operation. It increases the voltage drops in the switching devices, thus causing lower output voltage and efficiency. In non-inverting and inverting boost mode, the inductor current is continuous with a low THD as it is conducted through the inductor and load in turn on and off intervals of switching period (see Figure 12). Therefore, these characteristics improve its power quality.

6. Conclusions

A novel AC voltage controller, operating in separate buck and boost mode, with a bipolar voltage gain, is proposed in this research. In all operating modes of the proposed topology, the voltage stresses across the high frequency switches, are reduced to 50%, with the duty ratio of 0.5. The high switching frequency control effort is also reduced by implementing all operating modes with one DPWM and one IDPWM control switch. Each operating mode requires the conduction of two low frequency switches having a low internal resistance and forward voltage. The proposed topology, not only offers less voltage stresses across the high frequency switches but also reduced peak inductor ripple current, peak switching device current, and conversion losses (switching and conduction power losses), thus improved efficiency compared to the other topology reported in literature. The devices with low voltage and current ratings can be utilized, due to the reduced voltage stresses. A low ripple in the output voltage and the absence of short through issues, improve the power quality of the output voltage. The hardware implementation of the proposed converter validates the simulation results obtained in the MATLAB/Simulink environment.