An Enhanced H-Bridge Multilevel Inverter with Reduced THD, Conduction, and Switching Losses Using Sinusoidal Tracking Algorithm

Abstract

In this paper, an enhanced H-Bridge multilevel inverter is proposed with the sinusoidal tracking algorithm. The proposed multilevel inverter (MLI) consists of two half H-Bridges cascaded with two unidirectional switches, n direct current (DC) sources, and (n-2) number of bi-directional switches together to form an enhanced H-Bridge (EHB) multilevel inverter. The output voltage levels of an EHB MLI depends on the number of DC sources, the number of bi-directional switches, and the relationship between the magnitude of left-side and right-side DC sources. With the addition of DC sources, bidirectional switches, and employing the sinusoidal tracking algorithm, the performance of the inverter is enhanced with features like an increased number of levels and a reduction in the total harmonic distortion and switching losses. In all the modes of operation of the proposed inverter, only three switches are “ON”, so that conduction losses are less. The proposed enhanced H-Bridge MLI is simulated using MATLAB/Simulink R2017a, and is verified with the experimental result.

1. Introduction

In recent years, multilevel inverters have become popular because of their competence for carrying high power, high voltage, good power quality, lower order harmonics, lower switching losses, and lower electromagnetic interference, due to the absence of an inductor and a capacitor [1,2,3]. Multilevel inverters generate close to sinusoidal voltages, as in the form of a stepped voltage waveform, using many direct current (DC) voltage sources. In a multilevel inverter, increasing the number of output voltage levels results in lower THD at the output voltage. There are three kinds of multilevel inverter structures: diode-clamped, flying capacitor, and cascaded H-Bridge (CHB). To produce higher levels, the flying capacitor and diode-clamped topologies use many capacitors and diodes, respectively. Also, both of the structures suffer from voltage inequality of capacitors [4,5,6,7,8]. The CHB topology can be suitable to generate higher voltage levels, because it requires fewer components compared to the conventional topologies [1,2]. CHB inverters can increase the number of output voltage levels by increasing the number of H-Bridges used, which increases the number of switching devices used; this makes a multilevel inverter more complicated. Modifications to the H-Bridge inverter topology reduces the number of components. A bi-directional switch is added in the conventional H-Bridge to get two additional voltage levels via a capacitor from a single DC voltage source, and final output is a stepped five-level output voltage [9,10,11,12,13,14]. A series and parallel connection of DC voltage sources cascaded with a conventional H-Bridge gives a stepped output with the reduced harmonics content in the output voltage [15,16]. Series connections of sub-multilevel, half-bridge symmetrical and asymmetrical inverters generate 13 and 31 levels, respectively, when cascaded to an H-Bridge inverter, in this topology six switches are “ON” in all the modes of operation [17,18]. Two half-bridges are cascaded by adding two unidirectional switches, and this forms the seven-level inverter [19]. The cascading of two units of developed H-Bridges produces 49 output voltage levels, but in all the modes of operation, six switches are in the “ON” state [20]. Two cascaded half H-Bridges are nested to form a single unit. One half-bridge inverter and two units of the nested cascaded half H-Bridges are connected in series with the H-Bridge inverter to generate 15 levels, and comprised of 16 switches and seven DC sources. In this topology, a minimum of five switches and a maximum of nine switches are in the “ON” state [21]. Most of the inverters use pulse width modulation method to generate the switching pulses; due to this, the switching losses are very high, especially in high-voltage and high-power multilevel inverters. Frequent high-voltage switching generates more heat, due to power losses in the switches, so reference frequency switching is best to minimize the switching losses [22]. A new multilevel inverter based on modified H-Bridge topology generates a 13-level stepped output, and uses the capacitor to generate the in-between levels, but voltage balancing of the capacitor is difficult and bulky under various loaded conditions [23]. The proposed topology consists of a left-side half H-Bridge inverter with q number of DC sources, (q − 1) number of bidirectional switches, and similarly the right-side half H-Bridge inverter with r number of DC sources, (r − 1) number of bidirectional switches. Finally, these two half H-Bridges cascaded with two unidirectional (S_X, S_Y) switches, as shown in Figure 1. In the proposed enhanced H-Bridge (EHB) multilevel inverter (MLI), in all the modes of operation, only three switches are “ON”, and a reference frequency switching method is used so that the conduction losses and switching losses are minimal. In this proposed topology, there is no storage element like an inductor, and hence the losses are minimized. In this paper, to enhance the performance of the base unit and to reduce the THD, a choice of bidirectional switches and DC sources on both sides with two different methods and a sinusoidal tracking algorithm is proposed, with simulated and experimental results. This EHB MLI is suitable for medium-voltage applications and also used in v/f control drives.

2. Proposed Enhanced H-Bridge Multilevel Inverter

A single-phase, general enhanced H-Bridge multilevel inverter is shown in Figure 1. This general enhanced H-Bridge multilevel inverter consists of (q − 1) and (r − 1) number of bi-directional switches, q number of voltage sources on the left side, and r number of voltage sources on the right side are embedded to form a developed H-Bridge multilevel inverter. The developed H-Bridge consists of six unidirectional power switches (S₁, S₂, S₃, S₄, S_X, and S_Y). The number of output voltage levels of an enhanced H-Bridge multilevel inverter depends on the number of DC voltage sources, bi-directional switches, and the relation between left- and right-side voltage sources.

If the enhanced H-Bridge inverter has two voltage sources (V_P1, V_P2) in the left side and two voltage sources (V_N1, V_N2) on the right side, and the number of bi-directional switches on the left side is one (2 − 1), and the number on the right side is one (2 − 1; q = 2 and r = 2), along with the regular six unidirectional switches. Since the number of bidirectional switches is the same on both sides, it is a symmetrical structure enhanced H-Bridge (SSEHB) multilevel inverter, as shown in Figure 2.

Suppose the enhanced H-Bridge inverter has two voltage sources (V_P1, V_P2) in the left side and three voltage sources (V_N1, V_N2, V_N3) on the right side and hence the number of bi-directional switches on the left side is one (2 − 1), and on right side is two (3 − 1; q = 2 and r = 3), along with the regular six unidirectional switches. Since the number of bidirectional switches is not equal on both sides, it is an asymmetrical structure enhanced H-Bridge (ASEHB) multilevel inverter, as shown in Figure 3.

3. DC Voltage Source Selection Methods

The general enhanced H-Bridge consists of (q - 1) bi-directional switches (S_P1, S_P2, S_P3…S_P(q−1)) on the left side, (r − 1) bi-directional switches (S_N1, S_N2, S_N3…S_N(r−1)) on the right side, and six unidirectional power switches, (S₁, S₂, S₃, S₄, S_X, and S_Y) are available in the developed H-Bridge inverter. The proposed topology as shown in Figure 1 contains q number of voltage sources (V_P1, V_P2, V_P3…V_Pq) and r number of voltage sources (V_N1, V_N2, V_N3…V_Nr) in the left and right side, respectively. Based on the relationship between left- and right-side voltage sources, two methods are proposed here.

Method I

There are q number of voltage sources (V_P1, V_P2, V_P3…V_Pq) in the left side, and are equal in magnitude.

$${\mathrm{V}}_{\mathrm{P}1}={\mathrm{V}}_{\mathrm{P}2}={\mathrm{V}}_{\mathrm{P}3}=\cdots ={\mathrm{V}}_{\mathrm{Pq}}$$

(1)

where q = 1, 2, 3…C

There are r number of voltage sources (V_N1, V_N2, V_N3…V_Nr) in the right side, and are equal in magnitude.

$${\mathrm{V}}_{\mathrm{N}1}={\mathrm{V}}_{\mathrm{N}2}={\mathrm{V}}_{\mathrm{N}3}=\cdots ={\mathrm{V}}_{\mathrm{Nr}}$$

(2)

where r = 1, 2, 3…D

Equations (3) and (4) specify the difference in magnitude between the left and right side voltage sources when Method I is applied.

$${\mathrm{V}}_{\mathrm{P}1}={\mathrm{V}}_{\mathrm{P}2}={\mathrm{V}}_{\mathrm{P}3}=\cdots ={\mathrm{V}}_{\mathrm{Pq}}={\mathrm{V}}_{\mathrm{DC}}$$

(3)

$${\mathrm{V}}_{\mathrm{N}1}={\mathrm{V}}_{\mathrm{N}2}={\mathrm{V}}_{\mathrm{N}3}=\cdots ={\mathrm{V}}_{\mathrm{Nr}}=\left(\mathrm{q}\right){\mathrm{V}}_{\mathrm{DC}}$$

(4)

Method II

$${\mathrm{V}}_{\mathrm{P}1}={\mathrm{V}}_{\mathrm{P}2}={\mathrm{V}}_{\mathrm{P}3}=\cdots ={\mathrm{V}}_{\mathrm{Pq}}$$

(5)

$${\mathrm{V}}_{\mathrm{N}1}={\mathrm{V}}_{\mathrm{N}2}={\mathrm{V}}_{\mathrm{N}3}=\cdots ={\mathrm{V}}_{\mathrm{Nr}}$$

(6)

Equations (7) and (8) specify the difference in magnitude between the left and right side voltage sources when method II is applied.

$${\mathrm{V}}_{\mathrm{P}1}={\mathrm{V}}_{\mathrm{P}2}={\mathrm{V}}_{\mathrm{P}3}=\cdots ={\mathrm{V}}_{\mathrm{Pq}}={\mathrm{V}}_{\mathrm{DC}}$$

(7)

$${\mathrm{V}}_{\mathrm{N}1}={\mathrm{V}}_{\mathrm{N}2}={\mathrm{V}}_{\mathrm{N}3}=\cdots ={\mathrm{V}}_{\mathrm{Nr}}=\left(\mathrm{q}+1\right){\mathrm{V}}_{\mathrm{DC}}$$

(8)

Method I Example

In SSEHB, the equal number of bidirectional switches on both sides is

$$\left(\mathrm{q}-1\right)=\left(\mathrm{r}-1\right)=\mathrm{n}$$

(9)

In the SSEHB topology, the number of output voltage levels (N_Level) is

$${\mathrm{N}}_{\mathrm{Level}}={(\mathrm{n}+1)}^2+{(\mathrm{n}+2)}^2$$

(10)

If n = 1, ${\mathrm{N}}_{\mathrm{Level}}={(1+1)}^2+{(1+2)}^2=13$.

If n = 2, ${\mathrm{N}}_{\mathrm{Level}}={(2+1)}^2+{(2+2)}^2=25$.

The number of uni-directional switches is

$${\mathrm{N}}_{\mathrm{Uni}}=6$$

(11)

The number of bi-directional switches is

$${\mathrm{N}}_{\mathrm{Bi}}=2\mathrm{n}$$

(12)

The number of dc voltage sources

$${\mathrm{N}}_{\mathrm{DC}}=2\left(\mathrm{n}+1\right)$$

(13)

The maximum and minimum magnitude of the generated output voltage is

$${\mathrm{V}}_{\mathrm{O},\mathrm{Max}}={\displaystyle {\displaystyle \sum }_{\mathrm{q}=1,2,3}^{\mathrm{C}}{\mathrm{V}}_{\mathrm{Pq}}+{\displaystyle \sum }_{\mathrm{r}=1,2,3}^{\mathrm{D}}}{\mathrm{V}}_{\mathrm{Nr}}$$

(14)

$${\mathrm{V}}_{\mathrm{O},\mathrm{Min}}={\mathrm{V}}_{\mathrm{P}1}$$

(15)

if the number of bidirectional switches are not equal on both side, then

$$\left(\mathrm{q}-1\right)\ne \left(\mathrm{r}-1\right)$$

(16)

If $\left(\mathrm{q}-1\right)>\left(\mathrm{r}-1\right),\mathrm{n}=\left(\mathrm{r}-1\right)$

Else if $\left(\mathrm{q}-1\right)<\left(\mathrm{r}-1\right)$

$$\mathrm{n}=\left(\mathrm{q}-1\right)$$

(17)

$$\mathrm{x}=\left(\left(\mathrm{q}-1\right)~\left(\mathrm{r}-1\right)\right)$$

(18)

In the ASEHB topology, the number of output voltage levels (N_Level) is

$${\mathrm{N}}_{\mathrm{Level}}={(\mathrm{n}+1)}^2+{(\mathrm{n}+2)}^2+\left(2+2\mathrm{n}\right)\mathrm{x}$$

(19)

If n = 1 and x = 0, then ${\mathrm{N}}_{\mathrm{Level}}={(1+1)}^2+{(1+2)}^2+\left(2+2\left(1\right)\right)0=13$.

If n = 1 and x = 1, then ${\mathrm{N}}_{\mathrm{Level}}={(1+1)}^2+{(1+2)}^2+\left(2+2\left(1\right)\right)1=17$.

If n = 1 and x = 2, then ${\mathrm{N}}_{\mathrm{Level}}={(1+1)}^2+{(1+2)}^2+\left(2+2\left(1\right)\right)2=21$.

$${\mathrm{N}}_{\mathrm{Uni}}=6$$

(20)

$${\mathrm{N}}_{\mathrm{Bi}}=2\mathrm{n}+\mathrm{x}$$

(21)

$${\mathrm{N}}_{\mathrm{DC}}=2\left(\mathrm{n}+1\right)+\mathrm{x}$$

(22)

$${\mathrm{V}}_{\mathrm{O},\mathrm{Max}}={\displaystyle {\displaystyle \sum }_{\mathrm{q}=1,2,3}^{\mathrm{C}}}{\mathrm{V}}_{\mathrm{Pq}}+{\displaystyle {\displaystyle \sum }_{\mathrm{r}=1,2,3}^{\mathrm{D}}}{\mathrm{V}}_{\mathrm{Nr}}$$

(23)

$${\mathrm{V}}_{\mathrm{O},\mathrm{Min}}={\mathrm{V}}_{\mathrm{P}1}$$

(24)

Method II Example

Where n is an equal number of bidirectional switches on both sides (SSEHB). The value of n can be found by using Equation (9).

The number of levels in the inverter output voltage is given below:

$${\mathrm{N}}_{\mathrm{Level}}=2\left(\mathrm{n}+1\right)+{(\mathrm{n}+1)}^2+{(\mathrm{n}+2)}^2$$

(25)

If n = 1, then ${\mathrm{N}}_{\mathrm{Level}}=2\left(1+1\right)+{(1+1)}^2+{(1+2)}^2=17$.

If n = 2, then ${\mathrm{N}}_{\mathrm{Level}}=2\left(2+1\right)+{(2+1)}^2+{(2+2)}^2=31$.

If n = 3, then ${\mathrm{N}}_{\mathrm{Level}}=2\left(3+1\right)+{(3+1)}^2+{(3+2)}^2=49$.

The equations for the number of uni-directional switches (N_Uni), number of bi-directional switches (N_Bi), number of dc voltage sources (N_DC), maximum magnitude of the generated output voltage (V_O,Max), and the minimum magnitude of the generated output voltage (V_O,Min) are the same for the SSEHB topology represented in Equations (11)–(15), respectively.

If the topology contains unequal bidirectional switches (ASEHB) i.e., (q − 1) bi-directional switches at the left side and (r − 1) bi-directional switches at the right side. The value of n and x can be found by using Equations (17) and (18), respectively.

$${\mathrm{N}}_{\mathrm{Level}}=2\left(\mathrm{n}+1\right)+{(\mathrm{n}+1)}^2+{(\mathrm{n}+2)}^2+\left(4+2\mathrm{n}\right)\mathrm{x}$$

(26)

If n = 1, x = 0, then ${\mathrm{N}}_{\mathrm{Level}}=2\left(1+1\right)+{(1+1)}^2+{(1+2)}^2+\left(4+2\left(1\right)\right)0=17$.

If n = 1, x = 1, then ${\mathrm{N}}_{\mathrm{Level}}=2\left(1+1\right)+{(1+1)}^2+{(1+2)}^2+\left(4+2\left(1\right)\right)1=23$.

If n = 3, x = 5, then ${\mathrm{N}}_{\mathrm{Level}}=2\left(3+1\right)+{(3+1)}^2+{(3+2)}^2+\left(4+2\left(3\right)\right)5=99$.

The equations for the number of uni-directional switches (N_Uni), number of bi-directional switches (N_Bi), number of DC voltage sources (N_DC), maximum magnitude of the generated output voltage (V_O,Max), and the minimum magnitude of the generated output voltage (V_O,Min) are the same for the ASEHB topology represented in Equations (20)–(24) respectively.

In this section, a various number of bidirectional switches are associated with the developed H-Bridge to enhance the performance of the base unit SSEHB and ASEHB inverter, and for further enhancement, the various methods are applied to the proposed inverters, as shown in Figure 1. The number of output voltage levels for the different number of bidirectional switches and the two methods are tabulated in

Table 1. Choice of the number of bidirectional switches with respect to the number of output voltage levels.

Number of Bidirectional Switches in the Left Side NBi. (q − 1)	Number of Bidirectional Switches in the Right Side NBi. (r −1)	Difference between the Number of Bidirectional Switches x = (q − 1) ~ (r − 1)	NLevel (Method I)	NLevel (Method II)
1	1	0	13	17
2	1	1	17	23
3	1	2	21	29
4	1	3	25	35
5	1	4	29	41
6	1	5	33	47
2	2	0	25	31
3	2	1	31	39
4	2	2	37	47
5	2	3	43	55
6	2	4	49	63
7	2	5	55	71
3	3	0	41	49
4	3	1	49	59
5	3	2	57	69
6	3	3	65	79
7	3	4	73	89
8	3	5	81	99

.

From Table 1, one can choose the number of bidirectional switches needed for the required level of output voltage. Comparing Methods I and II, Method II gives more output voltage levels for the same number of bidirectional switches.

3.1. Modes of Operation

As shown in

Table 2. Switching states of the proposed SSEHB inverter based on Method I.

Level	Output Level Voltage	On Switches
1	0	S3, SY, S4
2	VP2	SP1, S3, Sy
3	VP1 + VP2	S1, S3, Sy
4	VN2+ VP2	SN1, SP1, SY
5	VN2+ VP2 + VP1	S1, SN1, SY
6	VN2 + VN1+ VP2	SP1, S2, Sy
7	VN2 + VN2 + VP2 + VP1	S2, S1, SY
8	−VP1	SP1, S2, Sx
9	−(VP2+ VP1)	S4, S2, SX
10	−(VN1 + VP1)	SN1, SP1, SX
11	−(VN1 + VP2 + VP1)	SN1, S4, SX
12	−(VN2 + VN1 + VP1)	S3, SP1, SX
13	−(VN2 + VN1 + VP2 + VP1)	S3, S4, SX

, the SSEHB multilevel inverter shown in Figure 2 can generate 13 voltage levels—(±V_P2), ±(V_P1 + V_P2), ±(V_N2 + V_P2), ±(V_N2 + V_P2 + V_P1), ±(V_N2 + V_N1 + V_P2), ±(V_N2 + V_N1 + V_P2 + V_P1), and (0) at the output, by selecting different magnitudes of the DC voltage sources as per the proposed Method I. As per the proposed Method II, the same SSEHB inverter is able to generate 17 levels by selecting different magnitudes of the DC voltage sources.

The ASEHB multilevel inverter shown in Figure 3 is able to generate 17 voltage levels.at the output by selecting different magnitudes of the DC voltage sources, as per the proposed method I. As per the proposed method II, the same ASEHB inverter is able to generate 23 levels by selecting different magnitudes of the DC voltage sources, as shown in

Table 3. Switching states of the proposed asymmetrical structure enhanced H-Bridge (ASEHB) inverter based on Method II.

Level	Output Level Voltage	On switches
1	0	S3, SY, S4
2	VP2	SP1, S3, SY
3	VP1 + VP2	S1, S3, SY
4	VN3	SN2, S4, SY
5	VN3 + VP2	SN2, SP1, Sy
6	VN3 + VP2 + VP1	S1, SN2, SY
7	VN3 + VN2	SN1, S4, SY
8	VN3 + VN2+ VP2	SP1, SN1, SY
9	VN3 + VN2 + VP2 + VP1	SN1, S1, SY
10	VN3 + VN2+ VN1	S2, S4, SY
11	VN3 + VN2 + VN1 + VP2	S2, SP1, SYy
12	VN3 + VN2 + VN1 + VP2+ VP1	S1, S2, Sy
13	−VP1	SP1, S2, SX
14	−(VP2 + VP1)	S4, S2, SX
15	−VN1	SN1, S1, Sx
16	−(VN1 + VP1)	SN1, SP1, SX
17	−(VN1 + VP1 + VP2)	SN1, S4, SX
18	−(VN1+ VN2)	SN2, S1, SX
19	−(VN1 + VN2 + VP1)	SN2, SP1, SX
20	−(VN1 + VN2 + VP1 + VP2)	SN2, S4, SX
21	−(VN1 + VN2 + VN3)	S3, S1, SX
22	−(VN1+ VN2 + VN3 + VP1)	S3, SP1, SX
23	−(VN1 + VN2 + VN3 + VP1 + VP2)	S3, S4, SX

. The output voltage levels are ±(V_P2), ±(V_P1 + V_P2), ±(V_N3), ±(V_N3+ V_P2), ±(V_N3+ V_P2 + V_P1), ±(V_N3 + V_N2), ±(V_N3 + V_N2+ V_P2), ±(V_N3 + V_N2 + V_P2 + V_P1), ±(V_N3 + V_N2+ V_N1), ±(V_N3 + V_N2 + V_N1 + V_P2), ±(V_N3 + V_N2 + V_N1 + V_P2+ V_P1), and (0).

The 23 levels of the output voltage give 23 modes of operation. In any mode of operation, three switches are “ON”, and the remaining switches are “OFF”, as shown in Table 3. In all the modes of operation, one switch from the left side inverter circuit (S₁, S₄, or S_{P(q − 1)}) and one switch from the right side inverter circuit (S₂, S₃, or S_{N(r − 1)}), and one switch from the cascade connection (S_X, S_Y) are always in the “ON” state.

3.2. Voltage Stress across Switches

An important parameter that determines the cost of a multilevel inverter is the blocking voltage of the power switches, as well as the DC voltage sources. If the proposed inverter requires a variety of blocking voltage switches, then the cost of the inverter is too high. The voltage blocking mainly depends on the topology of the inverter. In this section, voltage stress across various switches are derived for SSEHB and ASEHB inverters when methods I and II are applied. The equation to find the voltage stress across the switches is the same for both the SSEHB and ASEHB inverter.

The relation between V_Pq and V_Nr for Method I employing SSEHB and ASEHB inverters is shown in Equation (4). Similarly, the relationship between V_Pq and V_Nr for Method II employs SSEHB, and an ASEHB inverter is shown in Equation (8). For finding the blocking voltage across a switch substitute, the value of V_Nr in terms of V_Pq can be determined by Equations (27)–(31).

The blocking voltage across various power switches are given below:

$${\mathrm{V}}_{\mathrm{S}1}={\mathrm{V}}_{\mathrm{S}4}=\left({\displaystyle {\displaystyle \sum }_{\mathrm{q}=1}^{\mathrm{C}}}{\mathrm{V}}_{\mathrm{Pq}}\right)$$

(27)

$${\mathrm{V}}_{\mathrm{S}2}={\mathrm{V}}_{\mathrm{S}3}=\left({\displaystyle {\displaystyle \sum }_{\mathrm{r}=1}^{\mathrm{D}}}{\mathrm{V}}_{\mathrm{Nr}}\right)$$

(28)

$${\mathrm{V}}_{\mathrm{SP}1}={\mathrm{V}}_{\mathrm{SP}2}\cdots .{\mathrm{V}}_{\mathrm{SP}\left(\mathrm{q}-1\right)}=\left({\displaystyle {\displaystyle \sum }_{\mathrm{q}=1}^{\mathrm{C}-1}}{\mathrm{V}}_{\mathrm{Pq}}\right)$$

(29)

$${\mathrm{V}}_{\mathrm{SN}1}={\mathrm{V}}_{\mathrm{SN}2}\cdots .{\mathrm{V}}_{\mathrm{SN}\left(\mathrm{r}-1\right)}=\left({\displaystyle {\displaystyle \sum }_{\mathrm{r}=1}^{\mathrm{D}-1}}{\mathrm{V}}_{\mathrm{Nr}}\right)$$

(30)

$${\mathrm{V}}_{\mathrm{SX}}={\mathrm{V}}_{\mathrm{SY}}=\left({\displaystyle {\displaystyle \sum }_{\mathrm{q}=1}^{\mathrm{C}}}{\mathrm{V}}_{\mathrm{Pq}}+{\displaystyle {\displaystyle \sum }_{\mathrm{r}=1}^{\mathrm{D}}}{\mathrm{V}}_{\mathrm{Nr}}\right)$$

(31)

3.3. Conduction and Switching Losses

In this proposed ASEHB MLI, in all the modes of operation, only three switches are “ON”, and corresponding driver circuits are only “ON”, and so the power loss in the inverter during conduction is less compared to cascaded conventional H-Bridge inverter—hence, the efficiency of the inverter is improved. Here P_C is the conduction loss of the power switches.

$${\mathrm{P}}_{\mathrm{C}}=3{\mathrm{I}}^2{\mathrm{R}}_{\mathrm{on}}$$

(32)

where I is the current following through the switch, and R_on is the on-state resistance of the switch during conduction period.

The switching losses mainly depend on the carrier frequency in pulse width modulation inverter, whereas here the switching is done based on the reference frequency compared with the input DC voltage levels, so the switching losses depend on the number of levels of the inverter. Here the switching losses are calculated in three group of switches.

The left side group is comprised of the switches S₁, S₄, and S_P1 to S_{P(q − 1)}, and the total left-side group switch losses is equal to P_SL. Similarly, the right-side group is comprised of the following switches S₂, S₃, and S_N1 to S_N(r-1), and the total right-side group switch losses is equal to P_SR. Finally, the cascaded group comprises the following switches S_X and S_Y, and the total cascaded switching losses are equal to P_Scas.

$${\mathrm{P}}_{\mathrm{SL}}=\left(2{\mathrm{N}}_{\mathrm{Level}}-1\right) {\mathrm{f}}_{\mathrm{ref}}{\mathrm{C}}_{\mathrm{ce}}\left({\displaystyle {\displaystyle \sum }_1^{\mathrm{q}}}{\mathrm{V}}_{\mathrm{Pq}}^2\right)$$

(33)

$${\mathrm{P}}_{\mathrm{SR}}=\left\{\mathrm{integer}\mathrm{of}\left[\frac{\left(2{\mathrm{N}}_{\mathrm{Level}}-1\right)}{\left(\mathrm{q}+1\right)}-1\right]\right\}{\mathrm{f}}_{\mathrm{ref}}{\mathrm{C}}_{\mathrm{ce}}\left({\displaystyle {\displaystyle \sum }_1^{\mathrm{r}}}{\mathrm{V}}_{\mathrm{Nr}}^2\right)$$

(34)

$${\mathrm{P}}_{{\mathrm{S}}_{\mathrm{cas}}}=2{\mathrm{f}}_{\mathrm{ref}}{\mathrm{C}}_{\mathrm{ce}}{\mathrm{V}}_{\mathrm{o},\max }^2$$

(35)

Here the f_ref is the reference frequency, and C_ce is the capacitance across the collector and emitter of IGBT.

3.4. Sinusoidal Tracking Algorithm for an Enhanced H-Bridge Multilevel Inverter

This algorithm tracks the fundamental sinusoidal function to calculate the time at which to turn on the switches. The V_m and f is calculated with the help of sinusoidal reference. With the help of f and V_m = V_ref.p, fundamental reference V_ref is generated as given in Equation (36). A rectangle with area A_i is formed between successive voltage levels (∆V), and the time interval between these voltage levels (∆t). To find the equal area between two successive voltage levels, increment time by j, where the sampling time j is given in Equation (38). Increment the time by j and find V_ij, then calculate the area A_ij until the area of the rectangle is exactly 25% of the total area A_i. At that resultant time (t_jopt) or angle (α) and voltage, the corresponding switches for i mode are turned on. Similarly, calculate for all the voltage levels from zero to V_max. The best switching times to get the minimum THD using this sinusoidal tracking method is the time when the areas of the upper and the lower triangle of the fundamental sinusoidal wave are equal, as shown in Figure 4. Figure 5 details the switching states and timing calculation of the sinusoidal tracking algorithm for various input sinusoidal reference using a flowchart. This sinusoidal tracking algorithm is implemented with the help of a high-level language. The switching time is calculated offline and stored in the local PROM (programmable read only memory) of the PIC (peripheral interface controller) for various inputs of sinusoidal reference. Consider that the input DC voltages are stable and ripple-free to get a perfect enhanced performance for the proposed EHB MLI.

$${\mathrm{V}}_{\mathrm{ref}}={\mathrm{V}}_{\mathrm{ref}.\mathrm{p}}\sin \mathsf{\omega }\mathrm{t}$$

(36)

$$\mathrm{X}=2\left(\mathrm{integer}\mathrm{of}\left(\frac{{\mathrm{V}}_{\mathrm{ref}.\mathrm{P}}}{{\mathrm{V}}_{\mathrm{P}1}}+0.99\right)\right)$$

(37)

$$\mathrm{j}=\frac{1}{\mathrm{f}\ast \mathrm{10,000}}$$

(38)

$${\mathrm{V}}_{\mathrm{i}}={\mathrm{i}\ast \mathrm{V}}_{\mathrm{p}1}$$

(39)

$${\mathrm{t}}_{\mathrm{i}}=\frac{{\sin }^{-1}\left(\frac{{\mathrm{V}}_{\mathrm{i}}}{{\mathrm{V}}_{\mathrm{m}}}\right)}{\mathsf{\omega }}$$

(40)

3.5. Comparison with Other Multilevel Inverters

Table 4. Comparison of the basic cell used in the various topologies.

Parameter	NDC	NUni	NBi	Nlevel	NON	NVariety
H-Bridge	1	4	--	3	2	1
Modified H-Bridge [7,8,9,10,11,12]	2	4	1	5	2	2
Developed H-Bridge [19]	2	6	--	7	3	3
Cascaded developed H-Bridge [19]	4	10	-	31	5	5
Series connection of sub-MLI [17]: symmetric	6	14	--	13	6	2
Series connection of sub-MLI [17]: asymmetric	4	12	--	31	6	5
Proposed SSEHB (Method I)	4	6	2	13	3	5
Proposed SSEHB (Method II)	4	6	2	17	3	5
Proposed ASEHB (Method I)	5	6	3	17	3	5
Proposed ASEHB (Method II)	5	6	3	23	3	5
ASEHB (Method II)	6	6	4	31	3	5

compares the advantages of the proposed enhanced H-Bridge MLI with the various other H-Bridge multilevel inverters. N_ON is the number of switches that are “ON” in a particular state.

The modified H-Bridge inverter [7] requires 14 bidirectional switches and 15 symmetrical value DC voltage sources to get a 31-level output voltage. The cascaded developed H-Bridge inverter [19] needs 10 unidirectional switches and four DC voltage sources to get a 31-level output voltage. With the proposed base unit EHB 31 level inverter, or even a 99-level inverter, in all the modes of operation only three switches are “ON”, whereas with the cascaded developed H-Bridge [19], five switches are on in all the modes of operation for 31 levels. Hence, the switching conduction losses are minimized compared to the cascaded developed H-Bridge [19], but there is an increase in the number of DC sources. The proposed enhanced H-Bridge is the most suitable for a higher number of levels, a lower THD with reduced switching conduction losses, and the lesser number of a variety of blocking voltage power switches.

4. Simulation Results

To study and verify the performance of a single-phase SSEHB 13-level inverter with optimum components, a 13-level output based on the Method I has been simulated. Table 2 shows the switching states of the 13-level inverter. Simulation has been done by using MATLAB/SIMULINK R2017a software, and

Table 5. Simulation parameters.

Parameter	SSEHB Inverter (Method I)	ASEHB Inverter (Method II)	ASEHB Inverter (Method II)-Medium Voltage
Input voltage
VP1	55	30	300
VP2	55	30	300
VN1	110	90	900
VN2	110	90	900
VN3	–	90	900
NUni	6	6	6
NBi	2	3	3
Load resistor in ohm	50	50	50
RL load	50 + j0.055 Ω	50 + j0.055 Ω	–
Output frequency	50	50	50
NLevel	13	23	23
VM (Peak)	330	330	3300

lists the simulation parameters. For the proposed SSEHB 13-level inverter, the output voltage is obtained by comparing various (±55, ±110, 165, ±220, ±275, ±330, 0) DC levels with the fundamental sinusoidal function (335 V), as per the switching pattern, is given in Table 2. Similarly, to study and verify the performance of a single-phase ASEHB 23-level inverter with optimum components, a 23-level output voltage based on Method II has been simulated. Table 3 shows the switching states of the 23-level inverter. The output voltage of the proposed ASEHB 23-level inverter is obtained by comparing the various (±30, ±60, ±90, ±120, ±150, ±180, ±210, ±240, ±270, ±300, ±330, 0) DC levels with the fundamental sinusoidal function (335 V) as per the switching pattern given in the Table 5.

The MATLAB/SIMULINK model for the proposed ASEHB 23-level inverter 300 V peak is as shown in Figure 6.

The pulse generator of switch S₃ is shown in Figure 7. The optimum time (t_jopt) to turn on a switch is obtained from the sinusoidal tracking algorithm. The amplitude of the reference sinusoidal at the optimum time (t_jopt) and the previous state of a switch is compared to generate the pulse. Similarly, for all the transitions of switch S₃, switching pulses are generated and logically ‘OR’ed to give the complete pulse of S₃. The switching pulses for all other switches are generated using the same procedure.

Figure 8 shows the simulated output voltage and current waveforms of a proposed single-phase SSEHB 13-level inverter connected to a standalone R load. From observation, the SSEHB inverter generates the desired 13-level, 50 Hz stepped output voltage (sinusoidal fundamental) and the current waveform.

Figure 9 Shows the frequency spectrum of the SSEHB 13-level inverter’s output voltage and current waveform when connected to a purely resistive load. The total harmonic distortion of voltage and current is found to be 5.45% and 5.45%, respectively.

Figure 10 shows the simulated output voltage and current waveforms of a proposed single phase SSEHB 13-level inverter connected to a standalone RL load. From the observation, the SSEHB inverter generates the desired 13-level, 50 Hz stepped output voltage (sinusoidal fundamental) and the current waveform.

Figure 11 shows the frequency spectrum of the SSEHB 13-level inverter’s output voltage and current waveform when connected to an RL load. The total harmonic distortion of the current is found to be 3.51%.

Figure 12 shows the simulated output voltage and current waveforms of a proposed single-phase ASEHB 23-level inverter connected to a standalone R load. From observation, the ASEHB inverter generates the desired 23-level, 50 Hz stepped output voltage (sinusoidal fundamental) and the current waveform.

Figure 13 shows the frequency spectrum of the ASEHB 23-level inverter’s output voltage and current waveform when connected to a purely resistive load. The total harmonic distortion of voltage and current is found to be 1.09% and 1.09%, respectively.

Figure 14 shows the simulated output voltage and current waveforms of a proposed single-phase ASEHB 23-level inverter connected to a standalone RL load. From the observation, the ASEHB inverter generates the desired 23-level, 50 Hz stepped output voltage (sinusoidal fundamental) and the current waveform.

Figure 15 shows the frequency spectrum of the ASEHB 23-level inverter’s output current waveform when connected to an RL load. The total harmonic distortion of current is found to be 0.45%.

The voltage stress across the various switches of an ASEHB 23-level 330 V peak inverter with the help of MATLAB simulation is shown in Figure 16. Analyzing Figure 16, the maximum voltage stress across the switches is S₁ = 60 V, S₂ = 270 V, S_P1 = 30, S_N1 = 180, and S_X = 330, which is validated with Equations (27)–(31), respectively.

Figure 17 shows the simulated medium output voltage and current waveforms of a proposed single-phase ASEHB 23-level inverter connected to a standalone R load. From the observation, the ASEHB inverter generates the desired 23-level, 50 Hz stepped peak 3300 V output voltage (sinusoidal fundamental) and the current waveform.

Figure 18 shows the frequency spectrum of the ASEHB 23-level inverter’s output 3300 V peak waveform when connected to an R load. The total harmonic distortion of the voltage was found to be 1.09%.

Experimental Results

From Table 3, an ASEHB inverter employed with Method II produces a higher number of output voltage levels compared to Method I for the same number of switching devices. The complete comparison is also tabulated in Table 1. This comparison, along with the simulation results shown in Figure 12a, has been the motivating factor in developing an ASEHB 23-level inverter working model.

Table 6. Hardware specifications.

Parameter	Value	Part Number
Number of DC input voltage sources	5	-
VP1	30 V	-
VP2	30 V	-
VN1	90 V	-
VN2	90 V	-
VN3	90 V	-
Number of unidirectional switches	6	KGT25N120NDA
Number of bidirectional switches	3	KGT25N120NDA
Number of gate drive circuits	9	TLP250
Microcontroller	1	PIC16F887
Load resistor (in ohm)	50	-
Number of output voltage levels	23	-

lists the hardware specifications. In this, the PIC 16F887 series is used to generate the switching states, with the help of a comparison of various DC voltage levels with the reference signal, and stores the switching state’s timing in it.

The switching frequency is very low, as per the comparison of various DC voltage levels with the reference signal; hence, IGBT was chosen for power inverter circuits. This switching pulse triggers the IGBT switches present in the inverter through isolated gate driver circuits. Figure 19 shows the hardware layout, and the ASEHB 23-level 660 V peak-to-peak and 233 V RMS (root mean square) hardware output voltage is shown in Figure 20. The THD value of an ASEHB 23 level inverter working model is 4.17%, as shown in Figure 21, measured with the help of utility software, TDSPCS1 v2.6,-enabled Tektronix digital storage oscilloscope.

5. Conclusions

In this paper, a single-phase EHB multilevel inverter employed with a sinusoidal tracking algorithm has been proposed to generate 13-, 17-, and 23-level output voltages, respectively. From Table 2 and Table 3, Method II gives an enhanced performance to the proposed ASEHB inverter. The most important advantages of this topology are (1) less conduction loss, due to the reason that only three switches are “ON” in all the modes of operation; (2) fewer switching losses; and (3) a reduction in the variety of the blocking voltage and driver circuit used, compared with conventional H-Bridge inverters. In the proposed inverter, only three switches are “ON” in all the modes, hence the conduction losses are minimized compared with other MLIs, as shown in Table 4. The output voltage waveform of the ASEHB 23-level inverter contains 4.17% THD, as shown in Figure 18. In the proposed inverter, the switching devices are designed for high-voltage and low-frequency operation. Therefore, the EHB multilevel inverter can be applied to medium power applications. This basic cell is suitable up to 99 levels—beyond that, the cascading of two basic units with a suitable number of bidirectional switches gives the required number of voltage levels.

The future scope of this paper is that the proposed enhanced H-Bridge multilevel inverter can be cascaded to generate a higher number of levels.