1. Introduction
In recent years, power semiconductor devices such as the insulated gate bipolar transistor (IGBT) and the metal-oxide semiconductor field effect transistors (MOSFETs) have been widely applied in many industrial fields especially fields with high reliability requirements in new energy, wind power generation, and automotive and aerospace industries [
1]. Therefore, the reliability issues have become the focus of increasing concern. In particular, the novel wide band gap (WBG) devices, which are high electron mobility transistors such as silicon carbide (SiC) power MOSFET or gallium nitride (GaN), can significantly improve power density and conversion efficiency. However, due to the lack of related technology and the instability of the gate oxide layer, the WBG devices require significant condition monitoring to ensure its reliability [
2,
3,
4]. Studies have shown that 31% of failures in power electronic converters can be attributed to the failure of power devices while 60% of device failures are due to thermal stress. In fact, due to the different thermal expansion coefficients of several materials in power semiconductor modules, the accumulation of thermal stress will eventually lead to aging failure. In an actual operating condition, the higher the junction temperature is, the smaller the safety margin of the operation is. Additionally, the greater the junction temperature fluctuations are, the shorter the life of the thermal cycle is. Therefore, the measurement or estimation of junction temperature is essential for its condition monitoring [
5,
6]. Obtaining this temperature in real time during the operation of the converter can effectively improve the status monitoring system of the SiC MOSFET. In addition, using the junction temperature-based control algorithm can enhance the lifetime of the module [
7].
The current methods for obtaining the power semiconductor junction temperature are mainly through a direct measurement method and an indirect measurement method. Direct measurement methods are based on optical and physical contact methods that use infrared cameras (IR) and thermocouples to measure the junction temperature, but they need to destroy the module package structure [
8,
9]. This method uses an internal implanted thermistor sensor to obtain temperature, but it is limited by the accuracy and bandwidth of the sensor and the dynamic response is slow (a few milliseconds are required). This means the methods based on optical and physical contact are limited in practical industrial applications. Indirect measurement methods mainly include the RC thermal impedance model [
10,
11] and the thermo-sensitive electrical parameter (TSEP). The RC thermal resistance network model mainly includes the Foster and Cauer models, but they do not consider changes in the thermal impedance caused by aging, which results in the inability to obtain accurate junction temperatures. Based on the TSEP, the temperature estimation of the standard package module can be performed non-invasively without modifying the module itself and only the electrical parameters of the device need to be obtained. Many studies have found that the TSEP method is the most promising solution for monitoring the junction temperature of the module [
12]. The high-precision and fast-response temperature measurement of the power device can be performed, and the junction temperature can be measured online or offline using TSEP. This is a very extensive research field. Reference [
13] uses the on-resistance
Ron to obtain the junction temperature of the IGBT. However, due to the low on-resistance of the SiC MOSFET (several tens of mΩ), a very precise measurement circuit is required and the switching frequency of the SiC MOSFET is high. It is difficult to measure the junction temperature accurately. In Reference [
14], the IGBT junction temperature was measured using the Miller plateau voltage (
VGP). However, due to the high switching speed of the SiC MOSFET, the turn-on transient is only few hundred nanoseconds, which means the length of the Miller platform is very short and is difficult to measure. Reference [
15] provides a method for measuring the junction temperature using the threshold voltage (
VTH) of the IGBT. Physically,
VTH is the minimum gate bias inducing an inversion layer of free electrons underneath the gate oxide. It creates a conductive channel between the drain and source in MOSFET or the collector and emitter in IGBT. Since this voltage is not well defined, a quasi-threshold voltage (gate voltage of drain current reaching 10% of rated current) can only be obtained by detecting the value of the drain current. Reference [
16] uses the turn-off delay of IGBT to measure the junction temperature, but SiC MOSFET is a unipolar switching device and does not include any extracting minority carriers during the turned off transient. Therefore, the junction temperature cannot be measured using the temperature sensitivity of the minority carrier during the turn off transient. Reference [
17] proposed a method to obtain the junction temperature based on the peak value of the gate current
IG peak during the SiC MOSFET turn-on transient. Based on the positive temperature coefficient of the internal gate resistance (
RG-in), SiC MOSFET can generate different gate currents at different temperatures. The junction temperature is extracted by obtaining the peak value of the gate current.
Reference [
18] includes an analysis of the relationship between
dIDS/dt and the junction temperature during the SiC MOSFET turned on and off transient. However, it lacks the experimental research on the large current module and does not design a measurement circuit to define the junction temperature. In summary, compared to silicon semiconductors, there are few studies on the junction temperature of silicon carbide semiconductors. Due to the wide bandgap characteristics of SiC MOSFET, some methods of extracting junction temperature can be used on silicon IGBT but cannot be applied to SiC MOSFET. In this paper, based on the switching characteristics of SiC MOSFET, the junction temperature is obtained by the turn-on current switching rate (
dIDS/dt). Firstly, it is analyzed that the temperature sensitivity of
dIDS/dt is mainly related to the negative temperature coefficient of the threshold voltage (
VTH). Second, an experimental platform was established to demonstrate the good linear relationship between
dIDS/dt and the junction temperature. The effects of gate drive resistance
RG, the supply voltage
VDC, load current
IDS, and the drive voltage
VGG on
dIDS/dt have been experimentally verified. Lastly, a small and economical Rogowski coil measuring circuit for obtaining the
dIDS/dt is proposed. The circuit can be embedded in the SiC MOSFET driver. The feasibility of the circuit to obtain the junction temperature is verified by experiments. In practical engineering applications, considering the switching loss and frequency, an intelligent driver method is proposed to measure the junction temperature of the SiC MOSFET without increasing the switching loss.
2. Theoretical Analysis of Turn-On dIDS/dt Temperature Dependence
Figure 1a shows the cell structure of the planar SiC MOSFET. It can be seen that the cell of the SiC MOSFET is mainly composed of the gate, source, drain, oxide layer, N-drift region, N-base region, and Junction Field-Effect Transistor (JEFT) region. The figure also shows the route of the electron carrier flow, the position of inversion layer channel, and the distribution of parasitic capacitance.
Figure 1b shows the typical SiC MOSFET turn-on transient waveforms under an inductive load. In order to facilitate the theoretical analysis, the parasitic inductance of the switching loop is neglected [
19]. This switching process can be divided into four phases to analyze further. Before
t0, SiC MOSFET is blocked, the driving voltage
VGG =
Uoff, the drain-source voltage
VDS =
VDC (DC-link voltage), and the gate current
IG is zero.
In Phase 1 (
t ∈ [
t0,
t1]), the turn-on pulse trigger at t
0, the driving voltage
VGG =
Uon, and the gate current
IG first performs a step to its maximum value and then starts to decay. At the same time, the gate voltage
VGS begins to increase. Due to the forward bias of
VGS, holes in the P base region are first squeezed out to form a depletion layer. With the increase of
VGS, the electrons (minority carriers) in the P base region begin to gather under the gate oxide layer to form an inversion layer channel when the energy band is bent to the surface potential, which is equal to the body potential.
VGS rises to the threshold voltage
VTH when the inversion layer channel is formed at
t1.
tTH is the turn-on delay time. When initiating the turn-on until
VGS reaches
VTH, it can be calculated by using Equation (1) where
RG is the gate total resistance and
CISS is the input capacitance. The expression for
VTH can be obtained from reference [
18] where
q is the charge constant,
VFB is the flat-band voltage (related to the oxide layer and semiconductor interface charge and gate material),
ξsic is the dielectric constant of the semiconductor, and
NA is the doping concentration.
COX is the oxide layer capacitance,
T is the absolute temperature (thermodynamic temperature), the Fermi potential
ΨB is the potential difference between the mid-gap and the Fermi level far from the surface, and
К is the Boltzmann constant.
Using Equation (3), it can be seen that
ΨB is related to the doping concentration and temperature of the semiconductor and
ni is the concentration of the carrier. If the start time of turn-on is 0, the changing rate of the gate voltage can be calculated by using the equation below.
Phase 2 (
t ∈ [
t1,
t2)) is the inversion layer channel established at time
t1. The electron carriers start to enter in the JFET region and the drain-source current
IDS starts to increase. When
IDS reaches the rated current, the freewheeling diode starts to reverse recovery and the
IDS reaches its maximum value at time
t2. Due to the influence of the parasitic inductance between the drain and source, the drain-source voltage
VDS drops by a small step, but since
VDS >> (
VGG−
VTH), SiC MOSFET is in the saturation region, which means the expression of the drain current
IDS can be calculated by using the following equation:
In the above equations,
β is the gain coefficient,
WCH is the channel width of the inversion layer,
μCH is the effective mobility of the channel electrons,
COX is the capacitance of the oxide layer, and
L is the channel length. The current switching rate
dIDS/dt can be calculated together with Equation (4) and the derivative of Equation (5), which is shown below.
In Phase 3 (t ∈ [t2,t3)), when the drain-source current IDS reaches the maximum value at time t2, the gate voltage VGS rises to the Miller plateau voltage VGP, VGS remains basically unchanged, and IDS starts to fall to the rated current. After the reverse recovery of the freewheeling diode is complete, the gate current IG charges to the Miller capacitance reversely. At the same time, the drain-source voltage VDS begins to drop and drops to a very low on-state voltage at t3. The Miller plateau stage ends.
In Phase 4 (t ∈ [t3,t4)), the gate capacitance CGS is charged by the gate current IG after t3. VGS starts to increase exponentially and rises to the driving voltage VGG at t4. In addition, IG decreases to zero. At the end of this phase, the SiC MOSFET is fully turned on.
From the SiC MOSFET turn-on process, it can be seen that temperature-related factors include the threshold voltage
VTH and the drain current change rate
dIDS/dt. When Equations (2) and (3) are combined, the temperature is derived to obtain Equation (8). From Equation (2), the threshold voltage
VTH is a function of temperature. As the temperature is raised, the band bending (2
ΨB) required to induce an inversion layer decreases due to the rapid increase in the intrinsic carrier concentration (
ni) in Equation (3). This is partially offset by the temperature pre-factor (
KT) and the increased ionization of acceptors
NA when the temperature is raised. However, as the temperature rises, the Fermi level moves closer to the mid-gap. Therefore, the band bending (2
ΨB) needed to reach the threshold decreases. This reduces the threshold voltage, which is shown in Equation (2) [
20]. Therefore, the threshold voltage decreases with an increasing temperature and shows a negative temperature coefficient.
The derivation of the temperature is obtained by using Equation (7).
From Equation (9), it can be concluded that the temperature coefficient of
dIDS/dt is related to the gate threshold voltage
VTH and the temperature coefficient of the gain coefficient
β. Based on Equation (6), the gain coefficient
β is proportional to the channel width
WCH, the effective mobility of the channel
μCH, and the oxide capacitance
COX, but is inversely proportional to channel length
L.
WCH,
μCH, and
COX are related to the manufacturer’s process and are constant under the same module, which means
β only relates to
μCH. In the silicon semiconductor,
μCH is about half of the mobility of the drift region while, in 4H-SiC,
μCH is only 5–10% of the mobility of the drift region. It is mainly affected by the surface roughness scattering, Coulomb scattering, and phonon scattering of the semiconductor and oxide interfaces [
21]. The main effect of
μCH is Coulomb scattering at room temperature. As the temperature increases, the surface roughness scattering and Coulomb scattering decrease and a large number of phonon scattering increases, which results in a decrease of the carrier mobility. Therefore,
μCH decreases with an increasing temperature. From Equation (6),
β displays a negative temperature coefficient, but due to the wide bandgap characteristics of SiC MOSFET,
μCH is very low and the temperature sensitivity of
β is also low. Therefore, the negative temperature coefficient of
VTH dominates the negative temperature coefficient of
β [
21]. The temperature coefficient of
dIDS/dt ((
dIDS)
2⁄(dt·dT)) is mainly affected by the threshold voltage
VTH.
Reference [
22] proposed that the input capacitor
CISS is also affected by the temperature because
CISS includes Miller capacitance and gate capacitance
CGS where the gate capacitance
CGS does not change with temperature. The Miller capacitance is composed of the oxide layer capacitance
COX and depletion layer capacitance
Cdep. In general,
COX does not change with the temperature. The expression of
Cdep is shown in the equation below.
In Equation (10),
A is the effective area of the capacitor area,
ξsic is the dielectric constant,
q is the unit charge,
ND,
NA is the doping concentration of the donor and acceptor, and
VDS is the drain voltage of SiC MOSFET. When the temperature rises, the doping concentration increases, and the Miller capacitance increases with a rise in temperature. It shows a positive temperature coefficient. However, since the rise of the drain-source current
IDS mainly occurs in Phase 2 (
t1,
t2), the drain voltage
VDS is large during this period, which means the depletion capacitance
Cdep is small. The Miller capacitance is mainly the oxide capacitance
COX [
20]. Therefore, the temperature effect of the input capacitor
CISS can be ignored.
In summary, due to the negative temperature coefficient of the threshold voltage (a negative sign before dVTH/dT in Equation (9)), the turn-on dIDS/dt shows a positive temperature coefficient and the SiC MOSFET turns on faster at a higher temperature.
4. Design Measuring Junction Temperature Circuit and Experimental Verification
The
dIDS/dt as a real-time junction temperature extraction for SiC MOSFETs can be achieved using the following method. For the SiC MOSFET module with a source auxiliary terminal
S, it is possible to measure the peak value of the induced voltage
VS’S generated by the parasitic inductance
LS between the source assist
S’ and the source
S during the SiC MOSFET turn-on transient. The value of
LS can be found in the device manual. According to the formula
VS’S =
L(
dIDS/dt), the value of
dIDS/dt can be obtained.
Figure 15 shows the peak value measurement circuit of
VS’S, but the above circuit is only suitable for SiC MOSFET modules with an auxiliary source. In order to target all modules, a measurement circuit based on the printed circuit board (PCB) Rogowski coil [
26] was proposed. The measurement circuit is shown in
Figure 16a. It consists of two high-precision operational amplifiers (LM7171), a diode, a storage capacitor of 4.7 nF, and a discharge resistor
R1. The first LM7171 is mainly used to acquire the parameters of the
dIDS/dt sensed by the PCB Rogowski coil and is used to isolate the high voltage. The second LM7171 mainly amplifies the resolution according to the actual needs. It facilitates the acquisition of the one-to-one correspondence between
dIDS/dt and the junction temperature. From
Figure 17b, it can be seen that the circuit occupies a small space and the cost is low so that it can be embedded in the drive module. The PCB Rogowski coil can be directly mounted on the terminal of the SiC MOSFET module, which offers a new idea for engineering applications.
In order to verify the feasibility of the circuit, the driving voltage is 12 V under the voltage and current level of 350 V and 100 A and the double pulse experiments are carried out at the working junction temperature of SiC MOSFET at 50 °C, 75 °C, 100 °C, 125 °C, and 150 °C, respectively. The magnification of the measurement circuit is 1 (This value can be changed by adjusting the ratio of
R2 to
R3) and the output waveform is shown in
Figure 17. It can be seen that each temperature corresponding to the measured voltage shows better linearity. The measured voltage is 0.4 V at 50 °C, and 0.8 V at 150 °C. In addition, the resolution is 4 mV/°C. The resolution can be increased by increasing the amplification of the operational amplifier. The Junction temperature of SiC MOSFET can be obtained by using Equation (13) where
T1 is the calculation temperature,
K1 is the resolution (250 °C/mV), and
V1 is the measuring voltage by this measuring circuit.
To further test the feasibility of extracting the junction temperature of this circuit, the heating plate is adjusted to different temperatures. The measured voltage is obtained by the measuring circuit of
Figure 16 and the measured temperature can be calculated by using Equation (13). The result is shown in
Table 1. It can be observed that, compared with the actual junction temperature, the maximum deviation of the calculated temperature does not exceed 5 °C. Therefore, this circuit for extracting the junction temperature of SiC MOSFET is feasible. In an actual operation, the junction temperature and the measurement voltage corresponding to the calculated temperature are converted into the digital signals by the A/D module (Analog to Digital Converter) and are stored in the Field-Programmable Gate Array (FPGA) of the driving module. The junction temperature is obtained by looking up the table.
As mentioned above,
dIDS/dt has better temperature sensitivity under a small drive voltage and a large drive resistance, but it also brings about an increase in the switching loss. Since the real work does not need to extract the junction temperature at every moment, an intelligent driver [
27] can be used to set a small time period to make the driver open SiC MOSFET under the large resistance and small drive voltage for the junction temperature extraction. After the data is acquired, the original small drive resistance and large gate voltage are restored. Therefore, the accurate junction temperature can be extracted while satisfying fast switching frequency and small switching loss. In summary, it is feasible to extract the junction temperature from SiC MOSFET based on
dIDS/dt.