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Energies 2017, 10(9), 1357; doi:10.3390/en10091357

Article
Modeling and Analysis of the Common Mode Voltage in a Cascaded H-Bridge Electronic Power Transformer
Yun Yang, Chengxiong Mao, Dan WangOrcid, Jie Tian * and Ming Yang
State Key Laboratory of Advanced Electromagnetic Engineering and Technology, School of Electrical and Electronic Engineering, Huazhong University of Science and Technology, Wuhan 430074, China
*
Correspondence: Tel.: +86-27-8754-2669
Academic Editor: Tomonobu Senjyu
Received: 13 August 2017 / Accepted: 5 September 2017 / Published: 8 September 2017

Abstract

:
Electronic power transformers (EPTs) have been identified as emerging intelligent electronic devices in the future smart grid, e.g., the Energy Internet, especially in the application of renewable energy conversion and management. Considering that the EPT is directly connected to the medium-voltage grid, e.g., a10 kV distribution system, and its cascaded H-bridges structure, the common mode voltage (CMV) issue will be more complex and severe. The CMV will threaten the insulation of the entire EPT device and even produce common mode current. This paper investigates the generated mechanism and characteristics of the CMV in a cascaded H-bridge EPT (CHB-EPT) under both balanced and fault grid conditions. First, the CHB-EPT system is introduced. Then, a three-phase simplified circuit model of the high-voltage side of the EPT system is presented. Combined with a unipolar modulation strategy and carrier phase shifting technology by rigorous mathematical analysis and derivation, the EPT internal CMV and its characteristics are obtained. Moreover, the influence of the sinusoidal pulse width modulation dead time is considered and discussed based on analytical calculation. Finally, the simulation results are provided to verify the validity of the aforementioned model and the analysis results. The proposed theoretical analysis method is also suitable for other similar cascaded converters and can provide a useful theoretical guide for structural design and power density optimization.
Keywords:
electronic power transformer; cascaded H-bridge; common mode voltage; carrier phase shift modulation; electrical insulation; dead time; fault condition

1. Introduction

Recently, renewable energy sources (RESs), e.g., photovoltaic and wind power, with a rising penetration in the modern power grid, have attracted more attention and been exploited widely due to their renewable and environmentally friendly nature relative to traditional fossil fuel energy. Distributed generations and micro-grids are regarded as promising directions and technologies for the reasonable development and utilization of RESs [1,2]. Moreover, with the concept of ‘Energy Internet’ proposed [3], RESs and related technologies are expected to be more widely applied.
However, as the fundamental elements in the legacy grid, traditional line-frequency transformers are not well suited for the exploitation and utilization of RESs. Therefore, a multifunctional grid interface or energy router is required for the Energy Internet.
Electronic power transformers (EPTs) [4,5], also called solid state transformers (SSTs) or power electronic transformers (PETs) [6,7], has been investigated in recent years and identified as an emerging intelligent electronic device to meet the aforementioned requirements for the future smart grid or Energy Internet [8,9]. Unlike a line-frequency transformer, an EPT is generally composed of power electronic converters and medium frequency transformers (MFTs) [10]. Therefore, the controllability and multi-object operation can be implemented flexibly such as active power transmission and voltage level conversion, fast and continuous on-load voltage regulation [11], reactive power compensation and current harmonics suppression, fault current limitation, interface to RESs, and so on.
When an EPT is connected to a high or medium voltage power grid, e.g., a 10 kV distribution system, due to the limit of blocking the voltage rating of insulated gate bipolar transistors (IGBTs) or other switching devices, a series-input/cascaded structure has been the most reasonable and popular choice for EPTs [5,6,12], e.g., the 10 kV cascaded H-bridge EPT (CHB-EPT) industrial prototype presented in the literature [5].
It is well known that pulse width modulation (PWM) converters always generate common mode voltage (CMV) [13,14], also called zero-sequence voltage. Especially, a high common mode d v / d t will be generated at a switching instant, when the converter operates at a high switching frequency, which would bring many problems to converter devices, both internal and external. For instance [15,16,17]:
  • Due to the long power cables connecting to the grid or motors, the traveling high-rise-rate CMV wave reflected by the terminals of cables will further result in overvoltage for terminal devices and cause bearing currents that reduce the life of the motors.
  • High d v / d t may cause leakage currents through the parasitic capacitances, which also damage the insulation of elements in the devices, e.g., power cables; in addition, it also creates electromagnetic interference problems, which will interfere with the control systems of devices.
Since an EPT is composed of cascaded H-bridges on the high-voltage side, the aforementioned CMV phenomenon and problems will exist as well and would be more serious and complex, which directly affects the insulation performance and safety operation of the EPT.
For the CMV in traditional two-level PWM converters or grid-connected photovoltaic inverters, since the generation mechanism and analysis are relatively simple, much literature deals with it by improving PWM strategy and employing common mode filters or improved topologies [18,19,20,21]. As for the analysis and reduction of the CMV in cascaded converters, due to the significant damage to the insulation and bearing current of motors, much of the literature and research focuses on medium-voltage adjustable speed drive (MV-ASD) systems. The literature [13] analyses systematically the CMV in the MV-ASD and establishes a common mode equivalent circuit, then suppresses the CMV by means of an improved modulation scheme. In the literature [22], the characteristics and paths of common mode current (CMI) in cascaded-multilevel-inverter-based photovoltaic system are analyzed, and suppression filters are designed. As for EPTs, related analysis of the CMV in the previously mentioned literature cannot be applied to them directly, due to their different topologies and control strategies. So far, few papers discuss the CMV or CMI in EPTs. The literature [23,24] presents the CMV and CMI phenomenon in the SST with a solidly grounded neutral point on the high-voltage side and designs common mode chokes to suppress the CMI based on the CMI equivalent circuit. However, the generation mechanisms and distribution characteristics of the CMV in the EPT have not been discussed analytically in the literature. In addition, other factors, e.g., dead time and grid fault condition, are not considered as well.
In this paper, the analysis of the generation mechanism and the characteristics of the CMV in the CHB-EPT, for both the under balanced and fault grid conditions, are presented, based on the simplified circuit model of CHB-EPT and the corresponding PWM strategy, which can provide theoretical guidance for the insulation design and power density optimization of cascaded converters. The analysis method is also applicable for other cascaded converters, e.g., CHB-STATCOM and CHB-inverters.
Section 2 introduces the CHB-EPT system considered in this paper and establishes its equivalent simplified circuit model on the high-voltage side. Section 3 gives the analytical calculation of the CMV in the EPT using the Fourier series analysis method. In Section 4, the results of the analytical calculations are verified by a simulation in MATLAB.

2. Description of the CMV in a CHB-EPT

In this section, the configuration of the considered CHB-EPT system and its internal CMV are introduced.

2.1. CHB-EPT System

Figure 1 shows a distribution system configured with a 10 kV/400 V EPT and the topology of the CHB-EPT considered in this paper, which is designed in a modular fashion and consists of single-phase sub-units that include high-voltage power cells (HVPCs), medium frequency transformers (MFTs), and low-voltage power cells (LVPCs) [5]. Since MFTs provide galvanic isolation and voltage conversion [10], the main circuit also can be divided into high-voltage and low-voltage sides. At the high-voltage side, h back-to-back H-bridges are cascaded to sustain a high grid phase voltage and three phases are Y-connection with a floating neutral point. Unipolar double frequency sinusoidal pulse width modulation (SPWM) and carrier phase shift (CPS) modulation technology [25] are adopted in the H-bridge rectifier; then 2h f s kHz equivalent switching frequency can be obtained when the IGBTs work at f s kHz switching frequency. Note that the voltage reference G in Figure 1b, constructed by three 10 kV potential transformers (PTs), is meant to offer a reference ground for CMV in this paper. These descriptions form the basis for the subsequent analysis of CMV.

2.2. The CMV at the High-Voltage Side in the EPT System

This paper mainly focusses on the CMV problem at the high-voltage side of EPT. Although the CMV appears at the low-voltage side as well, it is not significant relative to the high-voltage side in terms of insulation design. In addition, due to the isolation stage embedded MFTs, which block the mutual transmission and influence of the CMVs on both sides, the CMV at the low-voltage side will not be considered in this paper.
At the high-voltage side, the CHB rectifier connects to the MV grid directly. Especially when a long connecting power cable is employed, the CMV problem will be more complicated and worse due to voltage reflection phenomena and cable to ground capacitance, which will result in overvoltage, even resonance [16,17]. Obviously, higher insulation design requirements should be taken into account in EPT devices. In view of this, the analysis of the CMV at the high-voltage side will be presented in the following.

2.2.1. Voltages Generated by the HVPC

Figure 2a shows the circuit of a high-voltage power cell (HVPC). Each HVPC consists of a high-voltage rectifier and a front-end voltage source converter (VSC) in the isolation stage. Note that the dc-link midpoint (marked with o) between the upper and lower capacitors in Figure 2 is virtual, just to facilitate the definition and calculation of related voltages generated in the HVPC.
Referring to the left VSC H-bridge in Figure 2a, the input differential mode voltage v a a is defined as the difference between the two PWM voltages across each phase input terminal, a and a , to the dc-link midpoint o, which can be expressed as:
v a a = v a o v a o
where v a o and v a o are determined by the PWM strategy and the dc-link voltage. Figure 3 illustrates the operating principle of the unipolar SPWM modulation strategy employed by the left H-bridge in Figure 2a, where v S A and − v S A are the reference sinusoidal waves for the left and right H-bridge arms respectively and v r is triangular carrier.
Figure 2b shows the equivalent circuit model (ECM) of a single HVPC, in which the voltage potential of the midpoint with respect to ground can reflect the variation of voltages in HVPC. Due to the bipolar modulation strategy generally employed by the back-end H-bridge [5], we have:
v T c m = v T 1 + v T 2 2 = 0
where v T c m represents the CMV with respect to the midpoint for MFT primary windings. If neglecting the voltage sources v T 1 and v T 2 , the equivalent voltage model for CMV analysis can be further simplified, as is shown in Figure 2b.

2.2.2. The CMV at Neutral Point

Referring to the modeling methods and equivalent circuits in [13,22,23], a simplified three-phase equivalent circuit for the high-voltage side of the EPT illustrated in Figure 1b is exhibited in Figure 4. Note that the grid is converted equivalently to a star-connected voltage source for the analysis and calculation of CMV.
In Figure 4, each phase stack has h ECMs of HVPC in series, and three-phase stacks are symmetric with a common unearthed neutral point N. It should be noted that the relevant parasitic capacitances in each HVPC are not drawn in Figure 4 to highlight the generation mechanism and characteristics of the CMV.
The CMV between point N and ground is defined as v c m , shown in Figure 4. Considering that the MV grid, i.e., the 10 kV distribution system, often operates without grounding (e.g., a distribution system in Figure 1a), even in the case of the occurrence of a single-phase earth fault, the EPT will continue to operate for the line-to-line voltages continue to be balanced as well and the relay protection of the grid would not trip to make an outage immediately. Whether on the normal or single-phase to ground fault condition, the control strategy for the operating of EPT is not affected. However, the corresponding voltages between point N and ground are different.
  • Normal grid: For the three-phase balanced power grid, the voltage between the virtual grid neutral g (see the location in Figure 4) and ground can be assumed as zero so the neutral point of the grid can be chosen as the reference ground directly; then we have v c m = v N g .
  • Single-phase to ground fault: The voltage between the neutral point g of the grid and ground will shift up to phase voltage when a single-phase to ground fault occurs. For a balanced EPT, the CMV at neutral point N with respect to ground will be shifted synchronously. Then we have:
    v c m = v N g + v g - g r o u n d
    where v g g r o u n d is the voltage between the neutral point of the grid in Figure 4 and ground.
In addition, other types of grid faults will not be considered because they are not within the normal operating range of the EPT.

2.2.3. Voltages with Respect to Ground in HVPCs

Taking phase A for example, from Figure 4, it can be seen that the voltage between O x L (L = 1, 2… h) and N can be expressed as:
v A o N L = v A L B + i = 1 L 1 v a a i
where L is the sequence number of the corresponding HVPC. Then the voltage v A o g L with respect to ground in HVPC L can be obtained from:
v A o g L = v A o N L + v c m
As seen from Figure 4 and Equationss (4) and (5), the voltage at each midpoint o in the corresponding HVPC will change following the variation of the switching transitions in its lower HVPCs , i.e., the equivalent voltage sources v T and v B . Thus, the voltage potential at each HVPC not only contains a DM component but also contains the CM component, i.e., the CMV at the neutral point.

3. Analytical Calculation of Voltages in EPT

3.1. Principle and Method to Calculate Voltages in EPT System

In this section, an analytical method for calculating the CMV at neutral points and the voltage potential of HVPCs in an EPT system is proposed. The proposed analytical procedure is described as follows:
(1)
Calculate the CMV at neutral point N with respect to ground, i.e., v c m .
(2)
Calculate the voltage between O x L and N, that is:
v x o N L = v x o N L 1 + v x ( L 1 ) T + v x L B
where x = {A, B, C}, L = 1, 2… h.
(3)
Finally, obtain the voltage potential with respect to ground v A o g L in HVPC L based on Equation (5).

3.2. Derivation and Calculation of the CMV at Neutral Point and Voltage Potential of HVPCs

3.2.1. The CMV with Respect to Ground at a Neutral Point

For the input stage of the EPT, there are following relationships:
e A N v A N = R L S i A + L s d i A d t
e B N v B N = R L S i B + L s d i B d t
e C N v C N = R L S i C + L s d i C d t
where R L S and L S are the per phase equivalent resistance and inductance of the input boost inductor; v A N , v B N , and v C N are the high-voltage side converter pole voltages with respect to point N (note that the number of levels of the pole voltages will be up to 2h + 1 when the modulation ratio M is close to 1, where h is the number of HVPCs); e A N , e B N , e C N and i A , i B , i C are the grid voltages and currents, respectively. In addition, the grid voltages under normal conditions can be expressed as:
e x N = e x g v c m
where x = {A, B, C}. Summing Equations (7) to (9), we have:
( e A N + e B N + e C N ) ( v A N + v B N + v C N ) = ( R L S + L s d d t ) ( i A + i B + i C )
Under the balanced utility grid conditions, e A g + e B g + e C g = 0 and i A + i B + i C 0 , substituting (10) into (11), we obtain:
v c m = 1 3 ( v A N + v B N + v C N )
Taking phase A, for example, the reference sinusoidal wave v S A can be expressed as:
v S A ( t ) = M cos ( ω s t + φ s )
where M is the modulation ratio of the CHB rectifier in the input stage of EPT and ω s and φ s are the frequency and initial phase of the modulation waveform, respectively. Since h HVPCs are cascaded and a unipolar CPS-SPWM strategy with a particular phase-shift angle of π / h based on a natural-sampling method is employed using a similar Fourier series analysis method to that in [25,26], the output voltages of the front-end H-bridge in Figure 2a and Figure 3 can be obtained as follows:
v a o L = V d c 2 M cos ( ω s t + φ s ) + 2 V d c π   m = 1 n = 1 m J n ( M m π 2 ) sin [ ( m + n ) π 2 ] c o s [ m ( ω c t + φ L ) + n ( ω s t + φ s ) ]
v a o L = V d c 2 M cos ( ω s t + φ s ) + 2 V d c π   m = 1 n = 1 m J n ( M m π 2 ) sin [ ( m + n ) π 2 ] c o s [ m ( ω c t + φ L ) + n ( ω s t + φ s + π ) ]
where ω c and φ c are the angular frequency and initial phase of the carrier; φ L = φ c + π h ( L 1 ) ; L = 1, 2… h; and, hereinafter assuming that φ s = φ c = 0 for simplicity, which will not introduce error for the calculation results, V d c is the dc-link voltage of the H-bridges and J n ( ) is the n-order Bessel function, with the expression J n ( x ) = m = 1 ( 1 ) m x n + 2 m 2 n + 2 m m ! ( n + m ) ! . Note that the dead time is not considered in this section for simplicity.
Then, the voltage between the two input terminals of the front-end H-bridge can be given by:
v a a L = v a o L v a o L = M V d c cos ( ω s t + φ s ) + 2 V d c π   m = 1 n = J 2 n 1 ( M m π ) m cos [ ( m + n 1 ) π ] c o s [ 2 m ( ω c t + φ L ) + ( 2 n 1 ) ω s t ]   .
Finally, the phase A stack output voltage can be given by:
v A N = L = 1 h v a a L = h M V d c cos ω s t + 2 V d c π m = 1 n = J 2 n 1 ( h m M π ) m cos [ ( h m + n 1 ) π ] cos [ 2 h m ω c t + ( 2 n 1 ) ω s t ]   .
Similarly, for phases B and C, the corresponding expression can be obtained by replacing φ s with φ s 2 3 π , respectively. Substituting three phase output voltage expressions into (12), we have:
v c m = 2 V d c π m = 1 n = J 6 n 3 ( h m M π ) m cos [ ( m + 3 n 2 ) π ] cos [ 2 h m ( ω c t + φ c ) + ( 6 n 3 ) ω s t ]
When single-phase to ground fault occurs, e.g., phase C to ground fault, according to Equation (3), Equation (18) should be rewritten as:
v c m = e C N 2 V d c π m = 1 n = J 6 n 3 ( h m M π ) m cos [ ( m + 3 n 2 ) π ] cos [ 2 h m ( ω c t + φ c ) + ( 6 n 3 ) ω s t ]

3.2.2. The Voltage with Respect to N at Point o x L

Still taking phase A for example, for H-bridge L in Figure 2 and Figure 4, the voltages between the input terminals with respect to the dc-link midpoint O x L have been derived in Equations (14) and (15). Define the right second term of Equations (15) as function H (L), in which the variable is L.
Therefore, the voltage v A o N 1 between the midpoint O A 1 and the neutral point N of the HVPC located at the bottom of the phase A stack can be given by:
v A o N 1 = v A 1 B = v a o 1 = V d c 2 M cos ω s t + v A o N h 1
where v A o N h 1 = H ( 1 ) . Similarly, the voltage v A o N 2 of the second HVPC can be obtained as follows:
v A o N 2 = v A 2 B + v a a 1 = 3 V d c 2 M cos ω s t + v A o N h 2
where v A o N h 2 is:
v A o N 2 = 2 V d c π m = 1 n = J 2 n 1 ( M m π ) m cos [ ( m + n 1 ) π ] c o s [ 2 m ( ω c t + φ L ) + ( 2 n 1 ) ω s t ] + H ( 2 )
The other voltages between the midpoints and N, i.e., v A o N 3 , …, v A o N h , have the same structure.

3.2.3. Voltage Potential of HVPCs

According to Equations (5) and (18), the CMV with respect to ground at point O x L on the balanced utility grid condition can be written as:
v A o g L = 2 L 1 2 M cos ω s t + v A o g h L
where v A o g h L = v A o N h L + v c m , L = 1, 2… h.
Similarly, for phase B and C, by replacing φ s with φ s 2 3 π , the corresponding expression can be obtained.
In the case of the occurrence of a single-phase earth fault, Equation (23) just needs to have the corresponding fault phase-voltage subtracted.

3.3. Analysis of the Voltages

The analysis of the above mathematical expressions will be presented in this section.

3.3.1. Analysis of the CMV with Respect to Ground at Neutral Point

From Equation (18), the significant feature is that the fundamental frequency component does not appear in v c m . As for the harmonics component, the groups of sideband harmonics arrange around the even multiples of the equivalent carrier h ω c , the angular frequency and amplitude value of which are 2 m h ω c ± ( 6 n 3 ) ω s and 2 V d c π J 6 n 3 ( h m M π ) m (m = 1, 2, 3…, n = 0, ±1, ±2…), respectively. Obviously, the amplitude of harmonics depends on the modulation ratio and the harmonics order. Note that the amplitude here does not necessarily decrease with an increase in the harmonics order, and the sideband harmonics also do not decrease symmetrically, which can be seen from the following analysis.
Assuming that h, f s , and V d c are 6 kHz, 1 kHz, and 1500 V, respectively, some analysis results can be obtained as follows:
(1)
The relationship between the amplitude of the CMV harmonics component and the modulation ratio M
Equation (18) shows that the lowest harmonic group corresponds to m = 1, and the variable x of an n-order Bessel Function is x = h m M π = 6 M π . Then the n-order Bessel Function curves can be plotted as in Figure 5.
As shown in Figure 5, when m = 1, the modulation ratio M changes from 0 to 1, the corresponding order of the maximum amplitude harmonic is varied. For example, when M is 0.9, the order of the maximum amplitude harmonic is 240 ± 15 .
(2)
The relationship between the amplitude of CMV harmonics and its order
Figure 6 shows the relationship between the amplitude of CMV harmonics and its order, where M is set as 0.9. It can be seen that the amplitude here does not necessarily decrease with an increase in the harmonics order. This point should be considered as especially involved in suppressing the CMIs in the EPT.

3.3.2. Analysis of the Voltage with Respect to Ground at Midpoint o x L

From (23), it can be found that the expression of the voltage with respect to ground at the midpoint o x L , contains the fundamental frequency component, and its amplitude increases with the characteristics of an arithmetic series. As for the harmonics component, it can be divided into two parts; one part is the high-order harmonics generated at the neutral point N, the other part is generated by the corresponding H-bridge due to using a unipolar double frequency modulation strategy.
It should be noted that the fundamental component appearing in Equation (23) is an effective component in the output voltage generated by the cascaded H-bridges; in other words, it cannot be eliminated by means of improving the PWM strategies.
When the values of the dc-link voltage and the modulation ratio M in HVPCs are 1500 V and 1, respectively, the amplitudes of the fundamental component of the voltage potential of HVPC 1 to 6 are 750 V, 2250 V, 3750 V, 5250 V, 6750 V, and 8250 V, respectively. It can be seen that the amplitude of the fundamental component of the voltage potential in the top HVPC will reach 8250 V, which is much higher than its dc-link voltage of 1500 V and also higher than the amplitude of the grid phase voltage, which is 8165 V. Furthermore, the voltage potential at the upper input terminal of the MFT primary windings connected with the top HVPC should add on 750 V ( V d c / 2 ); then it can even reach 9000 V. Especially when the single-phase to ground fault of an input grid occurs, the value will be higher, which results a huge threat to the insulation of HVPCs and MFTs in the EPT.

3.4. Effects of SPWM Dead Time on the CMV

The effects of SPWM dead time on the CMV are not considered in the above analysis and results for the sake of simplifying the calculation and highlighting the distribution characteristics of the CMV. It should be pointed out that, in practice, the dead time T d , e.g., a few microseconds, generally must be inserted into the switching signals of the IGBTS or other switching devices to prevent a short circuit. Hence, in this section, the impact of SPWM dead time on the CMV in the EPT will be discussed and analyzed.
The practical output voltage of phase A stack v A N * can be divided into two parts; an ideal part, i.e., the output voltage expressed in Equation (17) without dead time, and a correction part caused by dead time. Equation (17) can be rewritten as:
v A N * = L = 1 h v a a L = L = 1 h ( v a a L + v e r r _ a a L )
where v e r r _ a a L is the error voltage caused by the dead time. The total error voltage v e r r _ A of the phase A stack can be obtained by employing the DFIA method in [25].
v e r r _ A = L = 1 h v e r r _ a a L = L = 1 h [ v e r r _ a L v e r r _ a L ]      =   2 h n = 1 [ A 0 , n cos ( n ( ω s t + φ s ) ) + B 0 , n sin ( n ( ω s t + φ s ) ) ]      + m = 1 n = { 2 A m , n L = 1 h cos [ 2 m ( ω c t + φ L ) + ( 2 n 1 ) ω s t ] + 2 B m , n L = 1 h sin [ 2 m ( ω c t + φ L ) + ( 2 n 1 ) ω s t ] }      =   2 h n = 1 [ A 0 , n cos ( n ( ω s t + φ s ) ) + B 0 , n sin ( n ( ω s t + φ s ) ) ]      + m = 1 n = { 2 A m , n cos [ 2 h m ω c t + ( 2 n 1 ) ω s t ] + 2 B m , n sin [ 2 h m ω c t + ( 2 n 1 ) ω s t ] }
where A m , n and B m , n are the Fourier coefficients [25]. Similarly, for phases B and C, the corresponding expression can be obtained by replacing φ s with φ s 2 3 π . Then, the total CMV at point N, considered dead time, can be given by:
v c m * = 1 3 ( v A N * + v B N * + v C N * ) = v c m 1 3 ( v e r r _ A + v e r r _ B + v e r r _ C ) = v c m 2 h n = 1 [ A 0 , 3 n cos ( 3 n ( ω s t + φ s ) ) + B 0 , 3 n sin ( 3 n ( ω s t + φ s ) ) ] m = 1 n = { 2 A m , n cos [ 2 h m ω c t + ( 6 n 3 ) ω s t ] + 2 B m , n sin [ 2 h m ω c t + ( 6 n 3 ) ω s t ] } .
From Equations (18) and (26), it can be seen that the dead time does not bring a fundamental component to the CMV at the neutral point N. However, it will affect the harmonics component. The analysis in the case of the occurrence of a single-phase earth fault is similar to Equation (19).

4. Simulation Results

To display the waveforms and characteristics of the CMV directly and illustrate the correctness of the analysis presented in Section 3, simulations have been carried out in MATLAB/SIMULINK.
A model of three-phase 10 kV/400 V 1 MVA EPT with the same structure as shown in Figure 1b, which consists of six HVPCs and six LVPCs per phase, is built. The main parameters are given in Table 1.
In addition, SPWM natural sampling is employed in the simulation, and the SPWM dead time is set as 4 μ s . The modulation ratio M is close to 0.9 in the simulation.
Figure 7 shows the waveform of the phase A stack output voltage with 13 levels, and it was calculated in Equation (17).
Figure 8 shows the waveforms of the CMV between the neutral point N and reference ground with or without the dead time of 4 μ s inserted into the switching signals. As can be seen, both CMVs have almost the same waveforms and harmonic performance. The absolute maximum instantaneous values in both waveforms can reach up to 1000 V. The ordinate value at the right side of Figure 8 is the magnitude of the 50 Hz fundamental component and harmonic voltages. According to the conclusion in Section 3.3.1, the harmonic group should appear around 2 m h ω c , where m = 1, 2, 3…, h = 6, ω c / ω s = 20, i.e., 240th, 480th, 720th …, which is consistent with the fast Fourier transformation (FFT) analysis results on the right side of Figure 8. More agreement relations between the proposed mathematical model and the simulation results can be obtained for further analysis. In addition, there are significant differences between the low-order harmonics appearing in Figure 8a,b, i.e., the low-order harmonics have a higher magnitude in latter compared with those in the former, which is consistent with the discussion in Section 3.4 and with the results when SPWM dead time is considered. Thus, the accuracy of the aforementioned model can be proved.
Figure 9 exhibits a comparison of the magnitude values of CMV harmonics between the theoretical calculation and simulation results, where the theoretical values are obtained from Equation (18) and the simulation results are obtained directly by employing the FFT tool in MATLAB/SIMULINK. From the comparison in Figure 9, it can be found that the maximum error value between the theoretical and the simulation results is 8.67%, appearing at 507th harmonic, and the minimum error is lower than 0.39%, appearing at 225th harmonic. Although the relative errors of the high-order harmonics are slightly larger, their absolute amplitudes are lower. Therefore, the difference between the two results is very small, which also verifies the validity of the proposed CMV mathematical model.
Figure 10 shows the CMV at a neutral point (in Figure 4) and the voltage potential with respect to ground of the cascaded HVPCs at the high-voltage side in phase A under balanced grid voltage conditions and single-phase to ground fault in phase C, respectively. From 0.06 s to 0.10 s, the EPT is operating under normal grid conditions. It can be clearly seen from the figure that the characteristics of the voltages are consistent with the analysis in Section 3.2.3 and Section 3.3.2, e.g., the top HVPC in Figure 1b has to sustain the highest voltage potential with respect to ground, reaching up to 9000 V. At 0.10 s, a single-phase to ground fault occurs in phase C of the 10 kV grid. Since the line-to-line voltages of 10 kV also maintain the balance in this fault, the EPT continues to operate to provide high quality electricity for the loads in the secondary side. However, the voltages in Figure 10 change abruptly at 0.10 s, i.e., each voltage is injected with the voltage of phase C of the power grid, which results in a significant increase of the voltage potential with respect to ground of each HVPC. In the worst case, the RMS of the voltage potential of the top HVPC is close to the line-voltage of the grid. This brings a great challenge to the insulation design of the HVPC and MFT. All of the aforementioned analysis can offer a theoretical basis for insulation design.

5. Conclusions

This paper has investigated the generated mechanism of the CMV in a CHB-EPT, presented the characteristics of the CMV by using an analytical calculation method, and validated them with simulation results. The main analysis results can be concluded as follows:
  • The CMV at the neutral point N under normal and balanced grid voltage conditions mainly consists of high-order harmonics with relatively high d v / d t voltage stress for the high-voltage side of the EPT. The EPT has to sustain a higher fundamental component of the CMV, i.e., the voltage of the fault phase, when it operates under a fault grid condition (single-phase to ground fault).
  • The voltage potential at each equivalent midpoint of the HVPC with respect to ground, not only includes the high-order harmonics components, but also contains the line-frequency fundamental component. Furthermore, the magnitude of the latter will increase with an increase of the sequence number of the HVPC. Obviously, the highest electrical stress will appear in the top HVPC, which provides a theoretical guide for the structural design and further power density optimization of the EPT.
  • SPWM dead time has little effect on the magnitude of the CMV. In addition, it will not bring a fundamental component to the CMV at the neutral point.
In conclusion, through the analysis of the CMV in the EPT, a theoretical guide can be put forward for insulation design and power density optimization. In addition, the proposed analysis method can also be applied to other cascaded converters, e.g., CHB-STATCOM and CHB-inverters.

Acknowledgments

This work was supported by the National Key R & D Program of China (2017YFB0903604) and the China Postdoctoral Science Foundation (No. 2017M612457).

Author Contributions

The paper was a collaborative effort of the authors. Yun Yang contributed to the analytical calculation and simulations and wrote this paper. Chengxiong Mao and Dan Wang conceived the idea and supervised the research. Jie Tian and Ming Yang performed the analysis of the results and revised the manuscript.

Conflicts of Interest

The authors declare no conflicts of interest.

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Figure 1. Schematic diagram of (a) an Electronic power transformer (EPT)-based distribution system; and (b) a 10 kV/400 V cascaded H-bridge EPT (CHB-EPT).
Figure 1. Schematic diagram of (a) an Electronic power transformer (EPT)-based distribution system; and (b) a 10 kV/400 V cascaded H-bridge EPT (CHB-EPT).
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Figure 2. (a) The topology of a high-voltage power cells (HVPC); (b) Equivalent circuit model of HVPC for common mode voltage (CMV) analysis.
Figure 2. (a) The topology of a high-voltage power cells (HVPC); (b) Equivalent circuit model of HVPC for common mode voltage (CMV) analysis.
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Figure 3. Unipolar sinusoidal pulse width modulation (SPWM) modulation strategy for an H-bridge.
Figure 3. Unipolar sinusoidal pulse width modulation (SPWM) modulation strategy for an H-bridge.
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Figure 4. Equivalent circuit for common mode voltage analysis in three-phase CHB-EPT.
Figure 4. Equivalent circuit for common mode voltage analysis in three-phase CHB-EPT.
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Figure 5. The relationship between Bessel | J n ( x ) | and modulation M.
Figure 5. The relationship between Bessel | J n ( x ) | and modulation M.
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Figure 6. Relationship between the amplitude of CMV harmonics and its order.
Figure 6. Relationship between the amplitude of CMV harmonics and its order.
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Figure 7. Phase A stack output voltage.
Figure 7. Phase A stack output voltage.
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Figure 8. The waveforms and corresponding the fast Fourier transformation (FFT) analysis of the CMV between N and reference ground: (a) without SPWM dead time; (b) with SPWM dead time.
Figure 8. The waveforms and corresponding the fast Fourier transformation (FFT) analysis of the CMV between N and reference ground: (a) without SPWM dead time; (b) with SPWM dead time.
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Figure 9. A comparison of magnitude values of CMV harmonics in the theoretical calculation and the simulation results.
Figure 9. A comparison of magnitude values of CMV harmonics in the theoretical calculation and the simulation results.
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Figure 10. Simulation results: Related voltages under normal and fault conditions. (a) The CMV at a neutral point; (b) the voltage potential between the midpoints of the HVPCs and ground (From top to bottom: v A o g 6 , v A o g 3 , and v A o g 1 ).
Figure 10. Simulation results: Related voltages under normal and fault conditions. (a) The CMV at a neutral point; (b) the voltage potential between the midpoints of the HVPCs and ground (From top to bottom: v A o g 6 , v A o g 3 , and v A o g 1 ).
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Table 1. Main parameters of the 10 kV/400 V 1MVA EPT.
Table 1. Main parameters of the 10 kV/400 V 1MVA EPT.
ParameterValue
Number of cascaded H-bridges 6 per phase
Number of paralleled H-bridges6 per phase
Rated high voltage dc-link1500 V
Rated low voltage dc-link360 V
Capacitance in one high-voltage dc-link 2200 μ F
Capacitance in one low-voltage dc-link56 mF
Inductance of rectifier30 mH
Filter inductance of the inverter0.2 mH
Filter capacitance of the inverter250 μ F
Rated ratio of the MFIT4.17:1
Switching frequency at high-voltage side1 kHz
Switching frequency at low-voltage side4 kHz
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