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Sensors 2017, 17(4), 694; doi:10.3390/s17040694

Automated Software Acceleration in Programmable Logic for an Efficient NFFT Algorithm Implementation: A Case Study

1
Department of Industrial Engineering, Universidad de La Laguna, 38203 San Cristóbal de La Laguna, Spain
2
Department of Computer Engineering and Systems, Universidad de La Laguna, 38203 San Cristóbal de La Laguna, Spain
*
Author to whom correspondence should be addressed.
Academic Editor: Gonzalo Pajares Martinsanz
Received: 29 January 2017 / Revised: 20 March 2017 / Accepted: 21 March 2017 / Published: 28 March 2017
(This article belongs to the Special Issue State-of-the-Art Sensors Technology in Spain 2016)
View Full-Text   |   Download PDF [1748 KB, uploaded 28 March 2017]   |  

Abstract

Non-equispaced Fast Fourier transform (NFFT) is a very important algorithm in several technological and scientific areas such as synthetic aperture radar, computational photography, medical imaging, telecommunications, seismic analysis and so on. However, its computation complexity is high. In this paper, we describe an efficient NFFT implementation with a hardware coprocessor using an All-Programmable System-on-Chip (APSoC). This is a hybrid device that employs an Advanced RISC Machine (ARM) as Processing System with Programmable Logic for high-performance digital signal processing through parallelism and pipeline techniques. The algorithm has been coded in C language with pragma directives to optimize the architecture of the system. We have used the very novel Software Develop System-on-Chip (SDSoC) evelopment tool that simplifies the interface and partitioning between hardware and software. This provides shorter development cycles and iterative improvements by exploring several architectures of the global system. The computational results shows that hardware acceleration significantly outperformed the software based implementation. View Full-Text
Keywords: NFFT; SDSoC; software acceleration; Zynq; parallelism techniques NFFT; SDSoC; software acceleration; Zynq; parallelism techniques
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Rodríguez, M.; Magdaleno, E.; Pérez, F.; García, C. Automated Software Acceleration in Programmable Logic for an Efficient NFFT Algorithm Implementation: A Case Study. Sensors 2017, 17, 694.

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