The 90° symmetry cross-shaped Hall plate (see Figure 3) is most widely used because of its high sensitivity and immunity to alignment tolerances resulting from the fabrication process. Its fabrication technology is fully compatible with the standard CMOS process. As shown in Figure 3(a), the active area of the cross-shaped Hall plate is usually realized by a weakly doped N-well diffusion region. The N-well is isolated from the P-type substrate by the reverse-biased well/substrate p-n junction. A shallow heavily doped top P+ layer often covers the surface of active area to decrease the flicker noise and the surface losses. It is normally formed to create the source and drain regions of PMOS transistors [9]. In addition, four contact regions are highly N+ doped to reduce the contact resistances in the source and drain formation processing step for NMOS transistors. Based on the basic model topology shown in Figure 2, a new simplified 8-resistance model for the CMOS integrated cross-shaped Hall plate is developed, as shown in Figure 4. Compared with Dimitropoulos’ model, the simulation model is improved by replacing the JFETs by N-well body resistances and depletion capacitances. The four depletion capacitances are added into the model to simulate the transient behavior of the Hall plate. Besides, there are four controlled voltage sources V_H/2 to model the Hall voltage. Each Hall voltage source V_H/2 is controlled by the electrical current flowing through the nearer contact.

In order to determine the resistance values of R_H and R_D in our model, a new and simple computation method is proposed in contrast to the FEM simulation method [7]. It is well known that it is best to measure the N-well sheet resistance R_s according to the Van-der-Pauw method. Although the Van-der-Pauw method requires that the contacts of Hall device be point-like, it has been reported that cross-shaped Hall plate with a finger length to width ratio larger than 1:1 can give an accurate R_s value with an error of less than 0.1% [10]. Usually, the required ratio of finger length to width can be fulfilled for achieving a high current related sensitivity. Thus, in the case of symmetric Hall plates, the sheet resistance can be determined by measuring the resistance value R_AB,CD in term of Van-der-Pauw method [11]: (3) R A B , C D = ln 2 π R swhere R_AB,CD = V_CD / I_AB presents the voltage difference between contacts C and D dividing the current flowing from contact A to contact B. The contacts of A, B, C and D are shown in Figure 3(a).

On the other hand, according to the structure of the model illustrated in Figure 4, the resistance R_AB,CD is calculated by: (4) R A B , C D = R H 4 2 R D − R H 2 R D + R H

The internal resistance between two diagonal contacts is given by: (5) 2 R D R H 2 R D + R H = ( 2 L W + 2 3 ) R s

Here, (2L/W+2/3) is the effective square number of the N-well resistance. L and W are the finger length and finger width of cross-shaped Hall plate, respectively. The center square number is approximately reduced to 2/3 as the two fingers for sensing Hall signal are placed in parallel. Considering the Equations (3), (4) and (5), finally we can obtain: (6) R H = 2 R s π [ ( 2 L W + 2 3 ) π − 2 ln 2 ] (7) R H R D = 2 − 8 π ln 2 2 L / W + 2 / 3

The N-well sheet resistance R_s is calculated by: (8) R s = 1 q μ n N D , N W t e f f

Here, N_D,NW is the N-well doping concentration, t_eff is the effective depth of Hall plate. As shown in Figure 3(b), it is equal to: (9) t e f f = t N W − t P + − w N W , S U B − w N W , P +where t_NW is the depth of N-well implantation region, t_P+ is the thickness of the top P+ layer, w_NW,SUB is the bottom depletion region situated in between N-well and P-type substrate, w_NW,P+ is the upper depletion region situated in between N-well and top P+ layer.

Note that there are two main parasitic capacitances distributed across the Hall device body: (1) the reverse-biased upper depletion capacitance between the top P+ layer and N-well; (2) the reverse-biased bottom depletion capacitance between the N-well and p-type substrate. Usually the top P+ layer and P-type substrate are applied to ground together, thus they are connected in parallel physically. Unfortunately, the parasitic capacitances may limit the switching frequency for the spinning current offset reduction method. In order to simulate the complete ac behavior of the Hall plate, these parasitic depletion capacitances should be included in the model. Assuming the one-sided abrupt junctions, each depletion capacitance per unit area is calculated by following Equation (5): (10) C p n = q ε s i · N D , N W N A 2 ( N D , N W + N A ) [ V b i − U p n − 2 K T q ] − 1 / 2

Here, V_bi is the built in potential of PN junction, N_D,NW is the doping of N-well, and N_A is the doping of top P+ layer or P-type substrate.

When a magnetic field B is orthogonally applied on a device plane and two diagonal contacts are biased with a current I, the Hall effect takes place. Then the hall voltage V_H appears on two additional contacts, it is equal to: (11) V H = S I I Bwhere S_I is the current related sensitivity. It depends on device geometry (geometrical correction factor G and Hall plate effective thick t_eff) and technology parameters (N-well doping N_D,NW and Hall r_H) [12]. It is defined as: (12) S I G r H q N D , N W t e f f

When Hall plate is biased with a voltage source V, the Hall voltage is expressed by voltage related sensitivity S_V: (13) V H = S V V Bwhere S_V = μ_HG / N_square · μ_H = r_Hμ_n, it is the Hall mobility, μ_n is the electron mobility, and N_square is the equivalent square number of N-well diffusion resistance between two diagonal contacts.

The impact of the Hall devices geometry on Hall voltage is modeled by a geometrical correction factor. For a cross-shaped Hall plate, it can be calculated by using a conformal mapping [12]: (14) G = 1 − 5.0267 θ H tan ( θ H ) e − π 2 W + 2 L Wwhere θ_n = tan⁻¹(μ_HB), it is defined as the Hall angle. If W / 2L ≤ 0.39, G has an accuracy better than 0.5% [12].

In our model illustrated in Figure 4, each Hall voltage V_H/2 is modeled by using the current-controlled voltage sources with the following equation: (15) V H / 2 = 1 2 S I I ( n 1 , n 2 ) Bwith I(n₁, n₂) being current flowing between the contacts n₁ and n₂.

It is well known that the thickness of depletion region is obviously changed by the reverse biased PN junction. Therefore, both sheet resistance and magnetic sensitivity suffer from a strong voltage non-linearity dependence. Since the doping concentration of the P+ top layer is obviously higher than that of the P-type substrate, the thickness variation of the upper depletion region modulated by reverse biased voltage can be approximately ignored. Using Equation (8), which is extended by the voltage dependent t_eff, and a Taylor expansion results up to second order are given by [5]: (16) R s ( U p n ) = 1 q μ n N D , N W ( t e f f * − k 1 V b i ) + 1 2 k 1 V b i q μ n N D , N W ( t e f f * − k 1 V b i ) 2 V b i U p n + − 1 8 k 1 V b i ( t e f f * − k 1 V b i ) V b i 2 + 1 4 k 1 ( t e f f * − k 1 V b i ) 2 V b i q μ n N D , N W ( t e f f * − k 1 V b i ) U p n 2 = R s ( 0 V ) · ( 1 + B B R 1 · U p n + B B R 2 · U p n 2 )where R_s(0V) is the zero-biased N-well sheet resistance, BBR₁ and BBR₂ are the first and second voltage dependency of resistance coefficients, respectively. k 1 = 2 ɛ s i q ⋅ N A , S U B ( N A , S U B + N D , N W ) N D , N W, and t e f f * = t N W − t P + − w N , P + ( 0 V ). Here, w_N,P+ (0V) is the upper depletion region with zero-bias.

With the same calculation method, the current related sensitivity is modeled by: (17) S I ( U p n ) = S I ( 1 + B B S 1 · U p n + B B S 2 · U p n 2 )where BBS₁ and BBS₂ denote the first and second voltage dependent coefficients of sensitivity, respectively.

We know that the temperature drift has serious effects on the equivalent N-well resistance, sensitivities and offset of the Hall device. The temperature behavior of N-well sheet resistance can be well approximated by the second order polynomial: (18) R s ( U p n , T ) = R s ( U p n , 300 K ) · [ 1 + R T C 1 · ( T − 300 K ) + R T C   2 · ( T − 300 K ) 2 ]where R_TC1 and R_TC2 are temperature coefficients of N-well resistance. These parameters can be directly obtained from foundry technological files. R_S(U_pn,300K) is the sheet resistance at the room temperature.

Since the thermal expansion of silicon is merely 2.6 ppm/°K and the G and t_eff are considered as temperature independent, the thermal drift efficient of current related sensitivity can be given by [12,13]: (19) α S I = 1 S I d S I d T = α r H − α Nwhere, α_rH and α_N are the temperature coefficient of the Hall factor and the carrier concentration of N-well, respectively. For a N-well doping of 4 × 10¹⁶ cm⁻³, α_rH increases from 0 to 500 ppm/°K in a industrial temperature range (240 K–400 K) [12]. With a lower doping of N-well, α_rH is almost independent of N-well doping and the temperature, showing an approximately 700 ppm/°K constant value [12]. On the contrary, α_N decreases from 500 ppm/°K to 50 ppm/°K for the N-well doping of 4 × 10¹⁶ cm⁻³ in the same temperature range [13]. As a result, α_N could just right compensate α_rH at the room temperature, and zero temperature coefficient of sensitivity could be obtained. Considering the temperature dependency of α_rH and α_N, the drift of the current related sensitivity is about in the range of ±500 ppm/°K throughout the industrial temperature range. For the other doping values of N-well, α_rH and α_N can be obtained by referring to relevant data. Thus, considering this thermal drift effect of the sensitivity, Equation (20) can be rewritten as: (20) S I ( T , U p n ) = S I ( U p n ) [ 1 + α S I · ( T − 300 K ) ]

When a Hall plate is assembled, its performance is deteriorated by two physical stress-related effects, i.e., piezo-resistance and piezo-Hall effects. The piezo-resistance effect due to packaging stress provokes relative variations of N-well resistances. In combination with technology variation, junction field effects and temperature drift, it is the main source of offset. The sensitivity is also impacted by packaging stress. The variation of sensitivity is called piezo-Hall effect. Considering this effect, Equation (20) can be rewritten as [14,15]: (21) S I ( σ , T , U p n ) = S I ( T , U p n ) [ 1 + P 12 · ( σ x + σ y ) ]where σ_x and σ_y are the mechanical stress in the plane parallel to the Hall plate surface, P₁₂ denotes the piezo-Hall coefficient tensors in x-y plane, which is estimated at 40 × 10⁻¹¹ Pa⁻¹ for the N-well (4 × 10¹⁶ cm⁻³) [12].

Since the mechanical stress changes with temperature, the temperature coefficient of sensitivity illustrated in Equation (19) can be rewritten as: (22) α S I = α r H − α N − α p i e z o − H a l l

For a plastic packaging, the temperature coefficient related to piezo-Hall effect can be defined by [13]: (23) α p i e z o − H a l l = − C 1 · P 12 · E p g · ( α p g − α s i l i c o n )where E_pg is the modulus of elasticity of molding compound, α_pg and α_silicon is the thermal expansion coefficients of molding-compound and silicon, C₁ is a designed-dependent geometric constant. For a typical plastic package such as TSSOP, we can get C₁ ≈ 6 [13], so the approximate α_piezo–Hall value of −450 ppm/°K can be estimated [12].