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An improved equivalent simulation model for a CMOS-integrated Hall plate is described in this paper. Compared with existing models, this model covers voltage dependent non-linear effects, geometrical effects, temperature effects and packaging stress influences, and only includes a small number of physical and technological parameters. In addition, the structure of this model is relatively simple, consisting of a passive network with eight non-linear resistances, four current-controlled voltage sources and four parasitic capacitances. The model has been written in Verilog-A hardware description language and it performed successfully in a Cadence Spectre simulator. The model’s simulation results are in good agreement with the classic experimental results reported in the literature.

Presently, CMOS integrated Hall magnetic sensors are widely used in many practical fields. Besides directly measuring the value of magnetic field, they are usually used to indirectly measure position, distance, speed, rotational angle or an electric current [

Several compact simulation models of Hall elements have been put forward. Previously reported 4-resistance Wheatstone bridge models don’t fully take into account correlative physical and geometrical effects such as non-linear conductivity, junction effect, temperature drift, frequency-response, noise behavior and device shape-dependent sensitivity [

In this paper, an accurate 8-resistance simulation model for a cross-shaped CMOS-integrated Hall plate is developed. To be conveniently used by circuit designers, this model is improved by replacing the JFETs with passive non-linear resistances and depletion capacitances. It takes into account voltage dependent non-linear effects, geometrical effects, temperature effects, and packaging stress influence,

To be compatible with the spinning current techniques for reducing Hall offset [

If the fourth contact is applied to the reference ground, the Z-matrix of the 90° symmetry Hall plate is only decided by three parameters _{11}, _{12}, _{13}. If the input current _{1} is applied to the first contact, the three measuring potentials shown in _{1} – _{2} = _{3}, and then we can obtain _{11} – _{12} = _{13}. As a result, 90° symmetry Hall plates require at least two types of resistances to model their electrical properties. Thus, an 8-resistance model topology for the 90° symmetry Hall plate is suggested, which is illustrated in

However, in the conventional 4-resistance Wheatstone bridge model [_{D}

The 90° symmetry cross-shaped Hall plate (see _{H/2} to model the Hall voltage. Each Hall voltage source _{H/2} is controlled by the electrical current flowing through the nearer contact.

In order to determine the resistance values of _{H}_{D}_{s}_{s}_{AB,CD}_{AB,CD}_{CD}_{AB}

On the other hand, according to the structure of the model illustrated in _{AB,CD}

The internal resistance between two diagonal contacts is given by:

Here, (2

The N-well sheet resistance _{s}

Here, _{D,NW}_{eff}_{NW}_{P+}_{NW,SUB}_{NW,P+}

Note that there are two main parasitic capacitances distributed across the Hall device body: (1) the reverse-biased upper depletion capacitance between the top P+ layer and N-well; (2) the reverse-biased bottom depletion capacitance between the N-well and p-type substrate. Usually the top P+ layer and P-type substrate are applied to ground together, thus they are connected in parallel physically. Unfortunately, the parasitic capacitances may limit the switching frequency for the spinning current offset reduction method. In order to simulate the complete ac behavior of the Hall plate, these parasitic depletion capacitances should be included in the model. Assuming the one-sided abrupt junctions, each depletion capacitance per unit area is calculated by following

Here, _{bi}_{D,NW}_{A}

When a magnetic field _{H}_{I}_{eff}_{D,NW}_{H}

When Hall plate is biased with a voltage source _{V}_{V}_{H}G_{square}_{H}_{H}μ_{n}_{n}_{square}

The impact of the Hall devices geometry on Hall voltage is modeled by a geometrical correction factor. For a cross-shaped Hall plate, it can be calculated by using a conformal mapping [_{n}^{−1}(_{H}B

In our model illustrated in _{H/2} is modeled by using the current-controlled voltage sources with the following equation:
_{1}, _{2}) being current flowing between the contacts _{1} and _{2}.

It is well known that the thickness of depletion region is obviously changed by the reverse biased PN junction. Therefore, both sheet resistance and magnetic sensitivity suffer from a strong voltage non-linearity dependence. Since the doping concentration of the P+ top layer is obviously higher than that of the P-type substrate, the thickness variation of the upper depletion region modulated by reverse biased voltage can be approximately ignored. Using _{eff}_{s}_{1} and _{2} are the first and second voltage dependency of resistance coefficients, respectively.
_{N,P+} (0

With the same calculation method, the current related sensitivity is modeled by:
_{1} and _{2} denote the first and second voltage dependent coefficients of sensitivity, respectively.

We know that the temperature drift has serious effects on the equivalent N-well resistance, sensitivities and offset of the Hall device. The temperature behavior of N-well sheet resistance can be well approximated by the second order polynomial:
_{TC1} and _{TC2} are temperature coefficients of N-well resistance. These parameters can be directly obtained from foundry technological files. _{S}(U_{pn},300K)

Since the thermal expansion of silicon is merely 2.6 ppm/°K and the G and _{eff}_{rH}_{N}^{16} cm^{−3}, _{rH}_{rH}_{N}^{16} cm^{−3} in the same temperature range [_{N}_{rH}_{rH}_{N}_{rH}_{N}

When a Hall plate is assembled, its performance is deteriorated by two physical stress-related effects, _{x}_{y}_{12} denotes the piezo-Hall coefficient tensors in x-y plane, which is estimated at 40 × 10^{−11} Pa^{−1} for the N-well (4 × 10^{16} cm^{−3}) [

Since the mechanical stress changes with temperature, the temperature coefficient of sensitivity illustrated in

For a plastic packaging, the temperature coefficient related to piezo-Hall effect can be defined by [_{pg}_{pg}_{silicon}_{1} is a designed-dependent geometric constant. For a typical plastic package such as TSSOP, we can get _{1} ≈ 6 [_{piezo–Hall}

The new simulation model code has been written in behavioral Verilog-A language and was tested on a Cadence Spectre simulator tool using AMS 0.8 μm CMOS technological parameters (shown in

To show the correctness and accuracy of this model, the corresponding experimental results of the Hall plate fabricated using the same technology given in the literature [_{x} = σ_{y}= −70 MPa for a typical plastic packaging [

The measured and simulated relative variations of the current-related sensitivity related to the value at room temperature as a function of temperature for the zero-stress mounting of the Hall plate is demonstrated in _{SI}_{SI}_{I}_{I}

Finally, the ac simulation of the Hall plate was performed at 3 V DC bias. The ratio of finger length to finger width is fixed to 1, while the finger length is taken as a parameter, changing from 40 μm to 120 μm with a step of 40 μm. The simulation results in

An equivalent circuit simulation model for a CMOS-integrated Hall plate has been improved. The structure of the model consists of a passive network, including eight non-linear resistances, four depletion capacitances and four current-controlled voltage sources. The model completely takes into account the non-linear conductivity effects, geometrical effects and temperature effects. Meanwhile, the packaging stress influence on Hall plates is also considered to a certain degree. In addition, the model only needs a small number of key physical and technological parameters. The model has been implemented in Verilog-A hardware description language and was successfully tested with the standard EDA tool Cadence. For testing the model correctness and accuracy, the model simulation of a Hall plate were performed using AMS 0.8 μm CMOS technology parameters and are compared with the measured results reported in the literature [

This work was supported by China Jiangsu Science and Technology Support Project (NO.BE2009143).

Diagram of measuring Z-matrix for a 90° symmetry Hall plate.

An equivalent model topology for the 90° symmetry Hall plate.

Cross-shaped Hall plate fabricated in standard CMOS technology. (

A simplified model for the CMOS integrated cross-shaped Hall plate.

Comparisons between the measurements and the model simulation for the output Hall voltage with 1 mA biasing.

Comparisons between the measurements and the model simulation for the sheet resistance of N-well dependence of input voltage.

Comparisons between the measurements and the model simulation for the relative variation of the current-related sensitivity as a function of temperature.

Ac simulation gain

Model parameters (using AMS 0.8 μm CMOS process) [

Parameters Definition Default value |

_{D,NW}^{16} cm^{−3} |

_{A,P+}^{20}cm^{−3} |

_{A,SUB}^{16}cm^{−3} |

_{NW} |

_{P+} |

_{n}^{2}/V.s |

_{H}^{2}/V.s |

_{TC1} |

_{TC1} |

_{12}^{−11} Pa^{−1} |

_{SI}_{I} |

_{piezo-Hall} |