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Proceedings 2017, 1(4), 598; doi:10.3390/proceedings1040598

Thermal Noise Limited, Scalable Multi-Piezoresistor Readout Architecture

1
Institute of Technical Physics and Materials Science, Centre for Energy Research, HAS, H-1121 Budapest, Hungary
2
Doctoral School on Material Sciences and Technologies, Óbuda University, H-1034 Budapest, Hungary
Presented at the Eurosensors 2017 Conference, Paris, France, 3–6 September 2017.
*
Author to whom correspondence should be addressed.
Published: 11 August 2017
(This article belongs to the Proceedings of Eurosensors 2017)
Download PDF [866 KB, uploaded 11 October 2017]

Abstract

In this work we present a low noise, hardware efficient, and scalable read-out architecture for piezoresistive mechanical transducers containing multiple sensing elements. To reach the thermal noise limit the sensing elements are driven by modulated, differential stimuli at separated frequencies, their current are summed and digitalized for signal processing and response extraction. The solution decreases the complexity of the analog read-out electronics and makes it easily scalable. Besides the improved signal-to-noise ratio the principle can achieve minimised power consumption and self-heating of piezoresistors with minimal analogue hardware resources. The distinguishing features of the arrangement are the multiple frequency modulation, the current based multiple sensor integration, one AD converter, no analog multiplexing, and the need for only a half Wheatstone bridge per sensing element.
Keywords: low noise; thermal noise limit; lock-in readout; piezoresistive sensor; AC modulation low noise; thermal noise limit; lock-in readout; piezoresistive sensor; AC modulation
This is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. (CC BY 4.0).

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MDPI and ACS Style

Radó, J.; Battistig, G.; Pap, A.E.; Fürjes, P.; Földesy, P. Thermal Noise Limited, Scalable Multi-Piezoresistor Readout Architecture. Proceedings 2017, 1, 598.

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