Multi-Rate Parallel Real-Time Simulation Method for Doubly Fed Wind Power Systems Based on FPGA–CPU

Abstract

A multi-rate parallel real-time simulation method based on FPGA–CPU is studied to realize the asynchronous co-simulation of the converter of doubly fed wind power systems with the wind turbine and external power grid. The doubly fed wind power system is partitioned by simulation step length, and the partitioned small-step-length data are processed using integral homogenization. For large-step data, an improved delay-compensated linear interpolation method combined with Newton interpolation is proposed for processing. The general small time-step (GST) model method is used to implement the FPGA modeling of the small-step converter, and resource optimization is achieved through timing time-division multiplexing. Asynchronous parallel co-simulation of a doubly fed wind power system is implemented on an FPGA–CPU co-simulation platform. Among them, the FPGA realizes the development of the converter HDL with a small step of 1 $\mathsf{\mu }\mathrm{s}$, while the CPU completes the simulation of the wind turbine and power grid synchronously with a large step of 50 $\mathsf{\mu }\mathrm{s}$. Finally, by comparing with MATLAB/Simulink offline simulation and analyzing the error, it is concluded that the simulation accuracy of the improved method in this paper is higher than that of the un-interpolated parallel simulation, which verifies the real-time performance and accuracy of the modeling and improved method in this paper.

1. Introduction

As one of the main methods of wind power generation, the transient real-time simulation technology of the doubly fed wind power system has gradually become the research focus of scholars in various countries [1,2]. Compared with the traditional offline simulation, the real-time simulation can reflect the operation mechanism of the model more accurately, better reflect the dynamic characteristics of the model, and make it closer to the actual situation of system operation [3]. Therefore, it is necessary to deeply understand the grid-connected characteristics and transient characteristics of wind power systems through efficient and accurate real-time simulation [4,5,6].

As an emerging and rapidly developing modern digital simulation technology, the digital twin has been widely used in industrial manufacturing [7,8]. Based on the digital simulation platform, this technology builds a mapping relationship between the real space and the virtual space and achieves the purpose of manipulating the actual equipment or system through the state feedback of the virtual space [9,10,11]. However, the scale of power systems is much larger, and the control systems are more complex than those of industrial manufacturing, so digital twin technology has not yet been fully implemented in power systems [12]. In addition, digital twins are mostly implemented based on machine learning (ML) [13,14], and ML involves complex algorithms, which adds an extra burden to the already complex doubly fed wind power system. Therefore, the use of real-time simulators for major simulation tasks remains a necessary task under current technology.

At present, commercial real-time simulation machines represented by RTDS, RT-LAB and HYPERSIM have been widely used in the fields of control of doubly fed wind power systems [15], modeling of photovoltaic power plants [16], and model partitioning of power systems [17]. These simulators represent the CPU-based development of real-time simulation models, limited by the serial simulation structure of the CPU, and the simulation step length of such processors can only reach tens of microseconds in most cases [18]. However, the typical power electronic converter switching frequency has been as high as 10~200 kHz [19], and the development of high-frequency converter technology has brought great challenges to the real-time simulation of power electronics. To reduce the simulation step, RTDS and RT-LAB have introduced field-programmable gate arrays (FPGAs) as peripheral devices to undertake the simulation of high-frequency power electronics devices [20]. Compared to commercial simulators, FPGA has a fully configurable parallel hardware structure, distributed memory structure and pipeline structure [21]. The highly parallel numerical computation enables FPGA to perform microsecond and even nanosecond simulations. In addition, FPGA has the advantages of small size, low price, rich I/O interfaces, and short development cycle, and it has gradually become one of the main devices for real-time simulation [22].

However, for large systems containing high-frequency power electronics, if the whole system is simulated in small steps, the simulation scale will be severely limited [23]. Therefore, multi-rate co-simulation with multiple processors has gradually become the trend in real-time simulation platforms [24,25]. Ref. [26] proposed a multi-FPGA real-time simulation architecture, using multiple FPGAs as parallel computing units for real-time simulation, which effectively increases the simulation resources and reduces the simulation step size. Ref. [27] combines the advantages of the strong computational power of FPGA and the flexibility of RTDS and uses FPGA as the external expansion device of RTDS to realize the parallel real-time simulation of FPGA-RTDS. In multi-rate co-simulation, the interactive processing of parallel data is particularly important. The authors of [28] proposed a real-time simulation method based on a CPU-FPGA heterogeneous platform, which allocates different simulation tasks to different processors and greatly reduces the simulation burden of a single processor. However, this method directly takes the result of the last simulation step on the opposite side as the input during the simulation process, without further considering the timing error during the multi-rate decoupled parallel simulation. In [29], the authors proposed a multi-rate real-time simulation method based on Norton equivalence. The data interaction between asynchronous length systems is realized by linear extrapolation, and the multi-rate parallel simulation of FPGA-RTDS is achieved. However, the method does not consider the compensation of the predicted data on both sides, and there is a certain simulation error. In [30], the authors used an improved linear interpolation algorithm combined with Lagrange interpolation to achieve parallel interaction of asynchronous long data, which greatly improved the simulation accuracy based on the literature [29]. Unfortunately, the method did not process small-step data, and the Lagrange interpolation algorithm is computationally intensive and tends to occupy a large number of FPGA resources.

Based on the above research theories, this paper takes a doubly fed wind power system as an example and divides the system into two simulation subsystems with different step lengths based on the continuous–discrete model separation (CDMS) method. To reduce the simulation error, the partitioned small-step data are processed using integral average, and on this basis, an improved linear interpolation algorithm combined with Newton interpolation is used to realize the parallel interaction of the asynchronous step-length data. The general small time-step (GST) model is used to model the back-to-back converters in the doubly fed wind power system, and the model is optimized based on the time-sharing multiplexing principle. The asynchronous parallel real-time simulation of the whole doubly fed wind power system is performed by the FPGA–CPU platform. In particular, the hardware description language (HDL) of the converter is developed on the FPGA in small steps of 1 $\mathsf{\mu }\mathrm{s}$, and the 50 $\mathsf{\mu }\mathrm{s}$ simulation of the wind turbine and the external power grid is performed simultaneously in the CPU. By comparing with MATLAB/Simulink offline simulation results and analyzing the simulation errors, the real-time capability and accuracy of the modeling and improved methods in this paper are verified.

The remainder of this paper is organized as follows. Section 2 introduces the basic structure of the doubly fed wind power system. Section 3 performs model partitioning of the doubly fed wind power system and completes parallel processing of asynchronous length data on this basis. Section 4 implements the FPGA modeling of the back-to-back converter and the optimization of its hardware resources. Section 5 completes the FPGA–CPU asynchronous parallel real-time simulation and compares and analyzes the simulation results. Section 6 concludes the paper.

2. Basic Structure of Doubly Fed Wind Power System

As shown in Figure 1, The doubly fed wind power system consists of four parts: the turbine, the power grid, the back-to-back converter, and the control system. The turbine drives the rotor of the induction motor through a gearbox, and the rotor side is connected to the grid through a back-to-back converter, while the stator side is directly connected to the grid.

In the figure, parameters $u_{ref\_g}$ and $u_{ref\_r}$ represent the modulating voltages from the control system on the grid side and rotor side, respectively, and PWM1 and PWM2 are the trigger pulses of the converter on the grid side and rotor side. To understand the basic structure of the system in more detail, the back-to-back converter is listed separately. As shown in Figure 2, it consists of three sets of insulated-gate bipolar transistors (IGBTs) that are completely symmetrical about the DC bus capacitance. In this case, the modulating waves on both sides are compared with the high-frequency carrier waveform to generate three pulse signals, $g_{(1,3,5)}$ and ${g^{\prime }}_{(1,3,5)}$, respectively. Considering the trigger pulses of the upper and lower bridge arms of each group of converters as ideal complementary PWM waves, the control signals of the whole back-to-back converters can be obtained by inverting the three-way signals by bit. In the figure, C indicates the DC bus capacitor, $g_1$ indicates the trigger pulse of the upper bridge arm of the first converter, and $g_6$ indicates the trigger pulse of the lower bridge arm of the second converter.

In a doubly fed wind power system, the higher trigger pulse frequency of the converter requires a small simulation step, while the other parts can be run with larger step sizes. Therefore, a multi-rate co-simulation method can be used to simulate the whole system, i.e., different simulation steps for different time constants of the simulation subsystem [31].

3. Multi-Rate Parallel Simulation of Doubly Fed Wind Power System

Due to the difference in simulation performance, in this paper, the simulation step for the back-to-back converter part is set to $\Delta t$, while the other parts are simulated with a large step of $\Delta T$, $\Delta T$ is an integer multiple of $\Delta t$.

3.1. Multi-Rate Parallel Decoupling of Doubly Fed Wind Power System

For different step simulation systems, realizing multi-rate decoupled simulation of the system can reflect the high-frequency transient processes while effectively improving the simulation computational efficiency. A continuous–discrete model separation (CDMS) method is proposed in [32], as shown in Figure 3.

The main idea is to use an ideal current source to replace the discrete circuit model in the system, and then separate the switching devices from the whole system. The switching model $\mathrm{G}\left({\mathrm{V}}_{\mathrm{SW}}\right)$ is used to describe the voltage–current relationship of the switching device, and its calculated current $\mathrm{I}\left({\mathrm{V}}_{\mathrm{SW}}\right)$ is used as an input to the circuit model equation $\mathrm{F}({\mathrm{V}}_{\mathrm{SRC}},{\mathrm{I}}_{\mathrm{SRC}},{\mathrm{I}}_{\mathrm{SW}},\mathrm{X})$. $\mathrm{F}({\mathrm{V}}_{\mathrm{SRC}},{\mathrm{I}}_{\mathrm{SRC}},{\mathrm{I}}_{\mathrm{SW}},\mathrm{X})$ then calculates the voltage of the switching device and uses this voltage as the input to the equation $\mathrm{G}{\mathrm{V}}_{\mathrm{SW}}$.

In this paper, we improve the CDMS to decouple the doubly fed wind power system from the multi-rate simulation. As shown in Figure 4, the entire doubly fed wind power system is divided into two subsystems according to the simulation step, namely, the large-step turbine and power grid subsystem 1 and the small-step back-to-back converter and control module subsystem 2. The data interaction between the subsystem interfaces is achieved using controlled sources. In particular, the grid and rotor sides of the turbine receive the phase voltages from the back-to-back converter and use them as the control signal for the controlled voltage source on both sides. The back-to-back converter receives the three-phase currents from the grid side and rotor side and uses them as the control signals of the controlled current sources, thus realizing the decoupling of the whole system at different steps.

In the above decoupling process, the phase voltage data such as $v_{ab\_g}$ received by subsystem 1 will be discrete small-step PWM signals due to the influence of the PWM wave of the control module, while the current data such as $i_{abc\_g}$ received by subsystem 2 will be continuous large-step signals. Because of the difference in simulation steps, the simulation process will lead to delays in large-step data and loss of small-step data, which will seriously affect the simulation accuracy, so it is necessary to compensate for the simulation errors.

3.2. Parallel Processing of Data with Different Step Lengths

During real-time simulation, large- and small-step data need to be exchanged synchronously. However, the small-step data changes several times in a large-step cycle, and the data is passed out in the last small step before the large-step update. This results in the loss of many small-step data, which affects the simulation accuracy. In addition, the inherent delay in data transmission causes the data received on the large-step side to lag by one synchronous clock cycle, increasing the simulation error. Therefore, in this paper, the parallel data on the large- and small-step sides are processed for error compensation.

3.2.1. Small-Step PWM Equalization

Based on the principle of area equivalence, the data on the small-step sides are processed by integration averaging. The data output from subsystem 2 can all be considered as discrete small-step PWM signals of equal width and unequal amplitude, so the integration averaging process can be considered as an amplitude averaging process in combination with the time average method (TAM) [33].

$$\overline{v}=\frac{{\displaystyle {\int }_{t-\Delta T}^{t}v(t)dt}}{\Delta T}=\frac{{\displaystyle \sum _{i=1}^{\mathrm{n}}v(i)}}{\mathrm{n}}$$

(1)

where $\mathrm{n}=\Delta T/\Delta t$, $\mathrm{n}\in {\mathrm{N}}^{+}$, $v(i)$ is the small-step voltage output from the back-to-back converter, and $\overline{v}$ is its average value, as shown by the red dashed line in Figure 5.

Subsystem 2 sends $\overline{v}$ ahead of time, and subsystem 1 uses this value in the next large step for simulation. The above process is repeated in each $\Delta T$ thereafter to obtain the mean value of the small-step effect for subsystem 2, which indirectly reflects the current state of the small-step model. A series of equal-width and unequal-amplitude pulse data is obtained on the large-step side, thus enabling asynchronous data interaction.

3.2.2. Large-Step Prediction and Delay Compensation

Although the small-step PWM averaging can reflect the operation of the small-step model very well, it also brings a corresponding transmission delay.

As shown in Figure 6, in the real-time simulation, subsystem 1 samples and sends data at the beginning of each large-step cycle, which requires subsystem 2 to send out the small-step averages before the sampling point. Assuming that the data is sent in advance $T_{\mathrm{f}}$, generally speaking, $T_{\mathrm{f}}$ is larger than the simulation step $\Delta t$ of subsystem 2. As can be known from the previous subsection, the small-step averaging is performed in the last $\Delta t$ of each $\Delta T$, which makes the small-step averaging in the current cycle delayed by one $\Delta T$ before it is transmitted to the large-step subsystem, thus causing simulation errors.

To address the above errors, this paper uses the three-point interpolation method to predict and compensate for the large-step data.

$$i_{est}(t)=\frac{5}{4}i(t-\Delta T)+\frac{1}{2}i(t-2\Delta T)-\frac{3}{4}i(t-3\Delta T)$$

(2)

$$i_{est}(t+\Delta T)=\frac{5}{4}i(t)+\frac{1}{2}i(t-\Delta T)-\frac{3}{4}i(t-2\Delta T)$$

(3)

where $i_{est}(t)$, $i_{est}(t+\Delta T)$ are the predicted values of current at the present moment and the next moment, respectively. The three-point interpolation method has some errors in the prediction of data, and this paper uses error delay compensation to correct the prediction values. Since the current is a periodically varying sine wave, the prediction error also has the characteristic of periodically varying, so the prediction error of the current moment can be delayed by one present period to compensate for the prediction value of the next moment. Assuming that the initial value is zero, the current prediction correction value can be expressed as Equation (4) in the complex frequency domain.

$$i_{cor1}(z)=z{i}_{est}(z)+z^{-(\lambda -1)}(i(z)-i_{est}(z))$$

(4)

where $i_{cor1}(z)$ is the predicted correction value for the next moment, and $\lambda$ is the value of latency. In the case of back-to-back converters, the received data delay is influenced by the operating frequency of the system on the grid and rotor sides, as shown in Equation (5).

$$\lambda =\left\{\begin{array}{cc}\frac{1}{f\Delta T}& \hfill \mathrm{grid} \mathrm{side}\\ \frac{1}{sf\Delta T}\hfill & \hfill \mathrm{rotor} \mathrm{side}\end{array}\right.$$

(5)

where $f$ is the operating frequency of the grid side system, and $s$ is the slip ratio. After the large-step prediction and compensation, the data synchronization process between large and small steps can be realized. As expressed in Figure 6, the large-step data sent by subsystem 1 at the moment $t_2$ is the corrected value $i_{cor1}(t_2)$ at the Present moment. Subsystem 2 finishes receiving the corrected values at the moment $(t_2+T_{\mathrm{f}})$ and uses them for the small-step simulation between $(t_2+T_{\mathrm{f}}\sim t_4+T_{\mathrm{f}})$, and finishes the averaging process of the small steps in the last $\Delta t$ of this $\Delta T$. Subsystem 2 sends out the mean value ${\overline{v}}_3$ earlier at moment $t_5$, and subsystem 1 finishes receiving it at moment $t_6$. ${\overline{v}}_3$ is the result of $i_{cor1}(t_2)$’s participation in the small-step subsystem 2 simulation, i.e., the simultaneous interaction of data of different steps in the previous $\Delta T$ is achieved at moment $t_6$.

3.2.3. Small-Step Data Interpolation

The simulation accuracy of the system is greatly improved after the small-step averaging process, large-step prediction, and compensation operations. However, the small-step system receives the large-step data and holds it until the arrival of the next large-step data. This leads to the small-step module performing the same calculation several times, which wastes simulation resources and does not take advantage of the small-step simulation. In view of this, this paper uses the Newton interpolation method to correct the small-step data. Compared with other interpolation algorithms, Newton interpolation is less computationally intensive, easy to program and more suitable for real-time simulation [34]. The Newton interpolation polynomial is shown in Equation (6) [35].

$$f(x)=f(x_0)+f(x_0,x_1)(x-x_0)+f(x_0,x_1,x_2)(x-x_0)(x-x_1)+\cdot \cdot \cdot +f(x_0,x_1,\cdot \cdot \cdot ,x_n)(x-x_0)(x-x_1)\cdot \cdot \cdot (x-x_n)$$

(6)

where $f(x_0,\cdot \cdot \cdot ,x_n)$ is the nth order difference quotient of the function $f$. Since the small-step subsystem uses a fixed-step simulation, the Newtonian pre-interpolation formula for equidistant nodes can be used to interpolate the large-step data. Considering that the interpolated function has sinusoidal characteristics and the computational load of the real-time simulation should not be too large, a two-order polynomial is chosen to implement the interpolation. Before interpolation, it is also necessary to extend the known interval, and by combining Equations (3) and (4), it is obtained that:

$$i_{est}(t+2\Delta T)=\frac{5}{4}{i}_{cor}(t+\Delta T)+\frac{1}{2}i(t)-\frac{3}{4}i(t-\Delta T)$$

(7)

$$i_{cor2}(z)=z^2{i}_{est}(z)+z^{-(\lambda -2)}(i(z)-i_{est}(z))$$

(8)

In Equation (8), $i_{cor2}(z)$ is the predicted corrected value for the next two moments. From this, the two-order Newtonian pre-interpolation formula for large-step currents is obtained as:

$$i_2(t_1+\delta \Delta T)=i(t_1)+[i_{cor1}(t_1+\Delta T)-i(t_1)]\delta \Delta T+\frac{i_{cor2}(t_1+2\Delta T)-2i_{cor1}(t_1+\Delta T)-i(t_1)}{2!}\delta \Delta T(\delta \Delta T-1)$$

(9)

where $i_2(t_1+\delta \Delta T)$ denotes the multiple small-step current values obtained using quadratic Newton pre-interpolations after the $t_1$ moment.

$$\delta =(1+h\frac{\Delta t}{\Delta T})\hspace{1em}h=(1,2,\cdot \cdot \cdot ,\frac{\Delta T}{\Delta t})$$

(10)

The principle of small-step interpolation is shown in Figure 7.

The solid black line of subsystem 1 indicates the actual value of the large-step current, and the corrected values $i_{cor1}(t_2)$ and $i_{cor2}(t_2)$ at moments $(t_2+\Delta T)$ and $(t_2+2\Delta T)$ are obtained by three-point interpolation. The corrected values are advanced one sampling step for the interpolation condition, i.e., $i_{cor1}(t_2)$ is advanced to moment $t_2$ and $i_{cor2}(t_2)$ is advanced to moment $t_3$. Newton interpolation is performed on the interval $[t_2\sim t_3]$, and the interpolation results are applied to the simulation of the small-step subsystem. This enables the linearization of the large-step data and improves the simulation accuracy.

4. FPGA-Based Back-to-Back Converter Modeling and Hardware Resource Optimization

After parallel processing of the asynchronous data as described above, the system simulation tasks need to be distributed. In this paper, the small-step simulation of the back-to-back converter is implemented using FPGA, so the converter needs to be modeled for its HDL development. Since FPGA is highly parallel and has limited logic resources, the same parts of the converters can be simplified to save resources.

4.1. Common Switching Device Modeling Methods

At present, modeling methods for switching devices can be broadly classified into two types: mechanistic models and behavioral models [36]. The mechanistic model focuses on the internal transient characteristics of the switching device, while the behavioral model focuses on the external dynamic characteristics of the switching device. The latter is more suitable for FPGA real-time simulation. The behavioral models can be generally divided into three types: the average-value model method, the two-value conductance model method, and the switching function method [37].

The average-value model method averages one cycle of the switching device and replaces the actual value output with the average value. This modeling method does not take into account the high-frequency characteristics of the switching device and has low accuracy. The switching function method lists the basic equations of the simulation based on the physical characteristics of the switching device and the circuit topology. This method is more accurate, but the relationship between the system state variables needs to be known, and it is more difficult to model complex circuits. The two-value conductance method equates the on/off state of the switching device to a large/small resistance, respectively, which is simple to model and easy to implement. However, it wastes a lot of time and resources in updating and inverting the system matrix, and the method also causes the system equations to be pathological, resulting in numerical instability [38]. Therefore, some scholars have proposed the associated discrete circuit (ADC) method on this basis, which is to equate the on/off state of the switching device to small inductance/small capacitance, respectively. Using the numerical integration algorithm, the discretized branch circuit is equated to the parallel form of the conductor and the historical current source [39]. By calculating the parameters of each node, the overall transient simulation equation of the system is obtained.

$$\mathit{Gu}=\mathit{i}$$

(11)

where G is the conductance matrix, which is kept constant during the calculation, and u and i denote the voltage and current of each node, respectively. This method has a simple modeling idea and does not need to consider the operation state of the whole circuit, but the simulation accuracy is easily affected by the choice of parameters, and virtual power loss will be generated [18]. Based on this method, Ref. [40] proposes a fixed-admittance modeling method for power electronic converters using response-matching, that is, the general small time-step (GST) model method [41]. This method aims to eliminate transient errors and no longer relies on specific physical circuits and numerical integration methods, and can accurately simulate ideal switching characteristics through simple settings.

Table 1. Comparison of switching device modeling methods.

Modeling Method	Modeling Basis	Complexity	High-Frequency Characteristics	Simulation Accuracy	Generality
Average-value model	Periodic averages instead of actual values	Moderate	No	Low	Moderate
Switching function method	Circuit topology	Complex	Yes	High	Low
Two-value conductance method	On/off states are equivalent to different resistances	Simple	Yes	Low	High
Associated discrete circuit (ADC)	On/off state equivalent to inductor/capacitor	Moderate	Yes	Moderate	High
General small time-step (GST)	On/off state equivalent to on/off element	Simple	Yes	High	High

gives a comparison of the performance of various switching device modeling approaches.

In summary, to obtain better simulation accuracy and wider application scenarios, the GST model method is chosen for modeling, HDL development, resource optimization, and experimental verification of the back-to-back converters.

4.2. Modeling of Back-to-Back Converters

4.2.1. The GST Model

In the GST model based on response-matching, the on/off state of the switching device is no longer equated to a small inductor/small capacitor, but the on/off of the switching device is replaced by the closing/breaking element, respectively. The closing/breaking element is equated as a parallel form of conductor and historical current source, as shown in Figure 8.

To ensure the constant conductance characteristics of the model, the Dommel equivalent conductance when the switch is on and off should be equal, differing only in the historical current source, i.e., $Y_{\mathrm{sw}\_\mathrm{on}}=Y_{\mathrm{sw}\_\mathrm{off}}=Y_{\mathrm{sw}}$, which takes the following values:

$$\frac{\Delta t}{L_{\mathrm{f}}}\ll Y_{\mathrm{sw}}\ll \frac{C\mathrm{f}}{\Delta t}$$

(12)

where $L_{\mathrm{f}}$ and $C_{\mathrm{f}}$ denote the filter inductor and DC capacitance, respectively. Therefore, the relationship between the historical current source and the voltage and current of the previous step can be expressed as shown in Equation (13).

$$\left\{\begin{array}{l}{i}_{\mathrm{his}\_\mathrm{on}}(t)={\alpha }_{\mathrm{on}}{Y}_{\mathrm{sw}}u(t-\Delta t)+{\beta }_{\mathrm{on}}i(t-\Delta t)\\ i_{\mathrm{his}\_\mathrm{off}}(t)={\alpha }_{\mathrm{off}}{Y}_{\mathrm{sw}}u(t-\Delta t)+{\beta }_{\mathrm{off}}i(t-\Delta t)\end{array}\right.$$

(13)

In the modeling process, the voltage coefficient $\alpha$ and current coefficient $\beta$ are chosen as the optimal damping parameters for the fixed-admittance model of the two-level converter.

$$\left\{\begin{array}{l}{\alpha }_{\mathrm{on}}=-1+\sqrt{2}\hspace{1em}{\alpha }_{\mathrm{off}}=1\\ {\beta }_{\mathrm{on}}=-1\hspace{1em}\hspace{1em}\hspace{1em}{\beta }_{\mathrm{off}}=1+\sqrt{2}\end{array}\right.$$

(14)

4.2.2. Converters Modeling Based on GST Model

Based on the above GST model, the back-to-back converter in the doubly fed wind power system is modeled. The back-to-back converter consists of a DC bus capacitor and two groups of symmetrical IGBTs, and the GST model is used to replace each IGBT and DC capacitor to obtain the simulation topology shown in Figure 9.

In the figure, whether the historical current source is $i_{\mathrm{his}\_\mathrm{on}}$ or $i_{\mathrm{his}\_\mathrm{off}}$ will depend on whether the switching device is on or off, i.e., determined by the trigger pulse of the IGBT. Through the relationship between voltage and current, combined with Equations (11) and (13), the 13th-order iterative equation of the back-to-back converter can be obtained.

$$\left[\begin{array}{ccccc}{Y}_{\mathrm{sw}}E& 0& Y_{\mathrm{sw}}{Y}^{\mathrm{T}}& -E& 0\\ Y_{\mathrm{sw}}E& 0& 0& E& 0\\ 0& 0& Y_{\mathrm{c}}& Y& Y\\ 0& Y_{\mathrm{sw}}E& Y_{\mathrm{sw}}{Y}^{\mathrm{T}}& 0& -E\\ 0& Y_{\mathrm{sw}}E& 0& 0& E\end{array}\right]\left[\begin{array}{c}{V}_{\mathrm{g}}^{n+1}\\ V_{\mathrm{r}}^{n+1}\\ v_{\mathrm{dc}}^{n+1}\\ I_{\mathrm{g}}^{n+1}\\ I_{\mathrm{r}}^{n+1}\end{array}\right]=\left[\begin{array}{c}{I}_{\mathrm{his}\_\mathrm{hg}}\\ I_{\mathrm{his}\_\lg }\\ i_{\mathrm{his}\_\mathrm{c}}\\ I_{\mathrm{his}\_\mathrm{hr}}\\ I_{\mathrm{his}\_\mathrm{lr}}\end{array}\right]$$

(15)

where $E$ is the third-order unit matrix, $Y=\left[\begin{array}{ccc}-1& -1& -1\end{array}\right]$ is the coefficient matrix of the current; $Y_{\mathrm{c}}$ is the equivalent conductance of the DC capacitor after discretization by the trapezoidal integration method, $v_{\mathrm{dc}}^{n+1}$ and $i_{\mathrm{his}\_\mathrm{c}}$ are its voltage and historical current sources; $V_{\mathrm{g}}^{n+1}$ and $V_{\mathrm{r}}^{n+1}$ are the node voltages of the grid/rotor side of the back-to-back converter, $I_{\mathrm{g}}^{n+1}$ and $I_{\mathrm{r}}^{n+1}$ are the input currents of the upper bridge arm of the grid/rotor side; $I_{\mathrm{his}\_\mathrm{hg}}$ and $I_{\mathrm{his}\_\mathrm{hr}}$ are the historical current sources of the upper bridge arm of the grid/rotor side; and the expressions of the voltage and current matrices are shown in Equation (16).

$$\left\{\begin{array}{l}{V}_{\mathrm{g}}^{n+1}={\left[v_1^{n+1} v_2^{n+1} v_3^{n+1}\right]}^{\mathrm{T}} I_{\mathrm{g}}^{n+1}={\left[i_1^{n+1} i_2^{n+1} i_3^{n+1}\right]}^{\mathrm{T}}\\ V_{\mathrm{r}}^{n+1}={\left[v_4^{n+1} v_5^{n+1} v_6^{n+1}\right]}^{\mathrm{T}} I_{\mathrm{r}}^{n+1}={\left[i_4^{n+1} i_5^{n+1} i_6^{n+1}\right]}^{\mathrm{T}}\\ I_{\mathrm{his}\_\lg }=I_{\mathrm{abc}\_\mathrm{g}}+I_{\mathrm{his}\_\mathrm{dg}} I_{\mathrm{his}\_\mathrm{lr}}=I_{\mathrm{abc}\_\mathrm{r}}+I_{\mathrm{his}\_\mathrm{dr}}\end{array}\right.$$

(16)

where $v_k^{n+1}$ and $i_k^{n+1}$$(k=1\cdots 6)$ are the node voltages and upper bridge arm branch currents, $I_{\mathrm{abc}\_\mathrm{g}}$, $I_{\mathrm{abc}\_\mathrm{r}}$ are the three-phase input currents on the grid/rotor side, and $I_{\mathrm{his}\_\mathrm{dg}}$, $I_{\mathrm{his}\_\mathrm{dr}}$ are the historical current sources on the lower bridge arm on the both sides.

From Equation (15) to (16), it can be seen that the system conductance matrix remains constant during the modeling of the back-to-back converter using the GST model method. The modeling only requires the trigger signals of each switching device and the input currents on both sides. The trigger signal is used to control the change in the historical current source and is generated by the modulating waveform $u_{ref}$. This modeling method does not require knowing the logical relationship between the system state variables, and is simple and general, which is very suitable for HDL development on FPGA. In addition, according to the symmetry of the back-to-back converter, it can also be optimized for FPGA resources.

4.3. Optimization of FPGA Resources for Back-to-Back Converter

4.3.1. Model Optimization Basis

Since the mathematical models of the grid side and the rotor side of the back-to-back converter are the same, the two sides of the converter can be combined into one for modeling and simulation by time-sharing. Considering the clock periods of the large and small-step systems as $\Delta T$ and $\Delta t$, respectively, the asynchronous simulation timing of the model can be obtained as shown in Figure 10.

The system starts simulation at the moment $t_0$. The periods $t_0\sim t_1$ and $t_1\sim t_2$ are the operating intervals of the grid side and rotor side converters, respectively. When the grid side is working, the rotor side data is maintained as the simulation result of the previous step, and the same for the rotor side, and the length of the operating interval for each side converter is $\Delta t$. When the simulation time reaches $t_3$, the whole system completes a large-step simulation, and the two converters alternately perform $\mathrm{n}/2$ calculations, $\mathrm{n}=\Delta T/\Delta t$. The process is repeated in each subsequent large-step cycle, thus reducing the number of back-to-back converters by half for optimization purposes.

4.3.2. Resource Optimization of the Model

From Equation (15), it can be seen that the admittance matrix of the system has symmetry, and Equation (15) can be simplified to a seventh-order iterative equation based on the above optimization principle.

$$\left[\begin{array}{ccc}{Y}_{\mathrm{sw}}E& Y_{\mathrm{sw}}{Y}^{\mathrm{T}}& -E\\ Y_{\mathrm{sw}}E& 0& E\\ 0& Y_{\mathrm{c}}& Y\end{array}\right]\left[\begin{array}{c}{V}^{n+1}\\ v_{\mathrm{dc}}^{n+1}\\ I^{n+1}\end{array}\right]=\left[\begin{array}{c}{I}_{\mathrm{his}\_\mathrm{hgr}}\\ I_{\mathrm{his}\_\mathrm{lgr}}\\ i_{\mathrm{his}\_\mathrm{cd}}\end{array}\right]$$

(17)

where $V^{n+1}$, $I^{n+1}$ and $I_{\mathrm{his}\_\mathrm{lgr}}$ are results of alternating $V_{\mathrm{g}}^{n+1}$ and $V_{\mathrm{r}}^{n+1}$, $I_{\mathrm{g}}^{n+1}$ and $I_{\mathrm{r}}^{n+1}$, $I_{\mathrm{his}\_\lg }$ and $I_{\mathrm{his}\_\mathrm{lr}}$ in Equation (16) in time sequence, respectively, and $I_{\mathrm{his}\_\mathrm{hgr}}$ is the result of alternating $I_{\mathrm{his}\_\mathrm{hg}}$ and $I_{\mathrm{his}\_\mathrm{hr}}$ in Equation (15). $i_{\mathrm{his}\_\mathrm{cd}}$ is the sum of the upper bridge arm branch current on the working side within the previous $\Delta t$ and the DC capacitor history currents. The expression is shown in Equation (18).

$$i_{\mathrm{his}\_\mathrm{cd}}=i_{\mathrm{his}\_\mathrm{c}}+i_{1(4)}^{n+1}+i_{2(5)}^{n+1}+i_{3(6)}^{n+1}$$

(18)

where $i_{1(4)}^{n+1}$ denotes the branch current of bridge arm 1 or the branch current of bridge arm 4, the value of which is selected by the alternate timing.

The block diagram of hardware resource optimization for the back-to-back converter can be obtained as shown in Figure 11, where the inputs are currents and pulse modulated voltages on the grid/rotor side, respectively. Subsystem 1 obtains corrected data such as $u_{ref\_gcor}$ by predicting and compensating for the large-step data. Subsystem 2 performs Newton interpolation on the corrected data to obtain small-step data such as $u_{ref\_gN}$. The multiplexer realizes the time-sharing input of data, and the data on both sides are time-sharing multiplexed with a PWM generator and simplified converter model. The output value of the converter is used as the history term parameter of the model after delay. The data distributor distributes the data such as $v^{n+1}$ to the grid side and rotor side in time order, and the node voltages on both sides are passed through the subtractor to obtain the phase voltages of each phase. The output phase voltages $v_{ab\_g}$, $v_{bc\_g}$, $v_{ab\_r}$, $v_{bc\_r}$ and the DC capacitor voltage $v_{dc}$ are transformed from small to large step by small-step integral averaging process and participate in the simulation of subsystem 1 with a step size of $\Delta T$. As a result, the number of converters and PWM generators is reduced by half, which reduces the consumption of FPGA resources. In addition, the model built by the non-interpolated GST model can also be optimized for FPGA resources in the same way, and the optimized model is used for simulation in this paper.

5. Experimental Verification

5.1. Construction of Experimental Platform

Based on the converter model built using the GST method and the hardware resource optimization theory of FPGA, this paper selects HDL for 1 $\mathsf{\mu }\mathrm{s}$ FPGA development of subsystem 1 and completes 50 $\mathsf{\mu }\mathrm{s}$ simulation of subsystem 2 using CPU synchronously. FPGA is Kintex-7 series xc7k325t from Xilinx, package type and pin count is ffg676, speed level is −2, and hitched with two Ethernet communication network ports. The board input clock is selected to be 50 MHz, and the 100 MHz simulation main clock is generated through a phase-locked loop (PLL). The simulation CPU is the Universal Real-time Experimental Platform (UREP) independently developed by our group, which has the capability of real-time digital simulation and semi-physical simulation of the full electromagnetic transient state of 10,000-node level grid-scale and 1 million kilowatt-level level new energy and energy storage equipment. The system composition of the experimental platform is shown in Figure 12.

Among them, the PC implements the generation of the hardware description language of the back-to-back converter and the initialization of the UREP model. The UREP and the FPGA realize the data transfer in large and small steps via Ethernet. In addition, the PC monitors in real time the signals to be observed for the system in the UREP. The FPGA–UREP simulation physical platform is shown in Figure 13.

5.2. FPGA–UREP Asynchronous Parallel Co-Simulation

Since FPGA and UREP co-simulation requires high real-time performance, UDP (User Datagram Protocol), which is connectionless-oriented and has a fast transmission rate, is chosen as the asynchronous communication protocol in this paper. The flow chart for UDP sending data is shown in Figure 14. The actual data sent is UDP data, as shown in the light red box in the flow chart. The process of receiving data is basically the same as sending, the difference is that the receiving process adds a data bit counter, which is not repeated here.

The block diagram of FPGA and UREP asynchronous co-simulation is shown in Figure 15.

After both UREP and FPGA are started, UREP first sends an ARP (Address Resolution Protocol) request to the FPGA. The FPGA makes an ARP reply and links to UREP, The UREP first sends an ARP request to the FPGA, and the FPGA makes an ARP reply and links to the UREP, subsequently establishing communication between the two. The UREP runs subsystem 1 in 50 $\mathsf{\mu }\mathrm{s}$ steps and sends out the data obtained from the operation, such as $u_{ref\_g}$, through the UDP sending module. The FPGA data receiving/sending chip PHY (Port Physical Layer) receives data from the UREP through the UDP receiving module and writes these data into the asynchronous FIFO1 at the PHY operating frequency (125 MHz). When the data is received, all the data in FIFO1 is read out at the same time using the main frequency operation (100 MHz) of FPGA to ensure the synchronization of data. The readout data is assigned to the back-to-back converter as input and run in subsystem 2 with a 1 $\mathsf{\mu }\mathrm{s}$ step. When the simulation counter reaches 45 $\mathsf{\mu }\mathrm{s}$, the FPGA writes the $v_{dc}$ and other small-step data obtained from the run to the asynchronous FIFO2 one by one at its main frequency. The UREP receives data from the FPGA while sending out other data at the next 50 $\mathsf{\mu }\mathrm{s}$, and uses the received data for the simulation of subsystem 1. The above process is repeated in each $\Delta T$ thereafter, thus achieving asynchronous parallel co-simulation of FPGA–UREP.

5.3. Analysis of Co-Simulation Results

In this paper, the rated operating voltage of the external power grid is 120 kV, which is reduced to the rated voltage of 575 V of the wind turbine after passing through multiple transformers. The number of wind turbines is 6. The wind speed is constant at 15 m/s, the rated output power of the single machine is 1.5 MVA, and the power factor is 0.9. The DC bus capacitance of the back-to-back converter is 60 mF, and its stable working voltage is 1150 V.

5.3.1. Simulation Accuracy Analysis

To verify the real-time traceability of the interpolation and optimization method of this paper on the transient process of the system, the following two scenarios are set up in the external power grid and the wind turbine connection point, respectively.

Scenario A: A voltage loss fault occurs in the external power grid at the moment of 1.5 s, the voltage drop is 0.8 times the rated voltage, and the fault duration is 0.05 s, the simulation results obtained are shown in Figure 16.

Scenario B: A phase-to-ground short-circuit in phase A occurs at the wind turbine connection point at the moment of 2 s, and the fault duration is 0.01 s. The simulation results obtained are shown in Figure 17.

In Figure 16 and Figure 17, P represents active power and Q represents reactive power. The symbol Simulink shows the offline simulation results obtained by using MATLAB/Simulink library component IGBT modeling with a simulation step of 5 $\mathsf{\mu }\mathrm{s}$; GST and GST-N2 denote the FPGA–CPU real-time simulation results obtained using the GST model method modeling and the prediction compensation combined with Newton interpolation, respectively. Taking the simulation data within 0.2 s before and after the fault moment as steady-state and transient samples, respectively, we compared the Euclidean norm errors [42] of the rotor side A-phase current $i_{ar}$, grid side A-phase current $i_{ag}$ and active power P with the offline simulation results, as shown in

Table 2. Comparison of paradigm errors in different simulation scenarios.

Simulation Scenarios	Modeling Method	Errors in the Steady State (%)			Errors in the Transient State (%)
		${\mathit{i}}_{\mathit{a}\mathit{r}}$	${\mathit{i}}_{\mathit{a}\mathit{g}}$	P	${\mathit{i}}_{\mathit{a}\mathit{r}}$	${\mathit{i}}_{\mathit{a}\mathit{g}}$	P
Scenario A	GST	1.22	0.69	0.12	4.61	2.33	0.19
	GST-N2	1.20	0.62	0.08	2.21	0.67	0.08
Scenario B	GST	1.06	0.67	0.08	9.47	3.13	0.36
	GST-N2	1.03	0.63	0.05	2.54	0.93	0.10

.

From Figure 16 and Figure 17 and Table 2, it can be seen that both modeling methods can track the offline simulation results well in the steady state. When a fault occurs, the transient paradigm error modeled by the GST-N2 interpolation algorithm is reduced by more than half compared to that modeled by the un-interpolated GST, i.e., GST-N2 is closer to the offline simulation. In addition, the model established by the GST method appears to gradually offset the offline simulation after the occurrence of the fault. This verifies the reliability and accuracy of the interpolation algorithm in this paper, i.e., it has high simulation accuracy.

5.3.2. Simulation Time Consumption Analysis

During the FPGA–UREP co-simulation, the first communication consumes 0.28 $\mathsf{\mu }\mathrm{s}$ each for ARP request and reply, and then the link is established. In each 50 $\mathsf{\mu }\mathrm{s}$ large-step cycle, the UDP receiving time is 0.86 $\mathsf{\mu }\mathrm{s}$ and sending time is 0.74 $\mathsf{\mu }\mathrm{s}$ on the FPGA side under GST modeling, and the UDP receiving time is 1.5 $\mathsf{\mu }\mathrm{s}$ and sending time is 0.74 $\mathsf{\mu }\mathrm{s}$ under the GST-N2 interpolation algorithm. The sending and receiving time under both modeling methods does not exceed 5 $\mathsf{\mu }\mathrm{s}$, which leaves sufficient margin for the physical layer transmission of data, thus verifying the reasonableness of sending data 5 $\mathsf{\mu }\mathrm{s}$ ahead of time in this paper. Ignoring the initial compilation time for offline simulation and the link time for real-time simulation, the total simulation time for both modeling methods is shown in

Table 3. Comparison of simulation time consumption.

Simulation Methods	Modeling Method	Simulation Time (s)
		Scenario A	Scenario B
Off-line Simulation	GST	41.94	74.76
	GST-N2	85.13	116.64
Real-time Simulation	GST	2.0	2.5
	GST-N2	2.0	2.5

. From the table, we can see that the real-time simulation time of FPGA–UREP is much smaller than that of offline simulation, which greatly improves the simulation efficiency.

In summary, the FPGA–UREP co-simulation system established in this paper has very good real-time simulation characteristics. Compared with the un-interpolated model, the model built by predictive compensation combined with Newton interpolation algorithm greatly improves the simulation accuracy while maintaining a high simulation efficiency and high feasibility.

6. Conclusions

In this paper, we proposed an asynchronous parallel real-time simulation method for doubly fed wind power systems based on FPGA–CPU. The main work and contributions are as follows:

(1) Based on the CDMS, we performed an asynchronous length model segmentation of the doubly fed wind power system, which enables the decoupling of the small-step back-to-back converter from the large-step turbine and the grid.

(2) The timing and error problems in the decoupling calculation are analyzed, and the PWM data of the small-step side are processed using integral averaging. A prediction delay compensation method was proposed for linear prediction and correction of the data on the large-step side, and the error compensation of the small-step data was realized based on this method combined with Newton interpolation.

(3) The GST mode method is used to model the back-to-back converter in FPGA, and the hardware resources are optimized based on the time-sharing multiplexing principle.

(4) Using multiple processors for different simulation tasks, the real-time simulation platform of the doubly fed wind power system based on FPGA–CPU is built. In particular, the HDL development of the back-to-back converter is carried out on the FPGA with a small step of 1 $\mathsf{\mu }\mathrm{s}$, and the 50 $\mathsf{\mu }\mathrm{s}$ simulation of the wind turbine and the external grid is completed simultaneously in the real-time simulator UREP. By comparing with MATLAB/Simulink offline simulation results, combined with the analysis of errors and comparison of simulation time consumption, the real-time performance and accuracy of the modeling and improved method in this paper are verified.

The proposed improved method solves the latency of multi-processor asynchronous parallel co-simulation and improves the accuracy of co-simulation. Among them, the asynchronous data parallel processing method can be used as a reference for real-time simulation of various rigid systems in power systems. For example, the large inertia link in the power system can be simulated in the CPU, while the high-frequency power electronics are run in the FPGA, and the communication between them can be realized by the interface processing method proposed in this paper. As an important part of the doubly fed wind power system, the back-to-back converter, with its GST model and hardware resource optimization, is unique to doubly fed wind power systems, which is the focus of this paper. In addition, the real-time simulation in this paper can provide a mapping for the stable operation, fault detection, and control methods of the real-world doubly fed wind power system. The real-time simulation can effectively avoid the operation risk of the real system, reduce the probability of failure, and lower the system operation and maintenance cost.