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Computers 2018, 7(2), 21; doi:10.3390/computers7020021

Low Effort Design Space Exploration Methodology for Configurable Caches

1
Department of Electrical and Computer Engineering, University of Miami, Coral Gables, FL 33146, USA
2
Department of Electrical and Computer Engineering, University of Florida, Gainesville, FL 32608, USA
This paper is an extended version of our paper published in Proceedings of the 12th IEEE International Conference on Embedded and Ubiquitous Computing, Milano, Italy, 26–28 August 2014.
*
Author to whom correspondence should be addressed.
Received: 12 February 2018 / Revised: 16 March 2018 / Accepted: 17 March 2018 / Published: 27 March 2018
(This article belongs to the Special Issue Multi-Core Systems-On-Chips Design and Optimization)
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Abstract

Designers can reduce design space exploration time and efforts using the design space subsetting method that removes energy-redundant configurations. However, the subsetting method requires a priori knowledge of all applications. We analyze the impact of a priori application knowledge on the subset quality by varying the amount of a priori application information available to designers during design time from no information to a general knowledge of the application domain. The results showed that only a small set of applications representative of the anticipated applications’ general domains alleviated the design efforts and was sufficient to provide energy savings within 5.6% of the complete, unsubsetted design space. Furthermore, since using a small set of applications was likely to reduce the design space exploration time, we analyze and quantify the impact of a priori applications knowledge on the speedup in the execution time to select the desired configurations. The results revealed that a basic knowledge of the anticipated applications reduced the subset design space exploration time by up to 6.6X. View Full-Text
Keywords: design space exploration; embedded systems; configurable caches; cache tuning; design space subsetting design space exploration; embedded systems; configurable caches; cache tuning; design space subsetting
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Alsafrjalani, M.H.; Gordon-Ross, A. Low Effort Design Space Exploration Methodology for Configurable Caches. Computers 2018, 7, 21.

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