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Computers 2017, 6(1), 8; doi:10.3390/computers6010008

A Survey of Soft-Error Mitigation Techniques for Non-Volatile Memories

E-621, Department of Computer Science and Engineering, Indian Institute of Technology (IIT) Hyderabad, Sangareddy, Telangana 502285, India
Academic Editor: Manuel E. Acacio
Received: 8 December 2016 / Revised: 20 January 2017 / Accepted: 7 February 2017 / Published: 13 February 2017
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Abstract

Non-volatile memories (NVMs) offer superior density and energy characteristics compared to the conventional memories; however, NVMs suffer from severe reliability issues that can easily eclipse their energy efficiency advantages. In this paper, we survey architectural techniques for improving the soft-error reliability of NVMs, specifically PCM (phase change memory) and STT-RAM (spin transfer torque RAM). We focus on soft-errors, such as resistance drift and write disturbance, in PCM and read disturbance and write failures in STT-RAM. By classifying the research works based on key parameters, we highlight their similarities and distinctions. We hope that this survey will underline the crucial importance of addressing NVM reliability for ensuring their system integration and will be useful for researchers, computer architects and processor designers. View Full-Text
Keywords: reliability; non-volatile memory; PCM; STT-RAM; soft-error; read disturbance; write disturbance; resistance drift; error-correcting code (ECC) reliability; non-volatile memory; PCM; STT-RAM; soft-error; read disturbance; write disturbance; resistance drift; error-correcting code (ECC)
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This is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. (CC BY 4.0).

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Mittal, S. A Survey of Soft-Error Mitigation Techniques for Non-Volatile Memories. Computers 2017, 6, 8.

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