Array Multipliers for High Throughput in Xilinx FPGAs with 6-Input LUTs†
AbstractMultiplication is the dominant operation for many applications implemented on field-programmable gate arrays (FPGAs). Although most current FPGA families have embedded hard multipliers, soft multipliers using lookup tables (LUTs) in the logic fabric remain important. This paper presents a novel two-operand addition circuit (patent pending) that combines radix-4 partial-product generation with addition and shows how it can be used to implement two’s-complement array multipliers. The circuit is specific to modern Xilinx FPGAs that are based on a 6-input LUT architecture. Proposed pipelined multipliers use 42%–52% fewer LUTs, and some versions can be clocked up to 23% faster than delay-optimized LogiCORE IP multipliers. This allows 1.72–2.10-times as many multipliers to be implemented in the same logic fabric and potentially offers 1.86–2.58-times the throughput by increasing the clock frequency. View Full-Text
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Walters, E.G. Array Multipliers for High Throughput in Xilinx FPGAs with 6-Input LUTs. Computers 2016, 5, 20.
Walters EG. Array Multipliers for High Throughput in Xilinx FPGAs with 6-Input LUTs. Computers. 2016; 5(4):20.Chicago/Turabian Style
Walters, E. G. 2016. "Array Multipliers for High Throughput in Xilinx FPGAs with 6-Input LUTs." Computers 5, no. 4: 20.
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