Assessment of a High-Order Stationary Frame Controller for Two-Level and Three-Level NPC Grid-Connected Inverters

Abstract

Most grid-connected DC/AC inverters use traditional proportional–integral (PI) controllers in a synchronous frame. In addition to poor disturbance rejection capabilities, these PI controllers also exhibit steady-state errors for sinusoidal reference signals. To address these drawbacks, this article investigates the use of a high-order controller in the stationary frame and then compares it with the standard PI controller. The effectiveness of the high-order controller in the stationary frame has been examined by providing an infinite gain at a resonance frequency. In this work, the design of high-order and PI controllers and tuning instructions are given. Furthermore, both high-order and PI current-controlled two-level and three-level neutral point clamped (NPC) inverters are compared. Various operational conditions are used for the comparison. The high-order controller reduced the total harmonic distortion (THD) of the injected current by 1.15% for the two-level inverter in normal conditions as compared to the PI controller and 0.9% for the three-level NPC inverters. Furthermore, it reduced the THD in balanced abnormal conditions by 0.5% for the two-level inverter and 0.18% for the three-level NPC inverters. However, the dq controller has a lower THD during unbalance and short circuit conditions.

1. Introduction

Recently, there has been a rise in the demand for energy, which has resulted in various difficulties for distribution networks, including instability in the grid and power outages. Because it results in more flexibility, balance, and stability for the grids, the utilization of distributed power generating systems (DPGS) is a feasible solution for these issues. Additionally, it can enhance the management of distribution networks and lower the amount of carbon that is released [1]. Wind turbines and photovoltaic systems as well as energy storage devices such as battery banks and fuel cells as well as active filters are DPGS examples. The output voltage for these systems is typically DC, but it must be converted to AC before it can be discharged to the grid or used to power other loads [2,3].

As a result, inverters play a crucial part in grid connected DPGS because they enable the DPGS to convert the DC voltage and current to AC and then transfer it to the grid. As far as design goes, the three-phase inverter is the most basic two-level inverter. It finds widespread applicability in a diverse range of low-voltage and low-power contexts. In order for the two-level inverter to be able to endure high voltage and high current when used in high-power applications, it requires several switch connections that are connected in series and in parallel. In order to prevent overvoltage failures, all of the switches in the series must be turned on or off at the same time. In addition to this, the two-level inverter needs the utilization of big filters for the reduction in harmonics [4].

The reliability of conventional multilevel converters has been demonstrated in a variety of high-power applications. They are most commonly categorized as neutral-point clamped (NPC), cascaded H-bridge (CHB), or flying capacitor (FC) topologies [5,6]. When compared with the conventional two-level inverters, they are capable of managing more power and voltages at lower switch voltage stress than the conventional inverters. Because of this, both the size of the output filter and the switching frequency can be lowered in a noticeable way [7].

Nevertheless, connecting inverters to the grid is critical because it causes a slew of issues, including grid instability and disturbance, if no suitable controller is in place [8]. As a result, these systems should be able to compensate for grid distortions. In this case, a high-speed controller as well as a compatibility algorithm are required. Furthermore, the controller’s design is critical and significant. Active and reactive power transmission between the grid and DPGS, regulation of DC-link voltage, and grid synchronization are all critical functions of this controller [1]. The current-controlled inverter is the one that is utilized more frequently compared with the voltage-controlled inverter. The control strategy makes use of two cascade loops: an inner current loop that regulates the utility current and an outer power loop that supplies the reference current. There are two basic categories that may be used to categorize current-based controllers, namely, the non-linear control technique and the linear control technique [9].

Grid inverters have integrated non-linear controls such as sliding mode, dead-beat, hysteresis, and predictive control [10]. As one of the predictive regulators, deadbeat control mechanisms are the most commonly used control approach. When the deadbeat controller is properly tuned, it is possible to achieve near-zero tracking error in finite sample steps. When the sampling frequency is increased, this control is more susceptible to mismatches and noise [11,12]. A voltage source inverter can use the hysteresis control approach to create switching signals for inverters by comparing the output utility current to the input reference current. This control method’s advantages include ease of use, independence from the loads they are supposed to control, and an excellent transient response [13]. The ability of the predictive control method in nonlinear control systems is well-known. Predictive control can achieve precise current regulation with low total harmonic distortion; however, it is often difficult to execute in practice. The inverter voltage required to force the utility current to follow a current reference is monitored using this control technique [14,15]. The sliding mode (SM) control approach is popular for non-linear and linear loads. Its remarkable performance has made SM control one of the most extensively used algorithms. High dynamic response, stability, robustness, and ease of implementation are the main advantages of this control method. However, the SM control technique has some disadvantages that are well recognized when it is employed with variable switching frequency [16]. These constraints include control imprecision, significant power losses, and a complicated output filter design [17].

On the other hand, the proportional–integral (PI) controller and the proportional-resonant (PR) controller are both types of linear control techniques that can be used in current-controlled inverters [10]. The PI controller has two drawbacks that are well-known in the industry: The weakness of PI controller performance in the stationary frame, which results in steady state error and a phase shift in the current as compared to the reference [18]. Both drawbacks apply to the controller. This is a result of the integral action not performing effectively with sinusoidal reference [19]. Synchronous frame PI control with voltage feed-forward is a popular option [20]. However, it requires multiple conversions in frames and can be difficult to set up with a low-cost fixed-point digital signal processor [21,22]. The PR controller is a type of current controller that does not have the aforementioned disadvantages and is more suited to working with the sinusoidal references and stationary frame than other controllers do [23]. The PR controller only produces gain at one frequency, called the resonant frequency. At all other frequencies, the controller has almost no gain [21].

This paper focuses on two types of controllers, the PI controller in dq frame and the high-order controller in αβ frame. These two different current controllers have been designed and their performance has been compared under different operational conditions for controlling the two-level inverter as well as the three-level NPC inverters. The comparison between the controllers and topologies is conducted using the simulation platform MATLAB/Simulink.

2. Materials and Methods

2.1. Converter Modeling

A half-bridge is the fundamental topology of any voltage source converter because it is the topology that contains only one leg of the converter. In this section, an average model of a two-level half-bridge converter and a three-level half-bridge NPC converter is developed. This gives us the ability to explain the dynamics of the converter as a function of the modulating signal [16].

2.1.1. Two-Level Half-Bridge Converter Averaged Model

For the purpose of describing the fundamental half-bridge two-level converter seen in Figure 1, we will refer to the state of the switch as s(t). This value will be either 1 if the switch is conducting or 0 if it is blocked, and these values are complementary to one another.

$$s_1\left(t\right)+s_2\left(t\right)=1$$

(1)

when $s_1$ is on, $V_t\left(t\right)$ is equal to $\left(\frac{V_{DC}}{2}\right)$, but when $s_4$ is on, it is equal to $-\left(\frac{V_{DC}}{2}\right)$when $s_2$ is on, so $V_t\left(t\right)$can be expressed as a function of both $s_1\left(t\right)$and $s_2\left(t\right)$ as follows:

$$V_t\left(t\right)=\left(\frac{V_{DC}}{2}\right)s_1\left(t\right)-\left(\frac{V_{DC}}{2}\right)s_2$$

(2)

Using the averaging operator [24] to calculate the average of a variable as a function of time:

$$\overline{x}\left(t\right)=\frac{1}{T} {{\displaystyle \int }}_{t-T}^{t}x\left(\tau \right) d\tau$$

(3)

Additionally, applying the operator to $s_1\left(t\right)$and $s_2\left(t\right)$, it can be concluded that

$${\overline{s}}_1\left(t\right)=d$$

(4)

$${\overline{s}}_2\left(t\right)=1-d$$

(5)

where d is the duty ratio. Substituting (4) and (5) in (2)

$$\overline{V_t}\left(t\right)=\left(\frac{V_{DC}}{2}\right)\left(2d-1\right)$$

(6)

In the SPWM strategy, the relationship between the reference signal (m) and the duty ratio is [25]:

$$m=\left(2d-1\right)$$

(7)

From (6) and (7), it is safe to say that

$$\left(t\right)=\left(\frac{V_{DC}}{2}\right)\left(m\right)$$

(8)

2.1.2. Three-Level Half-Bridge Converter Averaged Model

In the three-level half-bridge shown in Figure 2, the AC-side voltage may be represented for a positive modulating signal m as follows:

$$V_t\left(t\right)=\left(\frac{V_{DC}}{2}\right)s_1\left(t\right)+\left(0\right) s_3\left(t\right)$$

(9)

where $s_1\left(t\right)+s_3\left(t\right)=1$. In the same way, the AC-side voltage for negative modulating functions is

$$V_t\left(t\right)=-\left(\frac{V_{DC}}{2}\right)s_4\left(t\right)+\left(0\right) s_2\left(t\right)$$

(10)

where $s_4\left(t\right)+s_2\left(t\right)=1$. Equations (9) and (10) can be unified through

$$V_t\left(t\right)=\left(\frac{V_{DC}}{2}\right)s_1\left(t\right) sgn\left(m\right)-\left(\frac{V_{DC}}{2}\right)s_4\left(t\right) sgn\left(-m\right)$$

(11)

where the function $sgn\left(x\right)$ is defined by

$$sgn\left(x\right)=\{\begin{array}{c}1, x\ge 0\\ 0, x<0\end{array}$$

(12)

Applying the averaging operator to both sides of (9) and (10), over one switching cycle, we reach the conclusion

$$\overline{V_t}\left(t\right)=\left(\frac{V_{DC}}{2}\right)m\left(t\right) , m \le 0$$

(13)

$$\overline{V_t}\left(t\right)=\left(\frac{V_{DC}}{2}\right)m\left(t\right) , m \le 0$$

(14)

Equations (13) and (14) can be unified as

$$V_t\left(t\right)=\left[\left(\frac{V_{DC}}{2}\right) sgn\left(m\right)+\left(\frac{V_{DC}}{2}\right) sgn\left(-m\right)\right] m\left(t\right)$$

(15)

Since $sgn\left(m\right)+sgn\left(-m\right)=1$, Equation (15) can be written as

$$\overline{V_t}\left(t\right)=\left(\frac{V_{DC}}{2}\right)m\left(t\right)$$

(16)

Therefore, it is obvious that (16) is identical to (8), which indicates that the average model can be applied for both converters [25].

2.2. AC Side Control Model of Both Converters

Considering Figure 1 and Figure 2, the dynamics of the AC current are described by

$$L\frac{d}{dt}i\left(t\right)+Ri\left(t\right)=V_t\left(t\right)-V_s$$

(17)

However, based on Equations (8) and (16), $V_t$ can be controlled by the modulating signal $m$. Figure 3 shows a control block diagram of the system described by (17).

Equation (17) can be expanded for the three-phase system as follows:

$$L\frac{d{i}_a}{dt}=-R{i}_a+V_{ta}-V_{sa}$$

(18)

$$L\frac{d{i}_b}{dt}=-R{i}_b+V_{tb}-V_{sb}$$

(19)

$$L\frac{d{i}_c}{dt}=-R{i}_c+V_{tc}-V_{sc}$$

(20)

2.3. Controller Modelling and Design [25]

2.3.1. High-Order Stationary Frame αβ Controller [25]

Equations (18)–(20) can be expressed in αβ frame using the Clarke transformation as follows:

$$L\frac{d{i}_{\alpha }}{dt}=-R{i}_{\alpha }+V_{t\alpha }-V_{s\alpha }$$

(21)

$$L\frac{d{i}_{\beta }}{dt}=-R{i}_{\beta }+V_{t\beta }-V_{s\beta }$$

(22)

Expressing $V_{t\alpha }$ and $V_{t\beta }$ in terms of $m_{\alpha }$ and $m_{\beta }$

$$L\frac{d{i}_{\alpha }}{dt}=-R{i}_{\alpha }+\frac{V_{DC}}{2}{m}_{\alpha }-V_{s\alpha }$$

(23)

$$L\frac{d{i}_{\beta }}{dt}=-R{i}_{\beta }+\frac{V_{DC}}{2}{m}_{\beta }-V_{s\beta }$$

(24)

Based on Equations (23) and (24), the control loop shown in Figure 4 is developed.

For real/reactive power controller, the currents $i_{\alpha -ref}$ and $i_{\beta -ref}$ are generated using the following equations:

$$i_{\alpha -ref}\left(t\right)=\frac{2}{3}\left[\frac{V_{s\alpha }}{V_{s\alpha }{}^2+V_{s\beta }{}^2 } P_{s-ref\left(t\right)}+\frac{V_{s\beta }}{V_{s\alpha }{}^2+V_{s\beta }{}^2 } Q_{s-ref\left(t\right)} \right]$$

(25)

$$i_{\beta -ref}\left(t\right)=\frac{2}{3}\left[\frac{V_{s\alpha }}{V_{s\alpha }{}^2+V_{s\beta }{}^2 } P_{s-ref\left(t\right)}+\frac{V_{s\beta }}{V_{s\alpha }{}^2+V_{s\beta }{}^2 } Q_{s-ref\left(t\right)} \right]$$

(26)

2.3.2. High-Order Stationary Frame αβ Compensator Design

First of all, the gain crossover frequency ${\mathsf{\omega }}_{C }$ of the designed compensator should be determined and it must satisfy the inequality ${\mathsf{\omega }}_{C }$< ${\mathsf{\omega }}_b$ < $2{\mathsf{\omega }}_{C }$, where ${\mathsf{\omega }}_b$ is the bandwidth of the closed loop which should be very larger than the command signal frequency ${\mathsf{\omega }}_{o }$ in such a way that ${\mathsf{\omega }}_{b }\approx 9{\mathsf{\omega }}_o.$ However, the loop gain of Figure 4 is dictated by:

$$l\left(s\right)=k\left(s\right) \frac{1}{Ls+R}$$

(27)

Since the command is a sinusoidal signal, the compensator should include complex-conjugate poles at the rated frequency (s² + ${{\mathsf{\omega }}_{o }}^2$) to ensure zero steady-state error. Figure 5 shows the frequency response of $l\left(j\omega \right)$ in dashed lines after adding the complex-conjugate poles, which contain a phase shift of $-{90}^{°}$ at low frequencies owing to the pole $s=-\frac{R}{L}$, which must be canceled out by the compensator $k\left(s\right)$ by including a zero at the same value. Figure 5 shows the frequency response after the pole cancelation in solid lines.

However, even after the pole cancelation, the phase margin at ${\mathsf{\omega }}_{C }$is zero and a lead compensator is needed to add a phase margin of ${45}^{°}$ at ${\mathsf{\omega }}_{C }$ to improve the stability. The dashed line in Figure 6 shows the frequency response after adding the lead compensator and it is noted that the system is stable, but the gain is almost constant at low frequencies. In order to exhibit a large gain at low frequencies, a lag compensator needs to be added to the compensator, and the solid lines in Figure 6 show the final compensator frequency response.

The final compensator is:

$$k\left(s\right)=h \left(\frac{s+\raisebox{1ex}{$R$}\!\left/ \!\raisebox{-1ex}{$L$}\right.}{s^2+{\mathsf{\omega }}_o{}^2}\right) k_{lead}\left(s\right) k_{lag}\left(s\right)$$

(28)

2.3.3. Synchronous Frame dq Controller [25]

Equations (18)–(20) can be expressed in dq frame using the Park transformation as follows:

$$L\frac{d{i}_d}{dt}=L{\mathsf{\omega }}_{o }{i}_d-R{i}_d+V_{td}-V_{sd}$$

(29)

$$L\frac{d{i}_q}{dt}=-L{\mathsf{\omega }}_{o }{i}_q-R{i}_q+V_{tq}-V_{sq}$$

(30)

Expressing $V_{td}$ and $V_{tq}$ in terms of $m_d$ and $m_q$

$$L\frac{d{i}_d}{dt}=L{\mathsf{\omega }}_{o }{i}_d-R{i}_d+\frac{V_{DC}}{2}{m}_d-V_{sd}$$

(31)

$$L\frac{d{i}_q}{dt}=-L{\mathsf{\omega }}_{o }{i}_q-R{i}_q+\frac{V_{DC}}{2}{m}_q-V_{sq}$$

(32)

Based on (31) and (32), the control loop shown in Figure 7 is developed.

For the real-/reactive-power controller, the currents $i_{d-ref}$ and $i_{q-ref}$ are generated using the following equations:

$$i_{d-ref}\left(t\right)=\frac{2}{3 V_{sd}}{P}_{s-ref\left(t\right)}$$

(33)

$$i_{q-ref}\left(t\right)=\frac{2}{3 V_{sd}}{Q}_{s-ref\left(t\right)}$$

(34)

2.3.4. Synchronous Frame dq Compensator Design

For simplicity, the control loop can be simplified as shown in Figure 8. However, an integral-proportional (PI) compensator can follow a DC reference in synchronous frame control, in contrast to stationary frame control where compensators are difficult to adjust and have large dynamic orders. The transfer function of the PI controller is given as follows:

$$k\left(s\right)=\frac{k_{p}s+k_i}{s}$$

(35)

As a result, the loop gain of the simplified loop will be given as follows:

$$k\left(s\right)=\left(\frac{k_p}{Ls}\right)\frac{s+\raisebox{1ex}{$k_i$}\!\left/ \!\raisebox{-1ex}{$k_p$}\right.}{s+\raisebox{1ex}{$R$}\!\left/ \!\raisebox{-1ex}{$L$}\right.}$$

(36)

From (35), it is noted that $\raisebox{1ex}{$k_i$}\!\left/ \!\raisebox{-1ex}{$k_p$}\right.$must be equal to $\raisebox{1ex}{$R$}\!\left/ \!\raisebox{-1ex}{$L$}\right.$ in order to cancel the pole effect, which can be achieved by making the constants $k_p$ and $k_i$ as follows:

$$k_p=\raisebox{1ex}{$L$}\!\left/ \!\raisebox{-1ex}{$\tau $}\right.$$

(37)

$$k_i=\raisebox{1ex}{$R$}\!\left/ \!\raisebox{-1ex}{$\tau $}\right.$$

(38)

where $\tau$ is the time constant of the closed loop and should be in the range of (0.5–5) ms.

2.3.5. Phase-Locked Loop (PLL)

Unlike the stationary frame, the synchronous frame needs to be synchronized with the grid. Phase Locked-Loop is a technique for calculating the grid angle. The grid voltage is fed into the system, and the grid angle θ and the frequency ω are outputs. For the PLL diagram shown in Figure 9, the input to the Park transformation is the voltage of each of the three phases of the grid (abc), and the outputs are the voltages in the Synchronous Rotating Frame (dq). Since the q voltage should be kept constant at zero, it is measured and compared with the reference value of zero. In order to cancel the component q, a PI controller is used to accelerate the dq frame within this feedback loop [26].

2.3.6. NPC DC Voltage Equalizer

Unlike the two-level inverter, technically the NPC’s key issue is to keep the voltages of the two DC-side capacitors equal and at a predetermined level. Due to system flaws, the voltages of DC capacitors may either significantly diverge during transients or steadily drift during steady-state operation. Voltage drift can be avoided through the use of an external converter to correct the DC component [27,28]. Here, the external converter is instructed on how much current to inject into the midpoint based on the (DC) voltage difference between the two capacitors. The biggest issue with this strategy is that it necessitates extra hardware to generate current, which raises both the cost and complexity of the overall system. However, an alternative approach is the control strategy proposed in [29], which recommends altering the converter switching pattern in order to keep the DC-side voltage at the appropriate value. The control strategy is based on the idea that if the neutral point voltage changes, the control scheme responds by adding a DC offset to the modulating signal, The capacitor balance is restored as a result of the offset creating a current in the neutral point. The controller in Figure 10 is responsible for generating the DC offset. This method is a good way to solve the NPC’s biggest technical problem from an economic point of view.

3. Results and Discussion

The system shown in Figure 11 and Figure 12 with parameters in

Table 1. System parameters [25].

Parameter	Value
Vdc	1250 V
Grid VL-L RMS	480 V
Filter inductor Lf	100 µH
Filter Resistor	1.19 mΩ
Switch frequency fsw	3420 Hz
Pref	1 MW
Qref	0 VAR

has been studied using the two controllers having the parameters given in

Table 2. Controller parameters.

dq Controller
Parameter	Value
Time constant $\tau$	2 ms
Porpotional gain $k_p$	0.05
Integral gain $k_i$	0.595
αβ controller
Parameter	Value
Gain $h$	1258
Transfer function	$\frac{S+11.9}{S^2+{377}^2}$
Lead compensator	$\frac{S+966}{S+5633}$
Lag compensator	$\frac{S+2}{S+0.05}$
NPC DC voltage equalizer
Parameter	Value
gain $k$	0.0014

. The performance of the two converters controlled by both controllers is compared in terms of power quality under five cases:

• Case 1: Balanced voltage grid (normal conditions).
• Case 2: Balanced voltage dip and swell.
• Case 3: Unbalanced voltage dip and swell.
• Case 4: Symmetrical and unsymmetrical faults at PCC point.
• Case 5: Transient analysis.

3.1. Case 1

Table 3. Case 1 results.

Converter	ITHD	VTHD
2L-αβ	1.33%	Less than 1%
2L-dq	2.48%	Less than 1%
3 L-αβ	1.29%	Less than 1%
3L-dq	2.19%	Less than 1%

shows the results of all topologies and controllers under normal conditions.

The output three-phase voltages are balanced and constant as shown in Figure 13, and the injected current is shown in Figure 14, indicating that all possible topologies and controllers are performing well and delivering power as the reference values as shown in Figure 15. However, the injected current in the three-level topology has lower Total Harmonic Distortion (THD) than the two-level topology. On the other hand, the high-order αβ controller outperforms the dq controller. The three-level high order αβ controller converter is superior; however, the other converter did not exceed the standard limits [30].

3.2. Case 2

Table 4. Case 2 results.

	Swell		Dip
Converter	ITHD	VTHD	ITHD	VTHD
2L-αβ	9.05%	7.88%	10.46%	11.81%
2L-dq	9.55%	7.88%	10.64%	11.81%
3 L-αβ	8.97%	7.88%	10.49%	11.81%
3L-dq	9.15%	7.88%	10.84%	11.81%

shows the results for all topologies and controllers at 30% balanced voltage dip and 30% balanced voltage swell occurring at 0.1 s.

All topologies and controllers exceeded the THD standard constraints; the pcc voltages and currents in the case of the balanced voltage dip are shown in Figure 16 and Figure 17, respectively. The conventional two-level topology performs better than the three-level topology, and the high-order αβ controller has a lower THD in the injected current than the dq controller. As demonstrated in Figure 18, all controllers successfully followed the power reference even under the voltage dip, despite the fact that the injected power experienced a minor transient dip at the time the voltage dip occurred.

The pcc voltages and currents for balanced voltage swell are depicted in Figure 19 and Figure 20, respectively. Although the three-level topology performs better than the two-level topology, the high-order αβ controller still has a lower THD in the injected current than the dq controller. Additionally, as shown in Figure 21, all controllers maintained the injected power as the reference value after the voltage swell occurred with a short transient swell at the time the voltage swell occurred.

3.3. Case 3

Table 5. Case 3 results.

	Swell		Dip
Converter	ITHD	VTHD	ITHD	VTHD
2L-αβ	10.70%	7.88%	16.22%	11.81%
2L-dq	7.76%	7.88%	8.78%	11.81%
3 L-αβ	10.61%	7.88%	16.24%	11.81%
3L-dq	7.22%	7.88%	8.93%	11.81%

shows the result for all topologies and controllers at 30% unbalanced voltage dip and 30% unbalanced voltage swell occurring at 0.1 s.

Identical to the previous case, each topology and each controller failed to meet the THD requirements. The currents and voltages at pcc are shown in Figure 22 and Figure 23 during the unbalanced voltage drop. The conventional two-level topology is superior to the three-level structure, and the THD of the injected current is lower for a high-level αβ controller than for a dq controller. As can be seen in Figure 24, after an unbalanced voltage drop occurred, no control device was able to prevent the injected power from fluctuating around the reference value.

Figure 25 and Figure 26 show the pcc voltages and currents during an unbalanced voltage swell. While the dq controller still has a lower THD in the injected current than the high-level αβ controller, the performance of the three-level structure is superior to that of the two-level structure. Moreover, as can be seen in Figure 27, after an unbalanced voltage swell occurs, the injected power oscillates around the reference value, indicating that no controller is able to keep it stable.

3.4. Case 4

In this case, all converters were subjected to a comprehensive short circuit test. Figure 28 and Figure 29 show the power flow in the symmetrical and unsymmetrical fault cases occurring at 0.1s, respectively. It can be seen that the dq controller has a significantly superior fault performance than the higher-level αβ controller, especially in terms of symmetrical fault power fluctuation. However, under the unsymmetrical fault, both controllers failed to maintain a constant flow of power.

3.5. Case 5

In this case, the coupling between active and reactive power has been investigated for both controllers under a transient analysis. At t = 0.1 s, P_ref experiences a step change from 0 to 1 MW, followed by another step change from 1 MW to -1 MW at t = 0.2 s. At t = 0.15s, Q_ref is exposed to a step change that goes from 0 to 600 MVAR. Figure 30a,b demonstrates that active and reactive powers are not totally decoupled from one other in αβ frame, as indicated by Equations (25) and (26). In contrast, as shown in Figure 30c,d, the active and reactive powers in the dq frame are decoupled from one another when any of them are changed, as indicated by Equations (33) and (34). This is the case even though the performance of both controllers following the reference power is satisfactory.

4. Conclusions

In this paper, the design of both dq and higher-order αβ controllers for a three-level NPC inverter and a two-level conventional grid-connected inverter is presented, and the performances are compared through simulations under different operational conditions. From the simulation results summarized in

Table 6. Results summary.

Case	Lower THD Topology	Lower THD Controller
Balanced voltage	Three-level	αβ controller
Balanced voltage dip	Two-level	αβ controller
Balanced voltage swell	Three-level	αβ controller
Unbalanced voltage dip	Two-level	dq controller
Unbalanced voltage swell	Three-level	dq controller
Symmetrical fault	Two-level	dq controller
Unsymmetrical fault	Two-level	dq controller

, it can be seen that under normal conditions, balanced voltage swell and balanced voltage dip, the higher-order αβ controller obtains a lower THD than the dq controller. The dq controller has a lower THD during unbalanced and short circuit conditions.

From a topological perspective, a three-level NPC inverter injected a current with lower total harmonic distortion (THD) under normal, balanced, and unbalanced voltage swell. THD is lower for both levels in other cases.

In the weak grid, the high-order αβ controller can be investigated for future research. In addition, their performance under unbalanced conditions must be investigated with properly designed additional harmonic compensation.