Bidirectional Twisted Single-Stage Single-Phase Buck-Boost DC-AC Converter

Abstract

This paper describes a bidirectional twisted single-phase single-stage buck-boost dc-ac converter based on an output unfolding circuit. This solution is derived by the combination of an inverting buck-boost dc-dc converter and an unfolding circuit. The operation principle, component design guidelines, along with the control approach are presented. The zero-crossing distortion problem is discussed and solved by a simple approach. The simulation and experimental results confirm all theoretical statements. Loss distribution and achievable efficiency are analyzed. Finally, the pros and cons of the proposed solution, along with the most promising application field, are analyzed and discussed in the conclusion.

1. Introduction

Renewable energy sources require advanced technologies. A photovoltaic (PV) system stands out among the present and future energy systems. The concept of a near zero energy building requires the presence of additional storage elements, which raises the cost of the overall system.

A solar inverter, as part of the PV system, contributes substantially to the overall price and efficiency of the system. System optimization, in terms of price, efficiency, input voltage range operation, and power density, is the priority task in power electronics research. The Google Little Box Challenge (GLBC) demonstrated a close relation with the topic of high-power density inverters for PV applications [1,2,3]. The main GLBC project outcome is the concept of a very high-power density converter. The finalists demonstrated that a basic full-bridge interleaved inverter with an active decoupling circuit, along with wide band-gap semiconductors utilization, may give the best result in terms of power density. At the same time, the mass production market demands simple and cheap solutions. Usually, power density optimization is not a first level priority.

In PV systems, several configurations can be used [4,5]. Single PV panels are available for low power applications. A partial shadowing in the serial or string connection leads to a significant voltage drop, which in turns leads to a wide range of input voltage variations during the energy utilization time. An intermediate voltage boost dc-dc converter can be used to overcome this drawback. It is shown in Figure 1a.

Another application field of the dc-ac converter with wide input voltage regulation is battery storage. Lithium-ion batteries are targeted to become the most popular choice for on-grid and grid-off solar battery storage in the foreseeable future. Such types of batteries have a wide range of input voltage. A converter that accepts different storage elements is preferable.

Several single-stage alternatives were presented as alternative solutions. Inverters with an active boost cell were described in [6,7,8,9]. These inverters provide very high boost of the input voltage but suffer from high current spikes in the semiconductors and passive elements. Impedance-source networks have been reported in many research papers as a promising single-stage solution. Z-source inverters (ZSIs) and quasi-Z-source inverters (qZSIs) were proposed for different applications. Existing solutions were reviewed in [10,11,12,13,14], and different relevant issues are addressed in [15,16,17,18,19,20]. However, recent research revealed evident drawbacks of the IS-based converters in terms of power density and efficiency [21,22,23].

Split-source inverters (SPIs) [24,25] were proposed as another alternative solution. According to the literature, SPIs have less passive component counts accompanied by higher voltage and current stresses at lower voltage gains, and they do not have short circuit immunity.

Several interesting single-stage buck-boost inverters were proposed in [26,27,28,29]. At the same time all of them did not find industrial application. For example, the solution [26] requires reverse-blocking IGBTs, while others are quite complex solutions.

An Aalborg inverter (Figure 1b) is proposed as an inverter that combines buck and boost functionality [30,31,32,33,34,35]. These solutions have two independent buck-boost stages that are responsible for output sinusoidal voltage generation. The main advantage of the proposed solution is in the minimum voltage drop of the filtering inductors in the power loop at any time. At the same time, this solution uses a double number of semiconductors and an inductor in the buck and boost stage, which is an obvious drawback. Another drawback consists in the two power sources utilization. A similar idea with double components is discussed in [36].

The solution based on the input boost and buck converter along with a line frequency unfolding circuit was proposed in [37,38]. The input voltage is boosting to the constant dc-link voltage. The Buck stage performs further modulation, which is unfolding to the sinusoidal voltage.

A modified solution based on the inverting buck-boost dc-dc converter that allows reducing count of inductors is proposed in [39,40]. This paper discusses a grid-connected application of the proposed above discussed solution along with its bidirectional application which extends its application. The objective includes designing a closed-loop control along passive component design with efficiency estimation.

2. Control System of Twisted Single-Phase Single-Stage Inverter based on Unfolding Circuit

The discussed single-phase single-stage buck-boost dc-ac converter based on the unfolding circuit is depicted in Figure 2. This circuit consists of inductances L₁, L₂ capacitors C₁ and C₂, switches S₁, S₂, and low frequency switches T₁–T₄. The switch S₂ can be replaced by a diode D₁ in the case of unidirectional operation.

According to the classical definition of the unfolding circuit, transistors T₁–T₄ realize a simple unfolding circuit. However, these switches can also be used for high frequency modulation.

The proposed solution is derived from the conventional buck-boost dc-dc converter that has a following gain factor B:

$$B=\frac{D}{1-D},$$

(1)

where D represents the duty cycle of the switch S₁. Taking into account the instantaneous reference output voltage v_c2(t), the instantaneous value of the duty cycle D(t) can be expressed as follows:

$$D(t)=\frac{\left|v_C(t)\right|}{v_{IN}+\left|v_C(t)\right|},$$

(2)

Figure 3a shows a general control system approach along with the modulation technique. It should be mentioned that the main task of a high-level control system depends on the particular application. Using an output current as a feedback signal, the modulation signal V_MOD can be derived by different control approaches including a resonant controller, DQ control, model predictive control, etc. A well-known Second Order Generalized Integrator (SOGI) phase-locked loop (PLL) algorithm for grid synchronization is used in [41].

The duty cycle modulator defines the duty cycle value according to Equation (2). This value defines the switching signal of the transistor S₁ by means of a very simple modulation technique. The unfolder’s transistors are controlled by a simple comparison of the capacitor voltage with the zero level.

The modulation signal V_MOD is derived from the output current controller. In this case, a simple proportional-resonant (PR) controller with Harmonic Compensation (HC) was used. The control system tuning is based on the transfer function of the proposed solution, which is derived from a small signal model [42]. The transfer function is shown in Figure 3b.

The PR-controller factors were determined based on the transfer function, which takes into account the input stress as the changing of the duty cycle:

$${G\left(s\right)|}_{\widehat{u}=0}^{}=\frac{{\widehat{i}}_g}{\widehat{d}}=\frac{N\left(s\right)}{sM\left(s\right)}$$

(3)

The small signal designing is a suitable approach for explaining the topology by analytic expressions. The equivalent circuits include the parasitic resistance of each passive element (Figure 4). These parasitic parts include resistors of on-state semiconductor switches. The presence of three passive elements leads to polynomials with third order in the denominator:

$$\begin{array}{l}N(s)=\frac{\left(C_{1}Rs+1\right)}{R\left(1+D^{\prime }\right)}\cdot [L_{1}s\left(v_g+V_D-\left(v_g+v_{IN}+V_D\right)D\right)+\\ \left(2v_{IN}+3v_g+3V_D-\left(v_g+v_{IN}+V_D\right)\left(3+D^{\prime }\right)\cdot D\right)\cdot R],\end{array}$$

(4)

$$\begin{array}{l}M(s)=[C_1{L}_1{L}_g{s}^3+C_{1}R{s}^2\cdot \left(L_g\cdot \left(1+D^{\prime }\right)+2L_1\right)+\\ s\cdot \left(C_1{R}^2\cdot \left(1+D^{\prime }\cdot \left(2+D^{\prime }\right)\right)+L_g\cdot {\left(D^{\prime }\right)}^2+L_1\right)+\\ R\cdot \left(1+D^{\prime }\right)]\cdot s,\end{array}$$

(5)

where $D^{\prime }$ is a reverse value of the duty cycle, and each parasitic resistance is replaced by $R$.

The tuning approach described in many research papers does not contain any novelty. Reference current I_REF can be derived from a high-level algorithm that depends on a particular application, which is out of scope of this paper. If the power flows from the dc to the ac side, it can be derived from the high-level maximum power point tracking algorithm or the battery discharging algorithm. In an opposite power flow, it can be derived by the battery charging algorithm or an additional capacitor voltage v_c2 control loop.

3. Component Design Guidelines for Bidirectional Operation

This section describes guidelines for the design of passive and active components taking into account predefined parameters and target losses level in the system.

The main approach of passive element design has relevance to the steady-state analysis. Each period occurs with the processing of energy storage by the input inductance (Figure 4a) and is immediately transferred to the load (Figure 4b). It should be noted that the parasitic parameters are not taken into account in the calculation.

As a rule, the expression of the pulsations of the output capacitor voltage depends on the capacitor current, the switching frequency, and the value of the capacitance. However, the change of the output current depends directly on the ac-part of the capacitor voltage. The area of the capacitor voltage ac-part is proportional to the ripples of the output current.

The values of passive components are expressed as:

$$L_1\left(\phi \right)=\frac{V_{IN}^2\cdot V_M^2\cdot \left|\sin \left(\phi \right)\right|}{2K_{L}Pf\left(V_{IN}+V_M\cdot \left|\sin \left(\phi \right)\right|\right)\cdot \left(V_{IN}+V_M\right)}$$

(6)

$$C_1\left(\phi \right)=\frac{2P\cdot {\sin }^2\left(\phi \right)}{2K_C{V}_{M}f\left(V_{IN}+V_M\cdot \left|\sin \left(\phi \right)\right|\right)}$$

(7)

$$L_g\left(\phi \right)=\frac{K_C{V}_M^2}{16K_{g}Pf}$$

(8)

where $\phi$ is a current phase of the grid voltage, V_M is the amplitude of the grid voltage and K_L, K_C, K_g are coefficients of corresponding element ripple. The ripples of elements are defined as follows:

$$K_L=\frac{2\Delta i_L}{I_{LMAX}},K_C=\frac{2\Delta v_C}{V_M},K_g=\frac{2\Delta i_g}{I_{gMAX}},V_{INp.u.}=\frac{v_{IN}}{V_{M }}.$$

(9)

The obtained expressions show the dependence between the optimal values of the passive components and the phase of the grid voltage. Also, the high-switching side of the topology allows obtaining a current with only positive values.

Figure 5 shows the influences of the passive component values on the ratio between the input stress and the amplitude of the grid voltage (Equation (9)) at constant input power and input current.

The ripple factor is constant for each element. All the values of inductances or the capacitor are normalized to their value at a point when the input voltage equals the grid voltage maximum:

$$L_{1p.u.}=\frac{L_1}{L_0},C_{1p.u.}=\frac{C_1}{C_0},L_{gp.u.}=\frac{L_g}{L_{g0}},$$

(10)

where L₀, L_g0, C₀ represent values of the passive elements when the ratio V_INp.u. is equal to one unit.

To select a semiconductor, the losses model of the proposed solution is proposed and analyzed. The switching and conduction losses of the MOSFET transistors are taken into account [43]. The conduction losses model is illustrated in Figure 4—it includes the drain-source resistance R_ds of transistors, the equivalent series resistance R_esr of capacitors and voltage drop on the diode V_fd.

Figure 6 demonstrates the power losses of the topology as the function of the power and the input voltage.

The switching losses at the constant input current and the constant input power are shown in Figure 6b. Figure 6c shows the overall expected efficiency of the converter as a function of the input voltage. In this case, different distributions between the conduction and the switching losses are considered. In the first case (dotted line), semiconductors with a good static characteristic are considered, while in the second case, the conduction losses dominate. The main idea of this quality analysis is to show the possibility of the maximum efficiency point tuning and optimization.

As a conclusion of this section, the values of the passive elements determine the pulsations of current in transistors. The proper selection of the passive components can avoid discontinues current mode, that could lead to unstable behavior. At the same time, the selected topology does not have a dc-link stage, thus no dc-link electrolytic capacitors are required.

4. Simulation Verification of Bidirectional Operation Capability

To verify the theoretical statements and basic operation modes, simulations were performed for proposed solutions in PSCAD simulation tool (Figure 7 and Figure 8). Since the PV or different storage batteries are considered as possible application scenario, a wide range of the input voltage is defined. The values of passive components are illustrated in

Table 1. Passive components used for simulation verification.

Passive Components	Value
Input capacitor, C1	330 uF
Inductor, L1	1800 uH
Unfolding capacitor, C2	2.1 uF
Grid side inductor, L2	670 uH
Switching frequency	60 kHz
Sampling frequency	15 kHz

.

Figure 7 shows the simulation diagrams for low input voltage and low input power operation mode. Figure 7a shows the rectifier mode, while Figure 7b shows the inverter mode. An ideal sinusoidal grid is considered. In the inverting operation, the average dc input voltage is equal to 250 V, while RMS output voltage is equal to 230 V, and input power is about 250 W. It can be seen that the input current has a continuous mode which is achieved by means of a simple input capacitor.

At the same time, its value is relatively small. In the reverse operation, the sign of reference PR controller current is changed, while the control structure remains the same.

Figure 8 demonstrates very similar simulation results for an increased input voltage (350 V) and power (850 W).

The main outcome from these figures is that simulation results correspond to the theoretical expectation. A very simple control system can provide bidirectional operation with acceptable grid current quality.

5. Experimental Verification

Figure 9 shows the experimental setup for the studied solution. It consists of an inverter PCB board, a control board and an inductor. The passive elements correspond to the simulation study.

The high switching transistors S₁, S₂ are realized on the MOSFET SiC transistor C2M0080120D along with SiC diode D₁ C3D10012A. The diode was used as an alternative solution for unidirectional operation. The unfolding circuit is based on the MOSFET transistors IPB60R060P7ATMA1. These transistors have the poor dynamic characteristics but low static losses.

All the diagrams were derived by current probes Tektronix TCP0150, and voltage probes Tektronix TPA-BNC along with the digital oscilloscope Tektronix MDO4034B-3. A general approach to the experimental verification is shown in Figure 4. A high performance power analyzer YOKOGAVA WT1800 was used for efficiency measurement.

The control system is based on a digital signal processing (DSP) controller and a low-cost field-programmable gate array (FPGA). External ADC converters were implemented to provide high accuracy. This approach is justified by the very high switching frequency of the transistors and the high-level demand of the calculation resources. As a result, the functionality is detached between the FPGA and the DSP. This test bench allows the realization of any PWM technique with a high switching frequency and high resolution. At all operation points, the switching frequency was 60 kHz.

Our experimental study was targeted to achieve several aims. First, the aim was to analyze the influence of the separate control of high switching and unfolding transistors on the zero crossing distortion. Second, the focus was on the influence of synchronous switching of transistors S₁ and S₂ on the zero crossing distortion. Finally, a detailed efficiency study was conducted.

Figure 10 shows the experimental results at low input voltage V_in = 250 V, and at low power P_in = 250 W in the inverter mode. In this case, several scenarios were tested. The first scenario (Figure 10a) corresponds to the case without synchronous switching of transistors S₁ and S₂ and without separate control of the unfolding transistors.

Figure 10a shows the output voltage in the grid-off mode, v_ab voltage before unfolding circuit, inductor i_L and input i_IN currents. As can be seen, zero crossing distortion is present. Figure 10b shows the same diagrams without synchronous switching of transistors S₁ and S₂ but with separate control; zero crossing distortion is slightly reduced but not completely eliminated.

Finally, the influence of synchronous switching was estimated. Figure 10c shows that an ideal output voltage shape is achievable in this case. It is explained by an additional discharge circuit that helps to keep the output voltage across the unfolding capacitor very close to sinusoidal shape. The THD value was estimated for all cases and confirms that the last case corresponds to the lowest value <1%.

Similar experimental results are shown in Figure 11 with increased output current. First of all, it should be underlined that an increase in power leads to a decrease in distortion, even in the worst case. Both of these figures show the open loop operation with a simple passive load.

To confirm the grid-connection operation capability, Figure 12 shows the diagrams in the grid-connected mode. It can be seen that despite current distortion, the experimental results are very similar to the simulation results. Slight distortion is caused by non-ideal laboratory grid voltage that can be improved by more sophisticated control, which is beyond the scope of this work. In this working point, THD values in all cases were less than 1%.

6. Efficiency Estimation

The efficiency profile as the function of the input power with constant input voltage is shown in Figure 13a. The open loop unidirectional mode was utilized when the transistor S₂ was replaced by a diode.

It can be seen that the characteristic has the peak value of efficiency at about 95%. The point of maximum efficiency is different at different input voltages. The solid line corresponds to 250 V, while the split line corresponds to the input voltage of 350 V. At a lower input voltage, the peak efficiency belongs to the input power of 300 W. At an increased input voltage, the maximum efficiency can be achieved with an increased input power as well.

At the same time, Figure 13b shows the dependence of the efficiency as the function of the input voltage with constant power. The power was investigated in a range from 100 W to 1000 W. The two cases are shown. In the first case, the reduced input power is 250 W. It can be seen that the peak efficiency occurs at a relatively low input voltage. A further increase in the input voltage in the constant power mode will lead to the overall efficiency decreasing. In the second case, illustrated by a split line, the power was increased to 850 W. In this case, the peak efficiency point is evidently shifted to the higher voltage.

The main conclusion is that the converter has some optimal operation point that depends on the input voltage and power level. This conclusion correlates with the theoretical losses model described above. The overall efficiency mostly depends on the conduction losses in the high-switching semiconductors and unfolding transistors. At the same time, it can be optimized for a certain operation point by means of selecting different semiconductors for high switching and unfolding circuit.

Figure 14 shows the next set of experimental tests devoted to the efficiency study in the bidirectional operation mode.

In this case, the diode was replaced by the transistor S₂. The diagrams in Figure 14 are similar to those in Figure 13. It can be seen that the efficiency profile behaves very similar to the unidirectional mode. The main difference lies in the significant efficiency increase, which in turn, is explained by the reduction of conduction losses. The maximum 96.2% efficiency is observed in this case.

Figure 15 shows pictures from the thermal camera. In the first case (Figure 15a,b) the input voltage and power were reduced, the total efficiency was about 96%. In the second case, the input power increases along with the input voltage. Figure 15c,d shows the corresponding thermal picture. The efficiency in this case was about 95%. Due to the lower efficiency and higher power, the temperature of the semiconductors was significantly higher as well. Figure 15a,c corresponds to the high switching semiconductors, while Figure 15b,d corresponds to the unfolding transistors. At the same time, it can be seen that all semiconductors have an acceptable temperature up to 90 °C.

Another important conclusion is that losses across the high switching transistor S₁ are larger than losses across the high switching transistor S₂. It directly confirms that efficiency increases in case a diode is replaced by a transistor for a bidirectional operation. It is especially evident for the first case when the boost mode is applied and the conduction time of the transistor S₁ is significantly larger.

The losses can be split and estimated separately taking into account datasheet parameters and current in semiconductors. Figure 16 shows the loss distribution for the operation point discussed above.

Conduction losses have a major contribution in both cases. It is evident that conduction losses increase as the input current increases.

The main conclusion from the efficiency study and the thermal pictures is that a converter may have high efficiency in a wide range of input voltage. The efficiency of 96% can be achieved without any extraordinary semiconductors or an interleaving approach. At a constant input current profile, the maximum efficiency does not correspond to the maximum voltage, which perfectly suits the PV profile. At the same time, this solution can be optimized for a certain input voltage level and bidirectional operation that in turn, means good applicability for battery storage interfacing.

In contrast to conventional solutions, reduced switching losses and EMI are expected since only two semiconductors are involved in the high switching performance.

7. Conclusions

This paper has presented a novel bidirectional twisted buck-boost converter based on the inverting buck-boost circuit and output unfolding circuit in the grid-connected mode. Component design guidelines, along with possible control strategies are given. Simulation and experimental results are confirmed by the theoretical analysis.

The overall efficiency can be very high because only two transistors are involved in high switching performance in any period of operation. Also, it may give benefits in reduced EMI compared to any other competitive solution.

It is demonstrated that a typical problem encountered in an unfolding circuit-based solution that consists in zero voltage distortion can be solved by a simple approach. Synchronous switching of the transistors along with proper control of unfolding transistors enables elimination of the zero crossing distortion. At the same time, synchronous switching leads to higher efficiency.

Also, it is demonstrated that the main advantage of this solution is simplicity, in the ability to work in a wide range of input voltages with high efficiency and high flexibility of the optimal operation point tuning. On the one hand, the maximum input voltage is limited by the maximum voltage stress across high-switching semiconductors. On the other hand, the high-voltage high-switching MOSFET transistor is a verified technology that enables reduction of price and removal of any serious challenges.

As a result, taking into account that efficiency for higher boost is not decreasing, it can be recommended for applications with PV arrays or storage batteries.