Adaptive Stabilization and Dynamic Performance Preservation of Cascaded DC-DC Systems by Incorporating Low Pass Filters

Abstract

This paper proposes a method to stabilize and enhance the dynamic performance of a cascaded DC-DC system by adaptively reshaping the source output impedance. The method aims to reduce the ratio of the source output impedance to the load input impedance, referred to as the minor loop gain, to eliminate the interaction between the load and the source systems. This interaction can deteriorate the dynamic performance or might lead to instability. Thus, the bus current is used to improve the dynamic performance by reducing the magnitude of the source’s output impedance adaptively according to the loading condition such that the dynamic performance is consistently improved. Utilizing the bus current facilitates the compatibility between the proposed controller and most widely used DC-DC converters controlled in voltage mode, including non-minimum phase converters. In addition to the flexibility the bus current provides to embed the proposed solution with conventional control schemes. Experimental results have validated the effectiveness of the proposed controller along with time-based simulation and theoretical analysis, for minimum and non-minimum phase converters.

1. Introduction

Cascaded DC-DC systems have been widely used in aerospace, maritime, and automobile industries due to their attractive features such as modularity, scalability, high power density, and high reliability [1]. They provide a flexible environment to efficiently integrate renewable energy resources with the existing power systems [2,3]. Typically, a cascaded system consists of a line regulating converter (LRC) [4], which acts as the source, connected in series with a load subsystem, as shown in Figure 1. The load system might consist of DC-DC converters, inverters, or a combination connected in parallel [5]. Since most load converter modules are tightly regulated and supply a load with one-to-one characteristic of voltage-to-current or speed-to-torque relationships [6,7], these modules act as constant power loads (CPL). CPLs exhibit a negative incremental impedance seen by the LRC [8]. This characteristic is notorious for degrading the dynamic performance of cascaded systems and might lead to instability [9].

Assessing the stability and the dynamic performance of cascaded DC-DC systems was initiated by R.D. Middlebrook in 1976, who studied the impact of the input filters on the stability and on the performance of regulated DC-DC converters [8]. His study resulted in the Middlebrook criterion, which ensures the stability and performance of cascaded systems. It is based on relating the ratio of the source output impedance to the load input impedance, which is called the minor loop gain ($T_m(s)=Z_o(s)/Z_{in}(s)$) in Figure 1), to system stability properties. The criterion is deemed to be very conservative [3], and requires infinite phase margin. Consequently, high capacitance is needed at the DC bus to achieve the required phase margin. Those requirements are impractical because they reduce the power density of cascaded systems, which is not desirable for most applications. To relax the conservativeness imposed by the Middlebrook criterion, other criteria have been proposed in the literature such as the Gain Margin Phase Margin (GMPM) [10], the Opposing Argument [11], and Energy Source Analysis Consortium (ESAC) [12], which in various ways confine the polar plot of $T_m$ in a specific region of the complex plane to guarantee acceptable dynamic performance [2,13]. All these criteria assume that the load and the source converters are standalone stable. The Three-Steps criterion was introduced in [14] to assess the stability of cascaded systems even if the source converter was standalone unstable. In addition, the Passivity-Based criterion was introduced in [15] to further relax the artificial conservativeness of designing cascaded systems. It examines the stability of a cascaded system by injecting current into the DC bus to determine the passivity of the bus impedance. Bus impedance passivity would ensure stability. All of the above mentioned criteria provide sufficient conditions to ensure stability or dynamic performance, so their violation does not necessarily mean instability.

It is desirable to implement the system of Figure 1 in a modular and scalable manner, such that it can host various load and source subsystems from different vendors [2]. However, these miscellaneous components have different dynamic properties and ensuring stability with satisfactory performance of such an assorted system is a challenging task. Hence, passive damping methods have been proposed to preserve the stability and to improve the dynamic performance of such a system. Using passive components to damp out system oscillations incurs inevitable power loss that reduces the overall efficiency. In addition, passive damping reduces the power density of the system by including bulky passive components.

Active damping methods were introduced to overcome the passive damping disadvantages [1,9,16]. In this approach, stability is ensured by modifying the control loop of the LRC or the load system. However, in the existing active damping methods, little attention has been given to preservation or improvement of system dynamic behavior, and it is typically compromised in favor of ensuring system stability. The existing solutions for enhancing the dynamic performance are either applicable to a single load converter, or limited to a particular configuration of source (LRC) DC-DC converter. In [17], the stability of the system has been exclusively ensured for buck converters, as the LRC, via adding extra feedback loops to modify the inductor’s series resistance. Although the system stability is guaranteed, the dynamic performance of the system is not improved because the system dynamics are changed while the controller has not been modified to accommodate that. In [18], the Middlebrook criterion was partially fulfilled; the stability condition has been met by inserting a virtual resistance in series with the load via feeding back the bus current into the controller. The performance requirement of the Middlebrook criterion was neglected. Moreover, a second controller is required to compensate for the voltage drop across the DC bus, which may introduce other stability and performance issues. In [19], the magnitude or the phase of the load’s input impedance is modified to prevent the interaction between the load and the source subsystems where the impedance overlap occurs using a band pass filter based on a method in [20]. It is achieved by inserting a virtual resistance either in series or in parallel with the load subsystem. The relative stability margins will be affected in that region, while the solution requires modifications for every converter that would be connected as a load.

In [21,22], an adaptive virtual capacitor connected to the DC bus is proposed to stabilize the system; the solution results in power density reduction because the virtual capacitor is implemented using an additional auxiliary converter, making it less desirable for density-sensitive applications. In reference [22], a method to improve the dynamic performance of a cascaded system that consists of a single DC-DC converter as the load was introduced. The proposed solution cannot handle multiple load converters operating in parallel. The authors of reference [23] proposed a method to design both source and load controllers simultaneously, such that their interaction is minimized. Similar to [22], the proposed method is solely valid for a single load DC-DC converter. The vast majority of the above mentioned active damping methods were introduced, and tested to stabilize minimum phase converters, e.g., buck converters, while the non-minimum phase converters have not received much attention in this sense.

To devise a method for ensuring stability and performance of cascaded DC-DC systems with multiple loads and to address the discussed issues, we propose a method that reshapes the output impedance of the LRC to stabilize the system and improve its dynamic performance. The proposed method is applicable to minimum and non-minimum phase converters, and it neither incurs additional power losses nor changes the LRC controller parameters. Additionally, it is applicable to linearized feedback control schemes, without changing the controller parameters. The method is based on adaptively reducing the magnitude of the source output impedance by feeding back the average value of the bus current. Consequently, the output impedance is reduced depending on the loading condition. Reducing the output impedance helps eliminate the interaction between load and source systems, and effectively decouples these two.

This paper first discusses the stability and performance issues of cascaded systems in Section 2. Then the proposed controller is explained in Section 3. The compatibility of the proposed controller with minimum and non-minimum phase converters is discussed in Section 4 and Section 5, respectively. Finally, the conclusions are drawn in Section 6.

2. Stability and Performance of Cascaded DC-DC Systems

The stability and performance of cascaded DC-DC systems are deteriorated by the incremental negative impedance exhibited by the load subsystem. The negative impedance appears to be due to the active nature of the load subsystem, which tightly regulates its output voltage while delivering a constant amount of power despite the variation in the input voltage. The mathematical derivation of the negative input impedance [24,25], is

$$r=\frac{\partial V_{bus}}{\partial I_{bus}}=\frac{\partial }{\partial I_{bus}}(\frac{P_{bus}}{I_{bus}})=-\frac{P_{bus}}{I_{bus}^2}=-\frac{V_{bus}}{I_{bus}}$$

(1)

where r is the load low frequency impedance, $V_{bus}$ is the DC bus voltage, and $I_{bus}$ is the DC bus current. Equation (1) can be related to the bus voltage and output power of each load converter ($P_{oi}$), assuming lossless converters [26], as

$$r=-\frac{V_{bus}^2}{{\sum }_1^n{P}_{oi}}$$

(2)

where n is the number of loads. Equations (1) and (2) are valid for the frequencies that are less than the cut-off frequency of the load converter (${\omega }_c$) [8], where the impedance is $\left|r\right|\angle {180}^{\circ }$. Beyond ${\omega }_c$, the load input impedance resembles an inductor impedance. Typical plots of the source output impedance $Z_o$ and the load input impedance $Z_{in}$ are shown in Figure 2, [13,24,27]. The proposed stabilization method depends on the maximum frequency (${\omega }_{i,max}$) of the interaction region, as illustrated in Figure 2.

The roles of $Z_o$ and $Z_{in}$ in assessing the stability of cascaded systems can be visualized using the characteristic equation of distributed DC systems [10,27] as

$$\frac{v_{o,i}}{v_{in}}=\frac{G_{vds}{G}_{vdl,i}}{1+T_m}$$

(3)

where $v_{o,i}$ is the ith load output voltage, $v_{in}$ is the source converter input voltage, $G_{vds}$ is the source converter control to output transfer function, and $G_{vdl,i}$ is the ith load converter control to output transfer function. For multiple loads, the input impedance of the load system is the parallel combination of each load module input impedance, i.e., $Z_{in}=Z_{i1}\parallel Z_{i2}\parallel Z_{i3}\parallel \cdots$.

To determine stability properties of the cascaded system, Nyquist criterion is used [13,16]. Stability is preserved if the polar plot of $T_m(s)$ does not encircle $(-1,j0)$. An impedance overlap in the low-frequency region ($\omega <{\omega }_c$) implies $|T_m|\ge 1$ and $\angle T_m(s)>$${180}^{\circ }$, consequently the polar plot of $T_m(s)$ will encircle $(-1,j0)$.

Source and load subsystems interaction alters the dynamic performance of the overall system. As a result of this interaction, the source control loop gain ($T_s$) is altered [28,29] as

$$T_s^L=\frac{T_s}{1+\underset{T_m}{\underbrace{\frac{Z_o}{Z_{in}}}}(1+T_s)}$$

(4)

where $T_s$ and $T_s^L$ are the original and load affected control loop gain of the LRC, respectively. The LRC dynamic performance stays intact from the loading effect iff $Z_o\ll 1$, consequently $T_s^L\approx T_s$ in Equation (4). Moreover, if $T_m$ encircles $(-1,j0)$, so does $T_s^L$ [16,29]. On the other hand, the dynamic performance of the load is degraded by the source according to

$$T_L^S=T_L\frac{1+T_m}{1+\frac{Z_o}{Z_{in\_o}}}$$

(5)

where $Z_{in\_o}$ is the open-loop input impedance impedance of the load converter, $T_L$ is the load converter control loop gain, and $T_L^S$ is source affected control loop gain of the load. Similarly, the load dynamic performance will be preserved iff $Z_o\ll 1$, which implies $T_L^S\approx T_L$ in Equation (5). Since reducing $Z_o$ helps decouple the dynamics of source and load systems, we propose to reduce the magnitude of the source output impedance based on

$$Z_o^{new}=\frac{Z_o}{1+\rho }\rho >0$$

(6)

where $\rho$ is a positive constant. Having ($1+\rho$) as the divisor is justified in the next section. Using Equation (6) the minor loop gain can be re-expressed as

$$T_m=\frac{Z_o}{(1+\rho )Z_{in}}$$

(7)

Increasing $\rho$ reduces the magnitude of $Z_o^{new}$, and consequently reduces $|T_m|$, which implies $T_s^L\approx T_s$ and $T_L^S\approx T_L$. Thus the source and the load systems are decoupled, and the Middlebrook criterion of ensuring stability and preserving the dynamic performance is satisfied without artificial conservativeness.

3. The Controller Design

The proposed controller aims to adaptively stabilize and preserve the dynamic performance of cascaded DC-DC converters without changing the LRC controller parameters. To do so, $T_s$ must stay intact from the loading effect as discussed earlier, and $Z_o$ must be reshaped adaptively according to the load conditions. In addition, the closed-loop transfer function of reference voltage to output voltage (${\tilde{v}}_o/{\tilde{v}}_{ref}$) should stay as ($T_s/(1+T_s)$).

In references [30,31], a controller that preserves (${\tilde{v}}_o/{\tilde{v}}_{ref}$) relationship, and reshapes the output impedance of single phase inverters or multi-input-dual-active-bridge DC-DC converters was introduced, as shown in Figure 3. We propose modifications to this controller such that the output impedance is adaptively shaped according to Equation (6). The small-signal output voltage (${\tilde{v}}_o$) of a DC-DC converter equipped with the controller of Figure 3 is expressed as

$${\tilde{v}}_o={\tilde{v}}_{ref}\frac{T_s}{1+T_s}-{\tilde{i}}_o\frac{Z_{o\_o}}{1+H{G}_{vd}{G}_{PWM}}+{\tilde{v}}_g\frac{G_{vg}}{(1+T_s)(1+H{G}_{vd}{G}_{PWM})}$$

(8)

where ${\tilde{i}}_o$, ${\tilde{v}}_g$ are the variations in the output current and input voltage, respectively. The coefficient H is used to shape $Z_o$, $G_{vg}$ is the input to output transfer function, $T_s=G_c{G}_{vd}{G}_{PWM}$, $G_c$ is the original controller, $Z_{o\_o}$ is the open loop output impedance of the source, and $Z_o=Z_{o\_o}/(1+T_s)$. $G_{PWM}$ is assumed unity hereinafter, for the sake of simplicity.

3.1. The Proposed Reshaping

To achieve the proposed reshaping of the output impedance according to Equation (6), the denominator $1+H{G}_{vd}$ in Equation (8) should equal $1+\rho$ [32]. Choosing H to be $\rho G_{vd}^{-1}$ is an obvious option, yet it is a non-realizable choice. $G_{vd}$ is a strictly proper transfer function for DC-DC converters. Thus, $G_{vd}^{-1}$ yields more zeros than poles, emulating an anticipatory system. We propose to realize $G_{vd}^{-1}$ in a certain frequency range using the transfer function of a low pass filter with unity DC gain

$$G_{LPF}=\frac{{\omega }_x^p}{{(s+{\omega }_x)}^p}$$

(9)

where ${\omega }_x$ is the corner frequency in rad/s, and p specifies the order of the filter. $G_{vd}^{-1}$ is practically realized as

$$G_R=G_{vd}^{-1}\frac{{\omega }_x^p}{{(s+{\omega }_x)}^p}$$

(10)

The coefficient p depends on LRC control-to-output transfer function and is selected such that Equation (10) is always realizable for DC-DC converters. Thus, Equation (6) is achieved by setting H equals to

$$H=\rho G_R$$

(11)

Consequently, ($1+H{G}_{vd}$) in Equation (8) can be interpreted as ($1+\rho$) $\forall \omega \le {\omega }_x$. Hence, $Z_o^{new}$ in Equation (6) can be practically realized as a function of $\rho$ as

$$\begin{array}{cc}\hfill Z_p(\rho )& =\frac{Z_o}{1+\rho G_R{G}_{vd}}\hfill \\ & =\frac{Z_o}{1+\rho }\forall \omega <{\omega }_x\hfill \end{array}$$

(12)

where $Z_p(\rho )$ is the output impedance of the LRC corresponding to the proposed controller, referred as the proposed output impedance hereinafter. $Z_p(\rho )$ does not require any change to the controller parameter while the desired response of ${\tilde{v}}_o/{\tilde{v}}_{ref}$ and the dynamic performance are preserved. In addition, it is applicable to linearized feedback control configuration, not limited to PI controllers only as in [30] or a specific converter as in [20]. The final shape of the source converter output impedance using (12) compared to $Z_o$, which corresponds to the original controller, is shown in Figure 4, where ${\omega }_x=1\times {10}^5$ rad/s. Ultimately, substituting Equation (12) into Equation (8) expresses the output voltage of a DC-DC converter that utilizes the controller with the proposed modifications as

$${\tilde{v}}_o={\tilde{v}}_{ref}\frac{T_s}{1+T_s}-{\tilde{i}}_o\frac{Z_o}{1+\rho }+{\tilde{v}}_g\frac{G_{vg}}{(1+T_s)(1+H{G}_{vd})}\omega <{\omega }_x$$

(13)

3.2. The Adaptivity

Evidently, any $\rho >0$ in Equation (12) will reduce the output impedance of the LRC. To make the proposed technique adaptive to load changes, we propose to use the average bus current

$$I_{bus}=\frac{1}{V_{bus}}(P_{o1}+P_{o2}+P_{o3}+...)$$

(14)

in Equation (12) such that $\rho =I_{bus}$. The bus current is used because it makes the proposed control adaptive to load changes. In addition, it equips the controller with the flexibility required to integrate it with minimum and non-minimum phase DC-DC converters. Thus, replacing $\rho$ by $I_{bus}$ in Equation (12) reduces $Z_p(\rho )$ adaptively by a factor of ($1+I_{bus}$) at various loading conditions. Figure 5 shows the practical implementation of the proposed controller.

3.3. Determining the Low Pass Filter Corner Frequency

Selecting ${\omega }_x$ is vital in successfully implementing the proposed controller. The interaction between the source and the load subsystems tends to occur around the LRC peak output impedance [13,16,24]. Thus, ${\omega }_x$ should be selected as

$${\omega }_x>{\omega }_{i,max}$$

(15)

where ${\omega }_{i,max}$ is shown in Figure 2. Selecting ${\omega }_x<{\omega }_{i,max}$ will neither stabilize the system nor preserve the dynamic performance because $Z_p(\rho )=Z_o,\forall \omega >{\omega }_x$, as shown in Figure 4.

3.4. Modification for Non-Minimum Phase Converters

Non-minimum phase converters are featuring right-half-plane (RHP) zero(s) in their control-to-output transfer functions ($G_{vd}$). Boost, buck-boost, fly-back and Cũk converters are typical examples of the non-minimum phase converter family. As a result, inverting their $G_{vd}$ yields unstable poles in the proposed controller. Although Equation (12) implies that the unstable poles in ($G_{vd}^{-1}{G}_{vd}$) would be canceled by the RHP zeros, it is misleading. Unstable pole-zero cancellation violates the internal stability of the system [33], so the controller will still be unstable despite the cancellation.

The unstable poles impediment can be addressed by the proposed controller, which depends on the magnitude of $G_{vd}$ to reshape the source output impedance. Hence, we propose to replace the RHP zeros of $G_{vd}$ by their left-half-plane (LHP) mirrors to obtain the modified control-to-output transfer function ($G_{vdm}$) for non-minimum phase converters. The magnitudes of $G_{vd}$ and $G_{vdm}$ are the same [34]. $G_{vdm}$ will have a different phase response compared to $G_{vd}$, which will not impact our scheme as it mainly depends on the magnitude. $\rho$ is a DC value, so the phase response of H in Equation (11) would have no impact on the proposed impedance reduction method. It solely manipulates the magnitude of the output impedance. $G_R$ in Equation (10) can be re-expressed for non-minimum phase converters as

$$G_R=G_{vdm}^{-1}\frac{{\omega }_x^p}{{(s+{\omega }_x)}^p}$$

(16)

while Equations (11)–(13) hold.

4. Minimum-Phase Cascaded System

4.1. Theoretical Analysis

A test system consisting of a buck converter, as the (LRC), and two loads has been designed to validate the performance of the proposed controller. Figure 6 shows the system schematic diagram, and

Table 1. Numerical parameters of the test system.

Parameter	Source	Load A	Load B
$V_{in}$	20	7	7
$V_o$	7	4	4
$L(uH)$	510	390	400
$r_L()$	0.05	0.01	0.04
$C(uF)$	697	697	697
$r_C(\mathsf{\Omega })$	0.1	0.1	0.1
$R_{load}(\mathsf{\Omega })$	⋯	2	2
$f_{switching}(KHz)$	100
$V_{PWM}(V)$	1
Source Controller
$Gc$	$0.001+{\displaystyle \frac{18}{s}}$

tabulates its parameters. The loads’ controllers are described by Equation (A1) in the Appendix A.

The LRC was designed to supply two load converters, however, an impedance overlap occurs while supplying full load using the original controller, as shown in Figure 7. Supplying a single converter ($50\%$ of the load) degraded the dynamic performance by lowering the gain margin of the LRC from 6.12 dB (≈20${\log }_{10}$(1/0.49)) to 3.09 dB (≈20${\log }_{10}(1/0.7)$), as depicted in Figure 8. Moreover, the system become completely unstable after adding the second load, when $T_s^L$ encircles $(-1,j0)$.

To validate the proposed controller, its corresponding LRC output impedance ($Z_p(\rho )$) is compared to the LRC impedance induced by using the original controller, $Z_o$, in Figure 9 at full load condition. ${\omega }_x$ was selected to be $1\times {10}^5$ rad/s. $Z_o$ had a peak impedance of $12.7$ dB$\mathsf{\Omega }$ ($4.32\mathsf{\Omega }$), while $Z_p(\rho )$ had $1.77$ dB$\mathsf{\Omega }$ ($1.23\mathsf{\Omega }$). The difference between them is $10.93$ dB$\mathsf{\Omega }$ which corresponds to ($1+I_{bus}$), where $I_{bus}=2.52$ A.

As $Z_p(\rho )$ decreases while increasing the output power, the poles of the loaded system ($T_s^L/(1+T_s^L)$) move towards the poles of the unloaded system ($T_s/(1+T_s)$), as illustrated in Figure 10. Consequently, the loading impact is reduced. Hence, the dynamic performance is improved. Figure 11 compares the impact of loading on $T_s$ using the original controller verses the proposed controller. The system was unstable while supplying $100\%$ of the load using the original controller. In contrast, the proposed modifications not only stabilized the system, but also were able to improve the dynamic performance. The LRC gain margin improved to $4.42$ dB using the proposed controller compared to $-3.88$ dB using the original controller, as displayed in Figure 11.

4.2. Simulation Case Studies

The system described in Figure 6 was simulated using PLECS Standalone software package (Plexim, Zürich, Switzerland) to verify the effectiveness of the proposed controller in order to adaptively reshape the source output impedance, and to improve the overall dynamic performance. The system with its original controller (depicted in Figure 3) was simulated to demonstrate the impact of loading on its stability. Figure 12a shows connecting Load_A caused substantial oscillations in the bus voltage due to the loss of 3.09 dB of gain margin, as expected from Figure 8. After 200 ms Load_B was connected, which completely destabilized the bus voltage. Despite the oscillations in the bus voltage, the output voltages of both loads were stable. Reference [35] explains this phenomena as every load controller was able to successfully track its input voltage due to their high bandwidth.

The performance of the proposed controller to stabilize and enhance the relative stability margins was then assessed. Load_A was connected first, and the dynamic response of the bus voltage was highly improved, as illustrated in Figure 12b. The settling time was substantially reduced from 100 ms, in Figure 12a, to 25 ms. Connecting load_B, after 200 ms, has neither destabilized the system nor degraded its dynamic performance.

To further demonstrate the effectiveness of the proposed controller, both loads were connected simultaneously to the DC bus. The original controller was unable to handle both loads, as shown in Figure 13a. Figure 13b demonstrates the capability of our controller, which stabilized the system in 25 ms.

4.3. Experiment

To validate the effectiveness of the proposed controller experimentally, the system in Figure 6 was built in the laboratory, as shown in Figure 14.

Two digital control platforms, using NI-cRIO systems ( National Instruments, Austin, TX, USA), were employed. One NI-cRIO was used to implement the LRC controller including the proposed method and the other one realizes two voltage controllers for two load converters. The selected sampling rate was 30 kHz, and the discrete transfer functions such as

$$\frac{y(z)}{x(z)}=\frac{n_3{z}^3+n_2{z}^2+n_{1}z+n_0}{z^3+d_2{z}^2+d_{1}z+d_0}$$

(17)

were realized using Normal Direct Form II (NDF-II) [36], as illustrated in Figure 15.

Two tests were conducted to verify the effectiveness of the proposed controller. For the first test, the load converters were sequentially connected to the DC bus such that load_B connects to the system 200 ms after Load_A. For the second test, the load converters were simultaneously connected to the DC bus.

4.3.1. Sequential Connection

Figure 16a shows the response of the system with the original controller to show its inability to handle the entire load, where $V_{oA}$ and $V_{oB}$ denote the output voltages of loads A and B, respectively. Connecting Load_A caused a decaying oscillatory response for 100 ms. Then, integrating load_B totally destabilized the bus voltage. As discussed earlier, the output voltages of the loads were stable.

Figure 16b shows the enhancement in the dynamic performance accomplished by the proposed controller. Connecting Load_A created oscillations in the bus voltage for 40 ms, showing 60% improvement in the settling time compared to Figure 16a. The reduction in the settling time implies that the poles of the system have moved towards the original system’s dominant poles, as shown in Figure 10. Then, connecting load_B caused negligible oscillations because the new gain margin is 4.2 dB compared to $-3.88$ dB, as shown in Figure 11.

4.3.2. Simultaneous Testing

The effectiveness of the proposed controller to stabilize and improve the dynamic performance while connecting the two loads simultaneously is verified in this case study. Figure 17a shows connecting the two loads without the proposed modification destabilizes the bus voltage. Then, the proposed controller was implemented, and it was able to stabilize the system in 50 ms, as shown in Figure 17b, which proves the ability of the introduced method to stabilize and enhance the dynamic performance.

5. Non-Minimum Phase Cascaded System

5.1. Theoretical Analysis

Another prototype consisting of a boost converter, as the LRC, supplying a buck converter was designed, as shown in Figure 18. This prototype is studied to validate the capability of the proposed controller in controlling non-minimum phase converters.

Table 2. Numerical parameters of the test system in Figure 18.

Parameter	Boost	Buck
$V_{in}$	5	7
$V_o$	7	3.6
$L(uH)$	930	390
$r_L(\mathsf{\Omega })$	0.05	0.01
$C(uF)$	697	697
$r_C(\mathsf{\Omega })$	0.1	0.1
$R_{load}(\mathsf{\Omega })$	⋯	1.4
$f_{switching}(KHz)$	100
$V_{PWM}(V)$	1

tabulates the parameters of the system, where the source controller is (0.005 + 13.2/s) and the load controller is described by Equation (A2) in the Appendix A. The load converter was designed to supply $9.25$ W. However, an impedance overlap occurs, as seen in Figure 19, that destabilizes the bus voltage.

The boost converter control-to-output transfer function is described by

$$G_{vd}=0.56{\displaystyle \frac{(s-1.435\times {10}^4)(s+657.9)}{s^2+339.5s+7.871\times {10}^5}}$$

(18)

which has a RHP zero, and is modified to

$$G_{vdm}=0.56{\displaystyle \frac{(s+1.435\times {10}^4)(s+657.9)}{s^2+339.5s+7.871\times {10}^5}}$$

(19)

$G_{vdm}$ and Equation (16) were used to shape the output impedance of the boost converter. ${\omega }_x$ was chosen to be ${10}^5$ rad/s because the impedance overlap occurred at $\omega ={10}^3$ rad/s, as Figure 19 depicts. As a result, the reshaped output impedance of the boost converter, using Equation (19), is shown in Figure 20, which highlights the ability of the proposed method to reshape the output impedance of the non-minimum phase converters. In addition, Figure 21 shows the unloaded loop gain ($T_S$), the unstable loop gain ($T_S^L$) due to the loading impact, and the improved loop gain using the proposed controller ($T_I$).

5.2. Simulation Case Studies

The system described in Figure 18 along with its parameters in Table 2 was simulated to verify the effectiveness of the proposed controller to stabilize a non-minimum phase converter. The test was performed by supplying $70\%$ of the load. Then, the remaining $30\%$ was connected at $t=0.2$ s. Figure 22a shows that the bus voltage has become unstable at the full load condition using the original controller.

Next the system was equipped with the proposed controller, and the test was preformed again. Adding the load at $t=0.2s$ did not compromise the stability of the system. The bus voltage suffered from neither permanent oscillations nor a long settling time. Hence, the simulation validates the effectiveness of the proposed controller, and the proposed modification of $G_{vd}$ to stabilize a non-minimum phase converter.

5.3. Experiment

The analytical and simulation results were further validated by experiments. A single NI-cRIO digital platform controller, with a sampling rate was of 30 kHz, was used to control the entire system of Figure 18. The digital transfer functions, such as Equation (17) were realized, as demonstrated in Figure 15.

The test was run first to demonstrate the inability of the original controller to preserve the bus voltage stability at full load condition, as shown in Figure 23a. The impact of the impedance overlap is evident. Thus, the proposed controller was implemented to decouple the impedance interaction, and the test was run again. The bus voltage stability was preserved, as Figure 23b depicts, so the experimental results are in agreement with the analytical and simulation outcomes. Collectively, these results validate the effectiveness of the proposed controller to stabilize and improve the dynamic performance of non-minimum phase converters.

6. Conclusions

This paper presents a method to stabilize and enhance the dynamic performance of cascaded DC-DC systems by reducing the magnitude of the source output impedance adaptively. The proposed controller is applicable to minimum and non-minimum phase converters that employ linearized feedback control schemes. In addition, the method can handle single or multiple loads. This flexibility is achieved by utilizing the average value of the bus current to reduce the magnitude of the source output impedance by the factor of ($1+I_{bus}$). The problem of reciprocating the control-to-output transfer function of DC-DC converters is solved by utilizing a low pass filter in order to realize the inversion in a certain frequency range. However, the RHP zeros of non-minimum phase converters cause instability if the corresponding transfer function is reciprocated as a result of introducing unstable poles to the system, which has been solved by mirroring the RHP zeros about the imaginary-axis of the complex plane.

Assessing the effectiveness of the controller is carried out by mathematical analysis, simulation, and experiments. All of the analyses results are in agreement and validated the satisfactory performance of the proposed control. Implementing the proposed controller could improve the relative stability margins of the studied systems. It is noteworthy that filtering the bus current introduces delay, which might prolong the settling time if the introduced delay was substantial. In addition, the discrete transfer functions are implemented practically by NDF-II, which produces the closest experimental outcomes to the simulation and to the theoretical results.