Studies on a Hybrid Full-Bridge/Half-Bridge Bidirectional CLTC Multi-Resonant DC-DC Converter with a Digital Synchronous Rectification Strategy

Abstract

This study presents a new bidirectional multi-resonant DC-DC converter, which is named CLTC. The converter adds an auxiliary transformer and an extra resonant capacitor based on a LLC resonant DC-DC converter, achieving zero-voltage switching (ZVS) for the input inverting switches and zero-current switching (ZCS) for the output rectifiers in all load range. The converter also has a wide gain range in two directions. When the load is light, a half-bridge configuration is adopted instead of a full-bridge configuration to solve the problem of voltage regulation. By this method, the voltage gain becomes monotonous and controllable. Besides, the digital synchronous rectification strategy is proposed in forward mode without adding any auxiliary circuit. The conduction time of synchronous rectifiers equals the estimation value of body diodes’ conduction time with the lightest load. Power loss analysis is also conducted in different situations. Finally, the theoretical analysis is validated by a 5 kW prototype.

1. Introduction

With advantage of ZVS + ZCS, the bidirectional resonant DC-DC converter (BRDC) is gaining more attention in DC distribution system or DC microgrid applications [1,2,3,4,5,6,7,8]. All the power switching devices, including metal oxide semiconductor field effect transistor (MOSFET) switches and diodes have the desirable soft-switching features, and the switching loss is greatly decreased. In addition, the electromagnetic interference (EMI) is also restricted. As a result, BRDCs are characterized by high efficiency, high power density and low EMI, and are applicable to high frequency applications [9,10]. Among all the BRDCs, the bidirectional series resonant converter (BSRC) is a candidate topology [11,12,13,14,15,16]. All the switches of a BSRC work in either ZVS or ZCS for a wide variation of voltage gains with phase-shift control [13]. A novel control scheme was developed for BSRC in discontinuous mode [14]. With the accumulation of energy packets to raise output voltage, it is possible to have a gain greater than one. A novel method for analyzing the frequency response is also presented based on a mixture of the Fourier and the average state-space methods [15]. The analysis method provides enough information to properly control the BSRC. A BSRC using a continuous current mode was proposed in [16]. Experimental results from a 6 kW prototype validated the theoretical analysis, and higher efficiency is obtained compared to the phase-shift DAB in a wide power range. However, the efficiency is not ideal for the whole frequency range. A bidirectional LLC resonant DC-DC converter is also a good option. A bidirectional three-level LLC resonant converter has a very wide voltage gain range with PWAM control [17]. It overcomes the limitation of voltage gain in LLC resonant converters. A bidirectional LLC resonant converter with automatic forward and backward mode transition is proposed in [18]. An auxiliary inductor is added to raise the voltage gain in backward operation. Based on LLC, a symmetrical bidirectional CLLC resonant converter was recently proposed [19,20,21]. The voltage gain in backward operation is the same as that in forward operation. However, with the growth of output power and voltage conversion ratio, the resonant inductance is small and the resonant capacitance is big. These parameters are hard to design.

Besides, the regulation capability of a resonant DC-DC converter is weak under light load conditions. Due to parasitic parameters in the resonant tank, the output voltage goes up as the switching frequency increases, and an upturn drifting occurs in the voltage gain curve [22]. This phenomenon causes trouble for voltage regulation under light load conditions. To solve this problem, many researchers have changed the control method for light load conditions [23,24,25,26,27,28]. Burst mode is used in [23,24], but the ripple of the output voltage is large and the dynamic response is slow. The phase-shift and PWM control methods are effective in [25,26,27,28], but the control scheme is complex due to the additional control elements. The changes are also conducted with the topology of resonant DC-DC converter. Adding an additional output capacitor to switches can reduce current ripple and decrease powering transmitted between two sides of transformer [29], but the ZVS range this time is narrow. An additional capacitor is paralleled with the resonant inductor to improve the gain characteristics in [30]. ZVS is acquired under entire load condition, and efficiency is improved with less turn-off loss, but the design of the transformer and additional capacitor is complex due to resonance between leakage inductor and the additional capacitor.

The synchronous rectification (SR) strategy for resonant converters is also important toward achieving working efficiency [31,32,33,34]. A novel driving scheme with a compensation network for synchronous rectifiers is used in LLC resonant converters. The conduction loss and switching loss are also reduced considerably [35]. A hybrid driving scheme for full-bridge SR is proposed in [36]. It uses one transformer auxiliary winding to drive two high-side SR switches and a simple current transformer (CT) to drive two low-side SR switches. The proposed method operates well under DCM and CCM conditions. A novel SR control strategy is developed, through accurately tracking the target switching moments in [37]. However, the strategies above are complex in application and they are not verified in BRDCs. A new synchronous rectification strategy, which is simpler and compatible to bidirectional power flow, needs to be developed.

In this study, a new bidirectional CLTC multi-resonant DC-DC converter is proposed. As Figure 1 shows, the converter is composed of a high-voltage side (HVS) full-bridge, low-voltage side (LVS) full-bridge and a multi-resonant tank. An auxiliary transformer T₂ and an extra resonant capacitor C_r2 are added on bidirectional LLC resonant DC-DC converter, so the converter is named by CLTC. The gain range in two directions is broadened with the added devices. ZVS for the input inverting switches and ZCS for the output rectifiers are realized in all load range. U_H represents HVS DC voltage, while U_L represents LVS DC voltage. Power flows in both forward and backward mode are modulated with pulse frequency modulation (PFM). In forward mode, S₁ & S₄ and S₂ & S₃ run with 50% duty cycle, the rectifier switches S₆ & S₇ and S₅ & S₈ are driven by the SR signals. In backward mode, S₆ & S₇ and S₅ & S₈ run at 50% duty cycle, S₁ & S₄ and S₂ & S₃ don’t work, diodes on HVS realize SR.

This paper is organized as follows: the operation principles and characteristic descriptions of the proposed converter are discussed in Section 2. Hybrid full-bridge/half-bridge configuration is used to improve the light load regulation capability in Section 3. Stresses of power devices, load and working frequency range in half-bridge CLTC are also given to prove the feasibility of the half-bridge configuration. SR strategy based on estimation of the diodes’ conduction time is proposed in Section 4. Power loss distribution and comparison tests are conducted with different loads and LVS DC voltages in Section 5. A 5 kW prototype is built with HVS voltage of 400 V and LVS DC voltage of 42–58 V. Experimental results are shown to validate the theoretical analysis above in Section 6. Conclusions are drawn in Section 7.

2. Operation Principles and Characteristic Description

In this section, the main operation principles of CLTC multi-resonant converter are given. It is similar to a LLC resonant converter as two stages of resonance exist. The resonant frequency, voltage gain and ZVS characteristic are analyzed, forming research foundations for the following sections.

2.1. Operation Principles

Figure 2 shows different states of the CLTC multi-resonant converter. In Figure 2, i_Lm1 is excitation current of transformer T₁ on HVS, i’_Lm1 is excitation current of transformer T₁ on LVS, i_Lr is current of resonant inductor, i_Cr1 and i_Cr2 are currents of resonant capacitors on HVS and LVS, u_GS14 is the driving signal of S₁ and S₄, u_GS23 is the driving signal of S₂ and S₃, u_GS58 is the driving signal of S₅ and S₈, u_GS67 is the driving signal of S₆ and S₇, u_DS14 is the drain-source voltage of S₁ and S₄, u_DS23 is the drain-source voltage of S₂ and S₃, u_DS58 is the drain-source voltage of S₅ and S₈, u_DS67 is the drain-source voltage of S₆ and S₇, i_DS14 is the drain-source current of S₁ and S₄, i_DS23 is the drain-source current of S₂ and S₃, i_DS58 is the drain-source current of S₅ and S₈, i_DS67 is the drain-source current of S₆ and S₇.

2.1.1. Forward Mode

The equivalent circuits in forward mode are listed in Figure 3. Detailed descriptions and explanations of the operational modes in half period are as follows:

Mode A [t₀–t₁]: S₂ and S₃ have just turned off at t₀. The HVS current charges the output capacitor of S₂ and S₃, and discharges the output capacitor of S₁ and S₄. After that, the HVS current passes through the antiparallel diode of S₁ and S₄, which makes the switches turn on under the ZVS condition.

Mode B [t₁–t₂]: At t₁, S₁, S₄, S₅ and S₈ turn on and power is transferred from HVS to LVS. The resonant current changes in a sine-wave with main resonant frequency, f_r. At t₂, i_Lr is equal to i_Lm1, i_Cr2 and i_ds58 become zero.

Mode C [t₂–t₃]: S₁ and S₄ are still on in this mode, S₅ and S₈ are off in this mode. As i_Cr2 and i_ds58 are zero in t₂, S₅ and S₈ turn off under ZCS condition. The HVS goes into secondary resonance with the frequency of f_r2f. At t₃, S₁ and S₄ are off and ready to go into dead-time duration.

When working frequency is bigger than main resonant frequency, Mode C and ZCS of LVS power switches disappear like LLC. The turn-off currents increase largely in this situation.

2.1.2. Backward Mode

The equivalent circuits in backward mode are listed in Figure 4. L’_m1 and L’_m2 are the magnetizing inductors on LVS. The modes are similar to those in forward mode. Detail descriptions and explanations of the operational modes in half period are shown as follows:

Mode A [t₀–t₁]: S₆ and S₇ turn off at t₀. The resonant current on LVS charges the output capacitor of S₆ and S₇, and discharges the output capacitor of S₅ and S₈. After that, the LVS current passes through the antiparallel diode of S₅ and S₈, which makes the switches turn on under the ZVS condition.

Mode B [t₁–t₂]: At t₁, S₅, S₈, D₁ and D₄ turn on and power is transferred from LVS to HVS. The resonant current on LVS changes in a sine-wave with main resonant frequency. At t₂, i_Cr2 is equal to i’_Lm1, i_Cr1 and i_ds14 become zero.

Mode C [t₂–t₃]: S₅ and S₈ are still on in this mode, D₁ and D₄ are off in this mode. ZCS of D₁ and D₄ is realized as i_Cr1 and i_ds14 become zero at t₂. The LVS goes into secondary resonance with the frequency of f_r2b. At t₃, S₁ and S₄ are off and ready to go into dead-time duration.

When working frequency is bigger than main resonant frequency, Mode C and ZCS of HVS diodes disappear like LLC. The turn-off currents increase largely in this situation.

2.2. Characteristic Description

Main resonant frequency of CLTC converter in two power flows, f_r, is:

$$f_{\mathrm{r}}=\frac{1}{2\pi }\sqrt{\frac{A}{B}}$$

(1)

where:

$$A=A_1+A_1{}^2-A_2$$

(2)

$$A_1=C_{\mathrm{r}1}{L}_{\mathrm{m}2}\left(L_{\mathrm{m}1}+L_{\mathrm{r}}\right)n_1{}^2{n}_2{}^2+\left(L_{\mathrm{m}1}+L_{\mathrm{r}}\right)C_{\mathrm{r}2}{L}_{\mathrm{m}2}{n}_1{}^2+\left(L_{\mathrm{m}2}+L_{\mathrm{r}}\right)C_{\mathrm{r}2}{L}_{\mathrm{m}1}{n}_2{}^2+2C_{\mathrm{r}2}{L}_{\mathrm{m}1}{L}_{\mathrm{m}2}{n}_1{n}_2$$

(3)

$$A_2=4C_{\mathrm{r}1}{C}_{\mathrm{r}2}{L}_{\mathrm{m}1}{L}_{\mathrm{m}2}{L}_{\mathrm{r}}\left(L_{\mathrm{m}1}+L_{\mathrm{m}2}+L_{\mathrm{r}}\right)n_1{}^2{n}_2{}^4$$

(4)

$$B=2C_{\mathrm{r}1}{C}_{\mathrm{r}2}{L}_{\mathrm{m}1}{L}_{\mathrm{m}2}{L}_{\mathrm{r}}{n}_2{}^2$$

(5)

f_r is obtained when no load is added and imaginary part of AC input impedance of CLTC is zero.

The secondary resonant frequency in forward mode, f_r2f, and the secondary resonant frequency in backward mode, f_r2b, are:

$$f_{\mathrm{r}2\mathrm{f}}=\frac{1}{2\pi }\sqrt{\frac{L_{\mathrm{r}}+L_{\mathrm{m}1}+L_{\mathrm{m}2}}{C_{\mathrm{r}1}{L}_{\mathrm{m}2}\left(L_{\mathrm{r}}+L_{\mathrm{m}1}\right)}}$$

(6)

$$f_{\mathrm{r}2\mathrm{b}}=\frac{1}{2\pi \sqrt{\left({L^{\prime }}_{\mathrm{m}1}+{L^{\prime }}_{\mathrm{m}2}\right)C_{\mathrm{r}2}}}$$

(7)

f_r2f and f_r2b are obtained with the resonant capacitance and inductance in secondary resonance. The resonant capacitance and inductance are shown in Figure 3c and Figure 4c.

By use of the fundamental harmonic analysis (FHA) method, Figure 5a and Figure 6a show 3D voltage gain curves according to load P_o and normalized working frequency f_s/f_r. G_F is gain in forward mode and G_B is gain in backward mode. As is shown in Figure 5b and Figure 6b, when the working frequency is below the main resonant frequency, G_F and G_B increase at first and decrease subsequently with the growth of working frequency. The peak gains are more than 1 over all the load range and obtained around secondary resonant frequency, f_r2f and f_r2b. At main resonant frequency f_r, the gain of the converter is 1. As is shown in Figure 5c and Figure 6c, when working frequency is above main resonant frequency, G_F and G_B decrease with the growth of working frequency. When load is lighter, the voltage gain is higher and the slope of gain curve is sharper. Voltage gain range of CTLC converter is wide enough to adapt applications like battery charger and DC microgrid.

In order to realize ZVS for HVS switches, in forward mode, the dead-time duration t_{dt_F} should satisfy (6) using the ZVS mechanism analyzed by [19]. C_{oss_H} is the output capacitance of HVS switch:

$$t_{\mathrm{dt}\_\mathrm{F}}\ge \frac{16C_{\mathrm{oss}\_\mathrm{H}}{L}_{\mathrm{m}2}(L_{\mathrm{r}}+L_{\mathrm{m}1})f_{\mathrm{s}}}{L_{\mathrm{r}}+L_{\mathrm{m}1}+L_{\mathrm{m}2}}$$

(8)

Similarly, in backward mode, the dead-time duration t_{dt_B} of LVS switches should satisfy:

$$t_{\mathrm{dt}\_\mathrm{B}}\ge 16C_{\mathrm{oss}\_\mathrm{L}}({L^{\prime }}_{\mathrm{m}1}+{L^{\prime }}_{\mathrm{m}2})f_{\mathrm{s}}$$

(9)

C_{oss_L} is the output capacitance of LVS switch in (7).

The inequations can be easily satisfied with different loads and working frequencies, which is good for efficiency. The t_{dt_F} and t_{dt_B} are set to 200 ns in experiments.

3. Hybrid Full-Bridge/Half-Bridge Configuration

In this section, the reason for the upturn phenomenon is analyzed. A full-bridge configuration is used with a normal load. Half-bridge configurations are used for light load conditions with the advantage of monotonous gain curve and lower frequency. Because the situations in forward and backward mode are similar, the discussion in this section is conducted only in forward mode, and details are not provided for the backward mode.

3.1. Half-Bridge Configuration at Light Load Condition

Using the analysis method proposed in [22], it is found that transformer wiring capacitance is the main factor leading to the upturn problem. As is shown in Figure 7a, the ideal gain curve without considering parasitic parameters in forward mode is monotonous with working frequency under light load conditions. However, the voltage gain curve considering transformer wiring capacitance and experimental gain curve has upturns. As the experiment gain curve is not monotonous, the gain cannot be regulated well with PFM. For example, the voltage gain of 1.02 in Figure 7a is obtained with four different working frequencies. When PFM is adopted to control LVS voltage, the working frequency may be around 1.4f_r instead of 0.8f_r, and fluctuates quickly as the gain curve is not monotonous.

To overcome the above problem, a half-bridge configuration is introduced in this paper to regulate the required output voltage. In forward mode, the full-bridge in HVS is transformed into a half-bridge by turning off Q₃ and turning on Q₄ incessantly. The voltage gain is reduced by half, with the same load and resonant parameters. Thus, when the voltage gain needed is below 1 under light load conditions, a half-bridge configuration is adopted and the required gain is obtained with lower working frequency. In Figure 7b, when the working frequency is around 0.35f_r, twice the required gain is acquired in full-bridge configuration. Thus, a gain of 1.02 is acquired in half-bridge configuration with the same working frequency and load. Also, the gain of 1.02 is controllable in half-bridge mode, because the working frequency decreases largely, away from the region where the gain is not monotonous.

The mechanism of transformation between full-bridge and half-bridge configuration is displayed in Figure 8. With the decrease of load in full-bridge configuration, the gain curve rises. Then, the full-bridge configuration is transformed into a half-bridge configuration, working frequency gets lower and the gain curve is monotonous around G_r. At last, half-bridge configuration is used to adapt lighter load instead of full-bridge configuration. The mechanism of transforming full-bridge into half-bridge is simple and effective, still, several considerations of the method are discussed here.

3.2. Voltage and Current Stresses

The stresses in both full-bridge and half-bridge configurations need to be checked. Voltage stresses of all the switches do not change. When the same power is transmitted, current stresses of LVS switches stay the same. Current stresses of HVS switches in half-bridge are twice of those in full-bridge as the AC input voltage is cut by half. Thus, the load must be light if half-bridge is adopted, to ensure the current amplitude is acceptable.

3.3. Load and Working Frquency Range

The peak gain should be larger than the required gain, G_r. It is because if the peak gain is smaller than G_r, G_r cannot be tracked. Taking a margin of 0.05G_r into consideration, the DC output resistance in half-bridge configuration, R_o,H, should satisfy the following equation:

$$G_{\mathrm{F},\mathrm{H}}\left(f_{\mathrm{H},1},R_{\mathrm{o},\mathrm{H}}\right)\ge 1.05G_{\mathrm{r}}$$

(10)

In (8), G_F,H is the voltage gain of half-bridge CLTC, f_H,1 is the maximum point.

Also, R_o,H should be bigger than twice of the rated resistance, R_o,H,rated, in full-bridge. As Section 3.2 tells, the selection of R_o,H should guarantee that the current stresses in half-bridge are no bigger than those in full-bridge. Thus:

$$R_{\mathrm{o},\mathrm{H}}\ge 2R_{\mathrm{o},\mathrm{F},\mathrm{rated}}$$

(11)

The working frequency of CLTC in half-bridge configuration, should be in the range of [f_H,1,max, f_r]. The working frequency should be lower than f_r to avoid upturn phenomenon of gain curve. Also, when load is heavier in half-bridge, f_H,1 gets larger as Figure 8 shows, so the lower limit of the working frequency is the largest value of f_H,1, f_H,1,max. In the range of [f_H,1,max, f_r], the gain curve monotonously declines with working frequency, and the slope is sharper in half-bridge configuration. It is ideal for voltage regulation of CLTC.

4. Synchronous Rectification Strategy Based on Estimation of Body Diodes’ Conduction Time

In consideration of improving the efficiency, a digital synchronous rectification strategy is proposed in forward mode. No auxiliary circuit is added. The proposed strategy adjusts conduction time of switches in LVS by calculating rectifier diodes’ conduction time in half period, t_SR. A whole process of calculating t_SR is proposed and verified in this section. It can be used in both full-bridge configuration and half-bridge configuration.

4.1. Synchornous Rectification Strategy

With the proposed digital synchronous rectification strategy, all the driving signals of HVS switches S₁–S₄ and LVS SR switches S₅–S₈ are given by STM32F series chip. The turn-on time of SR switches is set to the same with HVS main switches. But the conduction time (the interval between turn-on and turn-off time) is set with the estimation value of body diodes’ conduction time in half period, t_SR, so t_SR should be calculated for synchronous rectification.

4.2. Estimation of the Body Diodes’ Conduction Time

When working frequency of CLTC is larger than main resonant frequency, t_SR is half working period because the secondary resonance doesn’t exist. However, when working frequency is smaller than main resonant frequency, t_SR is a variable with respect to R_o and f_s. So discussion is focused on t_SR when working frequency is smaller than main resonant frequency.

In Figure 9, assuming resonant current on LVS, i_Cr2, is approximated to a sinusoidal pulse:

$$i_{\mathrm{Cr}2}=\{\begin{array}{ll}{I}_{\mathrm{Cr}2}\sin (\frac{\pi \times t}{t_{\mathrm{SR}}}),\hfill & 0\le t\le t_{\mathrm{SR}}\hfill \\ 0,\hfill & t_{\mathrm{SR}}\le t\le T\hfill \end{array}$$

(12)

I_Cr2 is the peak value of i_Cr2, t is the real time, T₂ is half period, 1/(2f_s). The value of u_AB is U_H in this period.

By using the law of conservation of electric charge, it can be obtained that:

$${\displaystyle {\int }_0^{t\mathrm{SR}}{I}_{\mathrm{Cr}2}\sin (\frac{\pi \times t}{t_{\mathrm{SR}}})dt}=I_{\mathrm{o}}\times T_2$$

(13)

According to (13), I_Cr2 can be expressed by:

$$I_{\mathrm{Cr}2}=I_{\mathrm{o}}\frac{\pi T_2}{2t_{\mathrm{SR}}}$$

(14)

The voltage of C_r2 can be expressed by:

$$u_{\mathrm{Cr}2}(t)=\frac{1}{C_{\mathrm{r}2}}{\displaystyle {\int }_0^t{I}_{\mathrm{Cr}2}\sin (\frac{\pi \times t}{t_{\mathrm{SR}}})dt}+U_{\mathrm{Cr}2,0}$$

(15)

As i_Cr2 is 0 and the voltage of C_r2 stays the same during t_SR–T₂, the following equation is found:

$$U_{\mathrm{Cr}2,0}=-u_{\mathrm{Cr}2}(T_2)=-u_{\mathrm{Cr}2}(t_{\mathrm{SR}})$$

(16)

Applying (15) into (16), the U_Cr2,0 can be expressed by:

$$U_{\mathrm{Cr}2,0}=-\frac{t_{\mathrm{SR}}{}^2{U}_{\mathrm{L}}}{2C_{\mathrm{r}2}{T}_2{R}_{\mathrm{o}}}$$

(17)

The voltage of magnetizing inductance L_m1 and L_m2, u_Lm1 and u_Lm2, can form following equations:

$$\{\begin{array}{l}\frac{u_{\mathrm{Lm}1}(t)}{n_1}+\frac{u_{\mathrm{Lm}2}(t)}{n_2}=U_{\mathrm{L}}+U_{\mathrm{Cr}2}(t)\\ (1+\frac{L_{\mathrm{r}}}{L_{\mathrm{m}1}})u_{\mathrm{Lm}1}(t)+\frac{1}{n_1}{L}_{\mathrm{r}}\frac{d{i}_{\mathrm{Cr}2}(t)}{dt}=u_{\mathrm{Lm}2}(t)\end{array}$$

(18)

so u_Lm2 can be expressed by:

$$u_{\mathrm{Lm}2}(t)=\frac{\frac{n_2}{n_1}{L}_{\mathrm{r}}\frac{d{i}_{\mathrm{Cr}2}(t)}{dt}+(1+\frac{L_{\mathrm{r}}}{L_{\mathrm{m}1}})n_1{n}_2\left[U_{\mathrm{L}}+U_{\mathrm{Cr}2}(t)\right]}{n_2+n_1(1+\frac{L_{\mathrm{r}}}{L_{\mathrm{m}1}})}$$

(19)

The instantaneous voltage between HVS full-bridge legs, u_AB, can be expressed as:

$$u_{\mathrm{AB}}(t)=U_{Cr1,0}+\frac{1}{C_{\mathrm{r}1}}{\displaystyle {\int }_0^t{i}_{\mathrm{Cr}1}(t)dt}+u_{\mathrm{Lm}2}(t)$$

(20)

where, U_Cr1,0 is the initial voltage of resonant capacitor C_r1 at t₀, and the instantaneous current of C_r1, i_Cr1, can be expressed as:

$$i_{\mathrm{Cr}1}(t)=i_{\mathrm{Lm}1}(t)+i_{\mathrm{Lm}2}(t)+(\frac{1}{n_1}+\frac{1}{n_2})i_{\mathrm{Cr}2}(t)$$

(21)

In order to simplify calculation process, L_m2 is supposed to be subject to u_AB during 0–t_SR. So i_Lm2 and i_Lm1 can be expressed as linearly increasing currents:

$$i_{\mathrm{Lm}1}(t)=\frac{U_{\mathrm{H}}}{2(L_{\mathrm{m}1}+L_{\mathrm{r}})}t+I_{\mathrm{Lm}1,0}$$

(22)

$$i_{\mathrm{Lm}2}(t)=\frac{U_{\mathrm{H}}}{2L_{\mathrm{m}2}}t+I_{\mathrm{Lm}2,0}$$

(23)

I_Lm1,0 and I_Lm2,0 is the initial value of I_Lm1 and I_Lm2:

$$I_{\mathrm{Lm}1,0}=-\frac{U_{\mathrm{H}}\times t_{\mathrm{SR}}}{4(L_{\mathrm{m}1}+L_{\mathrm{r}})}$$

(24)

$$I_{\mathrm{Lm}2,0}=-\frac{U_{\mathrm{H}}\times t_{\mathrm{SR}}}{4L_{\mathrm{m}2}}$$

(25)

Realizing that u_AB(t) = U_H and substituting (19) and (21) into (20), gives:

$$U_{\mathrm{H}}=U_{\mathrm{Cr}1,0}+\frac{1}{C_{\mathrm{r}1}}{\displaystyle {\int }_0^t\left[i_{\mathrm{Lm}1}(t)+i_{\mathrm{Lm}2}(t)+(\frac{1}{n_1}+\frac{1}{n_2})i_{\mathrm{Cr}2}(t)\right]dt}+\frac{\frac{n_2}{n_1}{L}_{\mathrm{r}}\frac{d{i}_{\mathrm{Cr}2}(t)}{dt}+(1+\frac{L_{\mathrm{r}}}{L_{\mathrm{m}1}})n_1{n}_2\left[U_{\mathrm{L}}+U_{\mathrm{Cr}2}(t)\right]}{n_2+n_1(1+\frac{L_{\mathrm{r}}}{L_{\mathrm{m}1}})}$$

(26)

Getting the derivative of the above equation:

$$0=-D\frac{{\pi }^2}{t_{\mathrm{SR}}{}^2}\sin (\frac{\pi \times t}{t_{\mathrm{SR}}})+E\times \sin (\frac{\pi \times t}{t_{\mathrm{SR}}})+F\times t_{\mathrm{SR}}\times t+\frac{I_{\mathrm{Lm}1,0}+I_{\mathrm{Lm}2,0}}{I_{\mathrm{Cr}2}}$$

(27)

In (27), D, E, F are:

$$D=\frac{C_{\mathrm{r}1}{n}_2{L}_{\mathrm{r}}}{n_1\left[n_2+n_1(1+\frac{L_{\mathrm{r}}}{L_{\mathrm{m}1}})\right]}$$

(28)

$$E=\frac{C_{\mathrm{r}1}(1+\frac{L_{\mathrm{r}}}{L_{\mathrm{m}1}})n_1{n}_2}{C_{\mathrm{r}2}\left[n_2+n_1(1+\frac{L_{\mathrm{r}}}{L_{\mathrm{m}1}})\right]}+\frac{1}{n_1}+\frac{1}{n_2}$$

(29)

$$F=\left[\frac{1}{2(L_{\mathrm{m}1}+L_{\mathrm{r}})}+\frac{1}{2L_{\mathrm{m}2}}\right]\frac{U_{\mathrm{H}}}{I_{\mathrm{Cr}2}{t}_{\mathrm{SR}}}$$

(30)

U_H can be expressed as U_L/M_SD, so F can be simplified by:

$$F=\left[\frac{1}{2(L_{\mathrm{m}1}+L_{\mathrm{r}})}+\frac{1}{2L_{\mathrm{m}2}}\right]\frac{2R_{\mathrm{o}}}{\pi T_2{M}_{\mathrm{SD}}}$$

(31)

$\frac{I_{\mathrm{Lm}1,0}+I_{\mathrm{Lm}2,0}}{I_{\mathrm{Cr}2}}$ is close to 0 as I_Cr2 is much larger than I_Lm1,0 + I_Lm2,0. When t is close to 0, $\frac{\pi \times t}{t_{\mathrm{SR}}}\approx \sin \left(\frac{\pi \times t}{t_{\mathrm{SR}}}\right)$, t_SR is the solution of (27):

$$t_{\mathrm{SR}}=\sqrt{\frac{-\pi E+\pi \sqrt{E^2+4DF\pi }}{2F}}$$

(32)

In Figure 10, the normalized estimated conduction time t_SR/T₂ versus normalized operating frequency f_s/f_r and different load (dots—simulation, solid lines—theoretical prediction). Figure 10 reveals good agreement between theoretical values and simulation results. The curve of t_SR/T₂ is basically proportional to f_s/f_r, and grows with the increase of load.

Based on the above analysis, the conduction time of LVS switches is set to estimated conduction time t_SR obtained when load is the lightest, so the conduction time of LVS switches in the proposed synchronous rectification strategy is not relevant to the load. It is a parameter changing with operating frequency. LVS switches turn on firstly to reduce conduction loss. Then, as estimated conduction time t_SR is a little smaller than the real conduction time of LVS body diodes, the body diodes of LVS switches conduct until the LVS resonant current becomes zero. Efficiency is not affected because the duration when body diodes conduct is short. The proposed digital synchronous rectification strategy is simple and effective, the effects are discussed in sections below.

5. Power Loss Analysis

The power loss of converters is the key factor for component selection and design. In this section, the power loss distribution is calculated with mathematical models and compared with different LVS DC voltages. The HVS DC voltage of the converter stays the same. The power loss with half-bridge configuration and synchronous rectification strategy are discussed in this section, too.

Before further analysis, several parameters are defined as follows, P_HSW,off is the turn-off loss of HVS power switches, P_HSW,con is the conduction loss of HVS power switches, P_LSW,off is the turn-off loss of LVS power switches, P_LSW,con is the conduction loss of LVS power switches, P_L is the power loss of resonant inductor, P_T,Σ is the total power loss of transformers, P_WIRE,con is the conduction loss in printed circuit board and copper bar, P_HD is the power loss of HVS diodes, P_LD is the power loss of LVS body diodes in power switches.

5.1. Loss Distribution with Different LVS DC Voltages

Power loss distribution with 5 kW load in forward and backward mode is shown in Figure 11. The power loss distribution is conducted with three LVS DC voltages of 42, 50 and 58 V and the HVS voltage of 400 V. In forward mode, the column of “50 V” is obtained around main resonant frequency, while the column of “42 V” is obtained with higher frequency and column of “58 V” is obtained with lower frequency. In backward mode, the column of “50 V” is obtained around main resonant frequency, while the column of “42 V” is obtained with lower frequency and column of “58 V” is obtained with higher frequency.

P_HSW,off and P_LSW,off are the dominant power losses. P_L and P_T,Σ change little with the change of LVS DC voltage. P_WIRE,con is large due to proximity effect and skin effect. The column of “42 V” in forward mode and the column of “58 V” in backward mode have greater power loss compared to the other columns. This is mainly because P_HSW,off and P_LSW,off are larger due to larger turn-off currents and higher working frequencies. The HVS switches are SiC power devices, and the LVS switches are Si power devices. Compared to LVS switches, the HVS switches have less turn-off delay time and fall time. So the switching loss of LVS switches is larger than that of HVS switches. Thus, the efficiency in forward mode is higher than that in backward mode in general.

5.2. Power Loss Distribution and Comparison between Full-Bridge and Half-Bridge Configuration

The power loss distribution and comparison between full-bridge and half-bridge configuration is made to demonstrate the advantage of half-bridge configuration in efficiency. Taking forward mode for example, changing from full-bridge configuration to half-bridge configuration has impacts as follows:

(1)

P_HSW,off and P_LSW,off decrease largely. In forward mode, switches staying on on-off mode in HVS decrease from 4 to 2, and their working frequency decreases from 160 kHz to around 40 kHz. So P_HSW,off decreases largely with half-bridge configuration. Also, P_LSW,off decreases with less turn-off current and lower working frequency.

(2)

The conduction loss of all devices increases. Resonant current on HVS increases to about twice, so P_HSW,con, conduction loss of resonant inductor and primary windings of transformers are amplified. However, as resonant current on LVS changes little, P_LSW,con and the conduction loss of secondary windings in transformers stay the same.

(3)

Core loss of resonant inductor and transformers stays the same. In half-bridge LLC, working frequency f_s decreases. However, B_max, the peak flux density, increases because peak value of current increases. With Steinmetz’s equation P_core = Kf_s^αB_max^βV_e, the core losses of resonant inductor and transformers in half-bridge configuration change little.

Figure 12a shows power loss distribution and comparison with load of 200 W in forward mode. Efficiencies of half-bridge and full-bridge configuration are 87.7% and 86.7%. The power loss distribution is in accordance with the above analysis. Compared to full-bridge configuration, efficiency is a little higher in half-bridge configuration.

Figure 12b shows power loss distribution and comparison with load of 200 W in backward mode. P_LSW,off gets much smaller in half-bridge configuration. The power loss is cut down by 26.7% and the efficiency is 81.5% in half-bridge configuration.

5.3. Power Loss Distribution and Comparison with and without Synchronous Strategy

Figure 13 shows the power loss distribution and comparison with and without synchronous strategy. When body diodes of LVS switches are used to realize rectification, P_LD is quite large with diode forward voltage of 0.9 V. However, the drain-source on-state resistance of LVS switches is only 0.7 mΩ. Thus, with the use of the proposed synchronous strategy, P_LSW,con is quite small. The total loss is cut by 49% with the use of synchronous strategy, showing the advantage in power loss reduction and efficiency enhancement.

6. Experimental Results

A 5 kW prototype is built in the laboratory to verify the above analysis. The parameters of the components are listed in

Table 1. Parameters of the converter.

Component	Model/Value
Rated power	5 kW
HVS DC voltage	380–420 V
LVS DC voltage	42–58 V
S1, S2, S3, S4	C3M0065090D
S5, S6, S7, S8	4 IPB036N12N3G in parallel
D1, D2, D3, D4	C3D30065D
Lm1	140 μH
n1	11:1
Lm2	875 μH
n2	20:1
Lr	57 μH
Cr1	251 nF
Cr2	10 μF
tdt_F	200 ns
tdt_B	200 ns

.

Figure 14 shows that ZVS of power switches can be realized in both forward and backward modes. In forward mode, the D-S voltage of S₁ decreases to 0, before the driving signal of S₁ comes. In backward mode, the D-S voltage of S₅ decreases to 0, before the driving signal of S₅ comes. The dead time of 200 ns is wide enough for both HVS and LVS power switches, while the efficiency is not greatly reduced.

Figure 15 shows experiment results in forward mode. The t_SR is 4.6 μs in Figure 15a with working frequency of 60 kHz and load of 3.5 kW. The t_SR is 4.5 μs with Equation (25) and 4.3 μs in the proposed synchronous rectification strategy, which is basically consistent with the experiment results. The accuracy of calculation and the effectiveness of proposed synchronous rectification strategy are verified through experiments. Figure 15b shows the waveforms around main resonant frequency. The resonant current is quite close to sinusoidal wave. The power loss is lower because of smaller turn-off loss in this situation.

Figure 16 shows experiment results in backward mode. In Figure 16a, secondary resonance does not happen, so ZCS of HVS diodes cannot be realized. In Figure 16b, the resonant current is quite close to sinusoidal wave around main resonant frequency. The power loss in Figure 16b is lower because of smaller turn-off loss.

Experiments are conducted to verify the effectiveness of half-bridge configuration at light load condition in Figure 17. In both forward and backward mode, the adoption of half-bridge configuration can track a gain of 1.02. Compared to full-bridge, the fall of working frequency in half-bridge configuration reduces turn-off loss, which is very good for efficiency.

Efficiency comparison is conducted with experiments at light load condition. In

Table 2. Efficiency comparison with load of 200 W.

Type	Half-Bridge	Full-Bridge
Forward	87.3%	83.0%
Backward	82.1%	70.9%

, the efficiency in half-bridge configuration is higher than that in full-bridge, which is in accord with analysis in Section 5.2. The advantage of half-bridge configuration is verified through experiments.

Efficiencies of the proposed converter with different loads and LVS DC voltages are measured and plotted in Figure 18. The efficiency with 5 kW load and 50 V LVS DC voltage is 95.9% and 94.9% in forward and backward mode. The maximum efficiency of the converter is 97.0%, with load of 2 kW and LVS DC voltage of 50 V in forward mode. Due to less turn-off currents and lower working frequencies, the efficiency of “58 V” or “50 V” is higher than that of “42 V” in forward mode and the efficiency of “42 V” or “50 V” is higher than that of “58 V” in backward mode. It is in accord with theoretical analysis in Section 5. High efficiency can be achieved in a wide load range. Even with 1 kW load, the efficiency is still over 92% due to the wide ZVS soft switching operation range and little turn-off currents.

The comparative experiments are conducted with and without synchronous rectification strategy when LVS DC voltage is 50 V, displayed as “50 V” and “Diode 50 V”. From the converter power loss distribution, the LVS diode conduction loss is the dominant part in “Diode 50 V”, which occupies nearly 50% of the total power loss. Experiment results show that the efficiency is improved largely with the help of the proposed synchronous rectification strategy.

7. Conclusions

In this work, a new CLTC multi-resonant DC-DC converter is proposed. Possessing the optimal ZVS + ZCS soft switching feature in all load range, CLTC benefits from little turn-off loss and high efficiency. The gain range is so wide that the demands of applications like battery chargers and DC microgrids can be satisfied easily. The problem of voltage regulation under light load conditions is so serious that voltage is not controllable. The hybrid full-bridge/half-bridge configuration is proposed to make gain curve monotonous under light load conditions. Discussion about voltage and current stresses, load and working frequency range in half-bridge configuration are put forth as well. Besides, a digital synchronous rectification strategy is proposed in forward mode to improve the working efficiency. The turn-on time of LVS switches is set to the same as the HVS switches. The conduction time of LVS switches equals the estimation value of body diodes’ conduction time with the lightest load. Simulations verify the accuracy of this estimation. Furthermore, power loss analysis is conducted with different LVS DC voltages in two directions. Power loss is much more when the working frequency is beyond main resonant frequency, because of high conduction losses and turn-off losses. Efficiency with a half-bridge configuration is a little higher than that with full-bridge configuration in both directions, due to less turn-off losses. The loss is cut by 49% with the use of a synchronous strategy, showing the advantage in improving efficiency. At last, experiments are conducted to validate the theoretical analysis above. ZVS feature, the effectiveness of hybrid full-bridge/half-bridge configuration, and the validity of proposed digital synchronous rectification strategy are all verified through experiments. With the help of ZVS + ZCS feature, high efficiency can be harvested in a wide load range. The full load efficiency is 95.9% in forward mode and 94.9% in backward mode with LVS DC voltage of 50 V. The maximum efficiency is 97.0% with a LVS DC voltage of 50 V and load of 2 kW.