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Article

Symmetrical Nine-Phase Drives with a Single Neutral-Point: Common-Mode Voltage Analysis and Reduction

by
Sherif M. Dabour
1,2,*,
Ahmed A. Aboushady
2,
Mohamed A. Elgenedy
2,
I. A. Gowaid
2,3,
Mohamed Emad Farrag
2,
Ayman S. Abdel-Khalik
3,
Ahmed M. Massoud
4,* and
Shehab Ahmed
5
1
Department of Electrical Power and Machines Engineering, Tanta University, Tanta 31733, Egypt
2
Electrical and Electronics Engineering Department, Glasgow Caledonian University, Glasgow G4 0BA, UK
3
Department of Electrical Engineering, Alexandria University, Alexandria 21544, Egypt
4
Department of Electrical Engineering, Qatar University, Doha 2713, Qatar
5
Electrical Eng. Dept., KAUST, Thuwal 23955, Saudi Arabia
*
Authors to whom correspondence should be addressed.
Appl. Sci. 2022, 12(24), 12553; https://doi.org/10.3390/app122412553
Submission received: 6 October 2022 / Revised: 18 October 2022 / Accepted: 20 October 2022 / Published: 7 December 2022
(This article belongs to the Topic Power Electronics Converters)

Abstract

:
Power converters generate switching common mode voltage (CMV) through the pulse width modulation (PWM). Several problems occur in the drive systems due to the generated CMV. These problems can be dangerous to the insulation and bearings of the electric machine windings. In recent years, many modulation methods have been developed to reduce the CMV in multiphase machines. Symmetrical nine-phase machines with single-neutral are considered in this paper. In this case, conventional PWM uses eight active vectors of different magnitudes in combination with two zero states in a switching cycle, and this generates maximum CMV. This paper proposes two PWM schemes to reduce the CMV in such a system. The first scheme is called active zero state (AZS). It replaces the zero vectors with suitable opposite active vectors. The second scheme uses ten large active vectors during switching and is called SVM-10L. Compared with conventional strategies, the AZS reduces the peak CMV by 22.2%, and the SVM-10L reduces the peak CMV by 88.8%. Moreover, this paper presents a carrier-based implementation of the proposed schemes to simplify the implementation. The proposed schemes are assessed using simulations and experimental studies for an induction motor load under different case studies.

1. Introduction

Due to their advantages over three-phase machines, multiphase induction machines have recently gained much attention for medium voltage and high-power applications [1]. These systems have high reliability, fault tolerance capability, higher power density, and reduced switch ratings in the power converters. Thus, they are well suited for many applications that are principally associated with electric vehicles (EVs), ship propulsion, electric aircraft, and remote high-power wind power generation systems [1,2,3].
The nine-phase drive, shown in Figure 1, has specific merits among the various possible numbers of phases, such as [4]:
  • The stator of the standard three-phase machine can be rewound to obtain the nine-phase stator, and the rotor is still the same.
  • The nine-phase VSI can be realized as a combination of standard three-phase inverters.
  • In terms of control and fault-tolerant operation, it has additional degrees of freedom.
These merits make the nine-phase machines attractive in different applications. Several contributions have been made to embody the nine-phase systems in ultrahigh-speed elevators [5], onboard chargers of electric vehicles [3,6,7,8], aerospace [9], ship propulsion, wind energy generation systems, and high-power industrial applications [1,2,10].
Although nine-phase machines are distinguished by their lower d v / d t value; they still have the same peak common mode voltage (CMV) as the three-phase machine, which equals V d c [11,12]. Regardless of the number of phases, the CMV seems a common problem in drive systems. Hence, it represents one of the leading research topics to be investigated in the drive systems, where it leads to multiple unwanted effects such as [11,12,13,14]:
  • Electromagnetic Interference (EMI),
  • Winding insulation failure, and
  • Damage to motor bearings due to leakage currents.
The traditional solutions to mitigate CMV’s effects on the drive systems are based on hardware solutions, such as using a passive output filter or grounded brushes for the bearings [13]. However, all these solutions are costly and need significant maintenance. Consequently, research has been directed to find more affordable and straightforward methods to apply. Therefore, some modifications have been adopted to the conventional Sinusoidal PWM and Space Vector Modulation (SVM) techniques to effectively reduce the CMV, beginning with three-phase drive systems [15]. These solutions were extended after that to multiphase machines. In particular, the problem of CMV reduction in five-phase machines has received substantial interest [11,13,16,17,18,19]. Moreover, few studies have focused on the CMV reduction methods in six- and seven-phase machines such as [20,21].
In particular, the CMV problems in the nine-phase machines have rarely been studied directly. As an example of an odd-phase multiphase machine, it has only been mentioned in [12,22,23]. Additionally, simulation and experimental results in these works are based on RL loads. These studies ignore the inductances and mutual inductances inside the machine subspaces, which are significant, resulting in inaccurate results. There has been no research to the authors’ knowledge that has comprehensively explored this topic.
This paper aims to fill this gap by proposing CMV reduction PWM schemes for symmetrical nine-phase IM drives fed from two-level VSI with optimal performance and without extra hardware components. This paper describes the nine-phase VSI modeling and introduces the basic outlines to reduce CMV in the nine-phase motor drives. Aiming to solve the CMV problem of symmetrical nine-phase machines, two unique SVM schemes to reduce the CMV are proposed. The first scheme extends the concept of CMVR in the three-phase system to the nine-phase case by replacing the true zero vectors with two opposite active vectors. This approach reduces the CMV’s peak by 22.2% compared with the conventional scheme. However, the nine-phase system has eight CMV levels, and the elimination of true zero-states does not guarantee minimal CMV as in the three-phase system. Hence, a new CMV reduction scheme is needed. Therefore, the second approach has been proposed to address the CMV problem more efficiently, and this represents the key contribution of this paper. It utilizes ten large active vectors in every switching period to reduce the CMV magnitude by 88.8% and ensure minimal CMV. This paper also presents a detailed CMV analysis of the conventional and proposed schemes. Finally, simulation and experimental results of the conventional and the proposed schemes are provided to verify the new SVM scheme’s effectiveness and motor performance.

2. Nine-Phase Induction Motor Drives

The schematic diagram of a nine-phase motor fed from two-level VSI is shown in Figure 1. The motor has a star-connected stator winding with a single neutral point, n. The switching state of a leg-j in the nine-phase VSI (j = a, b, c, d, e, f, g, h, i) is determined by a switching function S j { 0 , 1 } , which is defined as: S j = 0 when the upper transistor of the corresponding leg j is OFF, and S j = 1 when it is ON. Therefore, the state of the inverter switches can be determined by the switching vector, S _ , which contains the switching function of each leg of the inverter
S _ = [ S a S b S c S d S e S f S g S h S i ]
The nine-phase VSI has 512 ( 2 9 ) switching vectors for connecting the output phases to the positive or negative dc-rails [24]. These switching combinations can be analyzed in five groups, as listed in Table 1. The groups are represented as {k,l} where k and l are the numbers of phases connected to the positive and negative rails of the dc-link, respectively. The corresponding instantaneous phase to neutral voltages of the symmetrical nine-phase machine can be expressed based on the inverter switching functions by
v j n = V d c ( S j 1 / 9 k = a i S k )
where V d c is the dc-link voltage.
These voltages are mapped on four subspace planes, namely α β , x 1 y 1 , x 2 y 2 and x 3 y 3 . The output voltage’s fundamental component relates to the first plane, whereas the other harmonic components map into the other planes [22]. The transformation matrix given in (3) is used to calculate the α β and x y components from the phase variables, where α = 2π/9. Application of (3) in conjunction with (2) results in voltage representation in the planes of Figure 2, where the dots represent space vectors’ tips [25].
[ v α v β v x 1 v y 1 v x 2 v y 2 v x 3 v y 3 ] = 2 / 9 [ 1 cos ( α ) cos ( 2 α ) cos ( 3 α ) cos ( 4 α ) cos ( 5 α ) cos ( 6 α ) cos ( 7 α ) cos ( 8 α ) 0 sin ( α ) sin ( 2 α ) sin ( 3 α ) sin ( 4 α ) sin ( 5 α ) sin ( 6 α ) sin ( 7 α ) sin ( 8 α ) 1 cos ( 2 α ) cos ( 4 α ) cos ( 6 α ) cos ( 8 α ) cos ( α ) cos ( 3 α ) cos ( 5 α ) cos ( 7 α ) 0 sin ( 2 α ) sin ( 4 α ) sin ( 6 α ) sin ( 8 α ) sin ( α ) sin ( 3 α ) sin ( 5 α ) sin ( 7 α ) 1 cos ( 3 α ) cos ( 6 α ) 1 cos ( 3 α ) cos ( 6 α ) 1 cos ( 3 α ) cos ( 6 α ) 0 sin ( 3 α ) sin ( 6 α ) 0 sin ( 3 α ) sin ( 6 α ) 0 sin ( 3 α ) sin ( 6 α ) 1 cos ( 4 α ) cos ( 8 α ) cos ( 3 α ) cos ( 7 α ) cos ( 2 α ) cos ( 6 α ) cos ( α ) cos ( 5 α ) 0 sin ( 4 α ) sin ( 8 α ) sin ( 3 α ) sin ( 7 α ) sin ( 2 α ) sin ( 6 α ) sin ( α ) sin ( 5 α ) ] [ v a v b v c v d v e v f v g v h v i ]

3. CMV Analysis in Nine-Phase Drives

The CMV in the drive system, V C M is defined as the potential difference between the machine’s neutral and the dc supply’s midpoint. It can be determined for three-phase systems from
V C M = V d c 3 k = a c S j V d c / 2 .
From (4), it can be concluded that the zero vectors in the three-phase system ([000], [111]) produce a maximum peak CMV (±Vdc/2); a minimum peak CMV of (±Vdc/6) is produced by the active vectors; and the CMV has four levels. It is noticeable that the elimination of zero vectors in the three-phase systems reduces the peak CMV to ±Vdc/6.
Some SVM techniques are presented to CMVR in the three-phase systems by avoiding the zero vectors [14]. Based on the three-phase CMVR techniques, it is possible to obtain the same output voltage of the inverter by replacing the zero vectors with two opposite active vectors. Likewise, the CMV in the nine-phase system can be expressed by
V C M = V d c 9 k = a i S j V d c 2
Applying (5) to the switching vector groups of the nine-phase VSI, ten different levels of V C M can be distinguished:
  • Maximum CMV of magnitude ± V d c / 2 ,  
  • Large CMV of magnitude ± 7 V d c / 18 ,
  • Medium CMV of magnitude ± 5 V d c / 18 ,
  • Small CMV of magnitude ± V d c / 6 and,
  • Minimum CMV of magnitude ± V d c / 18 .
From these, the switching vectors can be reclassified according to the magnitude of the CMV as listed in Table 2 and Table 3, and the following observations can be made
  • The zero vectors (0, 511) generate maximum CMV. Consequently, the inverter’s zero vectors should be avoided to reduce the CMV, and a reduction of 22.2% in the peak CMV can be obtained.
  • If group 2 switching states are also avoided, the peak CMV can be reduced by 44.4%.
  • Bypassing of group 3 reduces the peak CMV by 66.6%.
  • However, the peak CMV can be reduced by 88.8% if the switching states of group 5 are only used.

4. Conventional SVM for Nine-Phase Voltage Source Inverter

This section reviews the conventional SVM scheme for the nine-phase VSI given in [23] to address the CMV problems adequately. In this scheme, eight active vectors and the two zero vectors (0, 511) are utilized in each sector to obtain the reference vector ( v α β * ) . The eight active vectors are selected from α β subspace to eliminate the components of the x-y subspaces [24]. Then, the selected vectors should be organized to minimize the switching stresses and obtain symmetrical SVM. Figure 3a and Figure 4a show the selected vectors in sector 1, the corresponding switching sequence, and the CMV waveform, respectively. The eight vectors’ duty cycles can be determined by
[ v α * v β * v x 1 * v y 1 * v x 2 * v y 2 * v x 3 * v y 3 * ] = [ v 1 α v 2 α v 3 α v 4 α v 5 α v 6 α v 7 α v 8 α v 1 β v 2 β v 3 β v 4 β v 5 β v 6 β v 7 β v 8 β v 1 x 1 v 2 x 1 v 3 x 1 v 4 x 1 v 5 x 1 v 6 x 1 v 7 x 1 v 8 x 1 v 1 y 1 v 2 y 1 v 3 y 1 v 4 y 1 v 5 y 1 v 6 y 1 v 7 y 1 v 8 y 1 v 1 x 2 v 2 x 2 v 3 x 2 v 4 x 2 v 5 x 2 v 6 x 2 v 7 x 2 v 8 x 2 v 1 y 2 v 2 y 2 v 3 y 2 v 4 y 2 v 5 y 2 v 6 y 2 v 7 y 2 v 8 y 2 v 1 x 3 v 2 x 3 v 3 x 3 v 4 x 3 v 5 x 3 v 6 x 3 v 7 x 3 v 8 x 3 v 1 y 3 v 2 y 3 v 3 y 3 v 4 y 3 v 5 y 3 v 6 y 3 v 7 y 3 v 8 y 3 ] [ d α 1 d α 2 d α 3 d α 4 d β 1 d β 2 d β 3 d β 4 ]
where the subscripts α 1 α 4 , and β 1 β 4 refer to the eight active vectors ( α 1 ≡ 451, α 2 ≡ 385, α 3 ≡ 487, α 4 ≡ 256, β 1 ≡ 449, β 2 ≡ 483, β 3 ≡ 384, β 4 ≡ 503), and the subscripts 1 α 8 α , 1 β 8 β , 1 x 1 8 x 1 , 1 y 1 8 y 1 , 1 x 2 8 x 2 , 1 y 2 8 y 2 , 1 x 3 8 x 3 , 1 y 3 8 y 3 refer to the components of the vectors in different subspaces.
The reference voltage vectors for the x y planes of (6) are set to zero to nullify the harmonic components. Hence, the duty cycles of the active vectors for sinusoidal output voltages can be determined by solving the matrix given in (6) for V x 1 y 1 * = V x 2 y 2 * = V x 3 y 3 * = 0 . Solving this matrix yields
{ d α 1 = 0.6737 v α * 1.6972 v β * d α 2 = 0.5920 v α * 1.4913 v β * d α 3 = 0.4388 v α * 1.1055 v β * d α 4 = 0.2348 v α * 0.5916 v β * d β 1 = 1.8043 v β * d β 2 = 1.5891 v β * d β 3 = 1.1783 v β * d β 4 = 0.6260 v β *
If the summation of the duty cycles corresponding to α - and β -axis is assumed to be d α and d β , respectively, hence
{ d α 1 + d α 2 + d α 3 + d α 4 = d α d β 1 + d β 2 + d β 3 + d β 4 = d β .
Accordingly
{ d α 1 / d α = d β 1 / d β = 0.1205 d α 2 / d α = d β 2 / d β = 0.2268 d α 3 / d α = d β 3 / d β = 0.3055 d α 4 / d α = d β 4 / d β = 0.3473
{ d α = V o * sin ( π / 9 ϑ ) / ( V l sin ( π / 9 ) ) d β = V o * s i n ( ϑ ) / ( V l sin ( π / 9 ) )
where V l is the largest active vector magnitude, which equals 0.64 V d c [22], ϑ indicates the reference vector position, and V o * is the reference vector length. The duty cycle for the zero vectors (0, 511), d z is then determined by
d z = 1 m = 1 4 ( d α k + d β k ) .
The maximum output fundamental voltage obtained considering the traditional scheme is 50.9% of the input dc-voltage. As shown in Figure 4a, the traditional SVM provides ten CMV levels between ±0.5 Vdc.

5. Proposed SVM for CMV Reduction

5.1. AZS-Scheme

In this scheme, two appropriate opposite active vectors in all subspaces are used to obtain the same effect of the actual zero states (0, 511) and reduce the CMV magnitude. A similar proposal is presented in [14,16,21] but for three-, five- and seven-phase VSIs, respectively. To get the same output voltage vector magnitude as in the conventional SVM scheme, the duty cycles of these phase-opposed voltage vectors must be the same and equal d z determined for the true zero vectors. With this concept, any two active vectors in phase opposition will generate a zero vector on average and obtain a similar output voltage as in the conventional scheme.
However, some of these vectors generate a switching pattern with more than one switching cycle per sampling period (Ts), thus increasing the switching frequency. In this case, the only pair of vectors in phase opposition that preserves a constant switching frequency (1/Ts), hence ensuring one switching cycle per sampling period occurs, is (264, 247) for the first sector. These vectors form group 3 (Table 2) and generate a CMV with peak values of ± 5 V d c / 18 . After searching for all sectors, Table 4 lists the new zero vectors selected to reduce the CMV and ensure minimum switching commutations. Moreover, the selected vectors and the switching pattern of sector 1 in this scheme indicate the generated CMV, as shown in Figure 3b and Figure 4b, respectively. It is noticeable that the elimination of the true zero vectors reduces the peak CMV by 22.22%, with the peak CMV equaling ± 7 V d c / 18 .

5.2. SVM-10L Scheme

In this technique, only the voltage vectors of group 5 in the α β subspace, represented by the large space vectors in Figure 2a and listed in Table 5, are used to synthesize the reference voltage vector. With this scheme, it is possible to achieve a minimum CMV voltage of ± V d c / 18 magnitude. Ten large active vectors should be considered in each switching cycle to obtain a fixed switching frequency with a symmetrical PWM pattern. Focusing on sector 1, the ten adjacent large vectors (271, 263, 391, 387, 451, 449, 481, 480, 496, and 240) are selected to satisfy the minimum CMV and switching frequency conditions as shown in Figure 3c and Figure 4c. Moreover, the selected vectors minimize the error voltage vectors. It is essential to mention that the duty cycles of the selected vectors should be calculated using (6) to satisfy the v x y = 0 condition.

6. Carrier-Based Implementation

The key problem of the carrier-based implementation of the SVM techniques is to find the reference signals that will be compared with the carriers to obtain the same performance. Typically, the reference signals for leg- j can be defined by
v j = v j * + v z s = M cos θ j + v z s
where ω is the frequency in rad/s, k = 1–9 and v z s is the injected zero-sequence signal (zs).

6.1. CB-SVM Scheme

The carrier-based implementation of the conventional SVM of nine-phase VSI is commonly discussed in the different works [12,13], and the ZSS, v z s is governed by
v z s = v μ = 1 / 2 ( v max * + v min * )
where v max * = max ( v j * ) and v min * = min ( v j * ) .
For the sake of illustration, the reference, and min-max injected signals of the conventional SVM scheme for M = 0.95 are shown in Figure 5a. Thus, the reference signals are compared with a common high-frequency triangular carrier wave to obtain the inverter’s switching pulses.
Conversely, in the CB implementation of CMVR schemes, two opposite carrier waves are utilized instead of a single carrier [13]. The carrier-wave selection depends on the sector or the phase order, as shown in Table 6.

6.2. CB-AZS Scheme

This scheme uses the same ZSS signal given in (10), which is employed for CB-SVM but with the carriers defined in Table 6. For example, the reference signals of phases a and f in sector 1, which have the maximum and minimum envelope, are compared with the negative carrier wave, whereas the other reference signals are compared with the positive carrier. The same approach is extended to other sectors.

6.3. CB-SVM-10L Scheme

In the carrier-based implementation of the proposed CMVR method using the ten-large space vector method, a different ZSS signal is utilized. In this case, the ZSS, v ξ is obtained by applying the maximum magnitude test
v ξ = ( 2 ξ 1 ) ξ v max * ( 1 ξ ) v min * ξ = 1 / 2 ( 1 + sign ( cos ( 9 ω t ) ) ) . .
The reference and zero sequence signals of this scheme are shown in Figure 5b. The reference signals are also compared with the opposite carriers determined from Table 6 to obtain the gating pulses.

7. Common-Mode Voltage Analysis

As far as this paper is concerned with the CMV magnitude, the CMV waveform and its instantaneous function, v c m is considered in every section of the sample time for the conventional and proposed schemes. For example, the CMV waveforms of Figure 4 for the first sector are considered. It can be seen that v c m shows a staircase waveform. The mean square value of the CMV for one sample time, v c m M S 2 is determined as follows [13]
v c m M S 2 = 1 T s t 0 t 0 + T s v c m 2 d t .
where T s is the sampling time.
Based on (13) and the CMV waveforms of Figure 4, the mean square CMV, v c m M S 2 can be written as
v c m M S 2 = D P W M ( V d c / 18 ) 2 .
where
D SVM = { 9 2 ( d 0 + d 511 ) + 7 2 ( d 256 + d 503 ) + 5 2 ( d 384 + d 487 ) + 3 2 ( d 385 + d 483 ) + d 449 + d 451
D AZS = { 5 2 ( d 264 + d 247 ) + 7 2 ( d 256 + d 503 ) + 5 2 ( d 384 + d 487 ) + 3 2 ( d 385 + d 483 ) + d 449 + d 451
D SV 10 L   = 1
Based on (14) to (17), Figure 6a shows the dependency of RMS-CMV with the modulation index and the angle θ in the first sector for the analyzed PWM schemes. As can be seen, the AZS scheme gives a lower CMV than the conventional SVM scheme, whereas the proposed SVM-10L scheme gives the minimum CMV with a constant magnitude of any value of M . Consequently, the total RMS-CMV for the fundamental period, V c m f R M S is determined from
V c m ( M ) = 9 π 0 π / 9 v c m M S 2 ( M ,   θ ) d θ .
Solving (20) for the analyzed PWM schemes yields
V c m 2 V d c 2 = { 1 4 M 9 π ( 2 k 2 + k 4 + k 8 + 2 k 1 + 3 ) ( SVM ) 49 18 2 M 9 π ( 2 k 2 + k 4 + k 8 6 k 1 + 3 ) ( AZS ) 1 / 18 2   ( SV10L )
where k p is a constant and equals
k p = sin ( p π / 18 ) ,   p { 1 , 2 , 3 , }
Figure 6b shows RMS-CMV as a function of the modulation index for all analyzed schemes. As can be observed, CMVR schemes show better performance than the conventional SVM scheme, especially for lower M . Over the entire modulation range, the SV-10L scheme has the best performance.

8. Simulation and Experimental Results

8.1. Simulation Results

Simulation models for the nine-phase VSI feeding a symmetrical nine-phase inductive load are carried out using the MATLAB/PLECS software platform to verify the proposed CMVR scheme’s effectiveness. Ideal switches are assumed with a switching frequency of 10 kHz. The inverter is fed from a 200 V dc-supply, and the simulation parameters are given in Table 7. Three simulation studies are carried out for the analyzed PWM schemes, as shown in Figure 7, Figure 8 and Figure 9.
In all cases, the inverter is controlled to obtain an output peak voltage of 96 V/phase at 50 Hz, and the motor starts at no-load, then a load of 7 N-m is applied at 1.2 s. Figure 7 shows the nine-phase motor currents and phase voltage waveforms, motor torque and speed response, and finally, the CMV waveforms for all the presented PWM schemes. Moreover, Figure 8 shows the FFT analysis of the output voltages. From these results of Figure 7 and Figure 8, it can be observed that,
  • The output phase currents are very close in all the presented PWM schemes. Moreover, the motor currents exhibit near sinusoidal waveforms.
  • Nevertheless, eliminating the true zero and specific switching vectors to reduce the CMV magnitude in the AZS and SV-10L schemes generates more distortion in the motor voltage and currents, as shown in Figure 7 and Figure 8. The motor terminal voltage total harmonic distortions (THDs) are higher in the CMVR schemes than in the conventional SVM scheme. The THD has been evaluated considering harmonic components up to 20 kHz.
  • The reversal voltage chops in the phase- a voltage waveform, v a shown in Figure 7 represents the utilization of phase-opposed vectors instead of the true zero vectors in the AZS and SV-10L schemes.
  • Moreover, motor speed and torque responses are similar.
  • However, CMV waveforms are quite different. As can be seen, the CMVR schemes reduce the CMV peak more than the conventional SVM scheme, whereas the proposed SV-10L scheme gives the minimum CMV. From this point of view, it can be deduced that the SV-10L scheme presents better overall performance with additional voltage harmonics.

8.2. Experimental Results

This section is devoted to the laboratory-designed experimental setup and the measurements. Figure 9 shows the photograph of the experimental setup. The symmetrical nine-phase induction motor was obtained by rewinding the stator of an existing 1.5 hp three-phase squirrel cage machine; the rotor was kept the same. Moreover, the nine-phase VSI was constructed using discrete semiconductors and based on Power MOSFET-IRFP460. The inverter was powered by a three-phase phase autotransformer via an uncontrolled rectifier. The dc-link comprised two series, 4700 μF/600 V, to obtain positive, negative, and midpoint terminals. The PWM schemes and their gating signals were implemented via the DS1104 dSPACE platform. Six of the nine phases had LEM current sensors for measuring the output phase current, whereas the phase voltage and the CMV were measured via TERCO-1971 differential voltage probes. Finally, a Tektronix DPO2024 Oscilloscope was used to show the voltage and current waveforms.
In the experiment, the motor operated at no-load conditions with a frequency of 20 Hz, and the inverter was fed from 100 Vdc. Due to the capability of the dSPACE platform, the switching frequency was set at 3 kHz. Figure 10 shows the measurement of the phase voltage waveforms for the motor phase- a voltage, the currents of phase a and b , and the CMV waveforms for the analyzed PWM techniques. Moreover, to evaluate the quality of the inverter outputs, the Fast Fourier Transform (FFT) spectrum for the captured motor current for each scheme is shown in Figure 11. It can be observed that a near sinusoidal current with about THD of 5.6% was achieved with the SVM scheme but with a high CMV magnitude. However, the proposed AZS and SV-10L schemes that reduced the CMV have multiple low-order harmonics in the motor currents with high THD.
It is worth mentioning from the experimental results that although the duty cycles and the analyzed modulation schemes’ implementations ensured sinusoidal output voltage with zero x y components, the motor currents’ experimental waveforms were distorted. This is why:
  • The motor was initially a three-phase machine. Only the stator winding was replaced to configure a symmetrical nine-phase machine, and the rotor was kept the same. This resulted in some induced x y current components and increased mutual inductance coupling effects.
  • Application of deadtime for the inverter switching signal to prevent short-circuits between the upper and lower switches of the same leg, and
  • Parasitic effects of the semiconductors.
  • It seems that the largest peaks appeared at periodic intervals. Is there a possibility that it was due to a loss of controllability? Is it possible that the distortion was due to the possible delay in the changes of current direction when changing state or sequence? Authors are asked to describe whether or not these are a possibility. It is requested that they include an additional figure where the switching signals are shown, and the dead time considered can be clearly observed
  • Another comment is that the voltage and current spikes in Figure 10 were due to the PWM schemes’ deadtime effects.
It can be concluded that the simulation and experimental results showed a good agreement, and a notable reduction of CMV was observed in the proposed SV-10L scheme at the expense of additional current harmonics. Therefore, low efficiency is expected when the reduced CMV schemes are used.
A further comment made here is that in this paper, we focused primarily on designing PWM modulation schemes to reduce common-mode voltage effects; however, to achieve a robust drive system, a voltage regulation and a current control loop must be designed. When closed-loop control strategies, such as vector control, are employed, the control loops are used to generate the reference modulating signals. Then, the proposed PWM modulators in this paper are used to generate the gating pulses that operate the inverter switches.

9. Conclusions

Two common-mode voltage (CMV) reduction PWM schemes based on the SVM technique for a nine-phase induction drive system have been proposed in this paper, and the following conclusions can be derived.
  • By replacing the zero vectors in the conventional SVM technique with two opposite active vectors (selected to reduce the CMV and to give the minimum number of commutations), the peak CMV was reduced by 22.2%, and the peak CMV became ± 7 V d c / 18 instead of ± V d c / 2 in the conventional SVM scheme.
  • In the second method, called the SV-10L scheme, the peak CMV was reduced to ± V d c / 18 In this scheme, ten large active vectors selected from the α β subspace were used during a switching period. The dwelling times of these vectors in the x y plane were determined to nullify the harmonics and were used in the implementation.
  • Notably, the second scheme gave minimum CMV magnitude with constant switching frequency and minimum error vectors. It reduced the peak CMV by 88.8% compared with the conventional SVM scheme.
Moreover, the implementation of the proposed schemes using simple carrier-based PWM approaches was presented. In this approach, two opposite symmetrical triangular carrier waves were utilized. The CMV analysis for the conventional and proposed schemes was presented.
Simulation and experimental results of conventional and proposed PWM schemes were provided to verify their effectiveness and their effect on motor performance. The experimental results showed good agreement with the simulation results by comparing the conventional and the proposed schemes. The proposed schemes have a slightly distorted motor current in the experimental study; therefore, lower efficiency is expected compared to the conventional SVM.

Author Contributions

Conceptualization, and software, S.M.D.; methodology, A.S.A.-K.; validation, S.A. and A.M.M.; formal analysis, I.A.G.; investigation, A.A.A.; resources, M.E.F.; experimental work, M.A.E.; writing—original draft preparation, S.M.D.; writing—review and editing, A.A.A. and A.S.A.-K.; visualization, A.M.M.; supervision, M.E.F.; project administration, S.A. All authors have read and agreed to the published version of the manuscript.

Funding

This research received no external funding.

Institutional Review Board Statement

Not applicable.

Informed Consent Statement

Not applicable.

Data Availability Statement

Not applicable.

Acknowledgments

Open Access funding provided by the Qatar National Library.

Conflicts of Interest

The authors declare no conflict of interest.

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Figure 1. Schematic diagram of nine-phase inverter feeding a symmetrical nine-phase motor.
Figure 1. Schematic diagram of nine-phase inverter feeding a symmetrical nine-phase motor.
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Figure 2. Output-voltage space vector planes corresponding to the switching combinations of the nine-phase VSI.
Figure 2. Output-voltage space vector planes corresponding to the switching combinations of the nine-phase VSI.
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Figure 3. Selected space-vectors of sector 1 in α β subspace corresponding to the traditional and proposed SVM technique. Note that, the asterisks (*) denote the reference.
Figure 3. Selected space-vectors of sector 1 in α β subspace corresponding to the traditional and proposed SVM technique. Note that, the asterisks (*) denote the reference.
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Figure 4. Switching sequence and the corresponding CMV of the selected space vector in sector 1 using traditional and proposed SVM schemes.
Figure 4. Switching sequence and the corresponding CMV of the selected space vector in sector 1 using traditional and proposed SVM schemes.
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Figure 5. Reference and injected signals of carrier-based implementation.
Figure 5. Reference and injected signals of carrier-based implementation.
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Figure 6. RMS-CMV dependency for the analyzed PWM schemes.
Figure 6. RMS-CMV dependency for the analyzed PWM schemes.
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Figure 7.  Simulation results for a nine-phase motor based on the conventional SVM and proposed schemes.
Figure 7.  Simulation results for a nine-phase motor based on the conventional SVM and proposed schemes.
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Figure 8. FFT analysis for the output phase voltage of the conventional SVM and proposed CMVR schemes.
Figure 8. FFT analysis for the output phase voltage of the conventional SVM and proposed CMVR schemes.
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Figure 9. Experimental Setup.
Figure 9. Experimental Setup.
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Figure 10. Experimental results of phase voltage, two of the line currents, and the CMV waveforms for the analyzed PWM schemes.
Figure 10. Experimental results of phase voltage, two of the line currents, and the CMV waveforms for the analyzed PWM schemes.
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Figure 11. Fourier Transform analysis for the motor current for the analyzed PWM schemes.
Figure 11. Fourier Transform analysis for the motor current for the analyzed PWM schemes.
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Table 1. Switching Combination Groups for nine-phase VSI.
Table 1. Switching Combination Groups for nine-phase VSI.
Groups{k,l}Number of StatesType of States
I{9, 0} and {0, 9}2Zero
II{8, 1} and {1, 8}18Active
III{7, 2} and {2, 7}72
IV{6, 3} and {3, 6}170
V{5, 4} and {4, 5}250
Table 2. Switching table for nine-phase VSI and corresponding CMV.
Table 2. Switching table for nine-phase VSI and corresponding CMV.
GroupsThe Decimal Value of the Switching Vectors (*) ± V C M
1(9-0)511 1 2 V d c
(0-9)0
2(8-1)255, 383, 447, 479, 495, 503, 507, 509, 510 7 18 V d c
(1-8)1, 2, 4, 8, 16, 32, 64, 128, 256
3(7-2)127, 191, 223, 239, 247, 251, 253, 254, 319, 351, 367, 375, 379, 381, 382, 415, 431, 439, 443, 445, 446, 471, 475, 477, 478, 487, 491, 493, 494, 499, 501, 502, 505, 506, 508 5 18 V d c
(2-7)3, 5, 6, 9, 10, 12, 17, 18, 20, 24, 33, 34, 36, 40, 48, 65, 66, 68, 72, 80, 96, 129, 130, 132, 136, 144, 160, 192, 257, 258, 260, 264, 272, 288, 320, 384
4(6-3)63, 95, 111, 119, 123, 125, 126, 159, 175, 183, 187, 189, 190, 207, 215, 219, 221, 222, 231, 235, 237, 238, 243, 245, 246, 249, 250, 252, 287, 303, 311, 315, 317, 318, 335, 343, 347, 349, 350, 359, 363, 365, 366, 371, 373, 374, 377, 349, 350, 359, 363, 365, 366, 371, 373, 374, 377, 378, 380, 399, 407, 411, 413, 414, 423, 427, 429, 430, 435, 437, 438, 441, 442, 444, 455, 459, 461, 462, 467, 469, 470, 473, 474, 476, 483, 485, 486, 489, 490, 492, 497, 498, 500, 504 3 18 V d c
(3-6)7, 11, 13, 14, 19, 21, 22, 25, 26, 28, 35, 37, 38, 41, 42, 44, 49, 50, 52, 56, 67, 69, 70, 73, 74, 76, 81, 82, 84, 88, 97, 98, 100, 104, 112, 131, 133, 134, 137, 138, 140, 145, 146, 147, 148, 152, 161, 162, 164, 168, 176, 193194, 196, 200, 208, 224, 259, 261, 262, 265, 266, 268, 273, 274, 276, 280, 289, 290, 292, 296, 304, 321, 322, 324, 328, 336, 352, 385, 388, 392, 400, 416, 448
5(5-4)31, 47, 55, 59, 61, 62, 79, 87, 91, 93, 94, 103, 107, 109, 110, 115, 117, 118, 121, 122, 124, 143, 151, 155, 157, 158, 167, 171, 173, 174, 179, 181, 182, 185, 186, 188, 199, 203, 205, 206, 211, 213, 214, 217, 218, 220, 227, 229, 230, 233, 234, 236, 241, 232, 244, 248, 271, 279, 283, 285, 286, 295, 299, 301, 302, 307, 309, 310, 313, 314, 316, 327, 331, 333, 334, 339, 341, 342, 345, 346, 348 355, 357,
358, 361, 362, 364, 369, 370, 372, 376, 391, 395, 397, 398, 403, 405, 406, 409, 410, 412, 419, 421, 422, 425, 426, 428, 433, 434, 436, 440, 451, 453, 454, 457, 458, 460, 465, 466, 468, 472, 481, 482, 484, 488, 496
1 18 V d c
(4-5)15, 23, 27, 29, 30, 39, 43, 45, 46, 51, 53, 54, 57,
58, 60, 71, 75, 77, 78, 83, 85, 86, 89, 90, 92, 99,
101, 102, 105, 106, 108, 113, 114, 116, 120, 135, 139, 141, 142, 149, 150, 153, 154, 156, 163, 165, 166, 169, 170, 172, 177, 178, 180, 184, 195, 197, 198, 201, 202, 204, 209, 210, 212, 216, 225, 226, 228, 232, 240, 263, 267, 269, 270, 275, 277, 278, 281, 282, 284, 291, 293, 294, 297, 298, 300, 305, 306, 308, 312, 323, 325, 326, 329, 330, 332, 337, 338, 340, 344, 353, 354, 356, 360, 368, 387, 389, 390, 393, 394, 396, 401, 402, 404, 408, 417, 418, 420, 424, 432, 449, 450, 452, 456, 464, 480
(*) The numbers in this column represent the decimal value corresponding to the switching vector, S of each space vector.
Table 3. Classification of the switching vectors for nine-phase VSI based on the corresponding peak CMV.
Table 3. Classification of the switching vectors for nine-phase VSI based on the corresponding peak CMV.
GroupsNumber of Switching VectorsCMV ± V C M
12Maximum 0.5 V d c
218Large 7 V d c / 18
372medium 5 V d c / 18
4170Small 3 V d c / 18
5250Minimum V d c / 18
Total number of switching vectors = 512
Table 4. Selected Zero Vector of AZS Scheme.
Table 4. Selected Zero Vector of AZS Scheme.
SectorVectorsSectorVectorsSectorVectors
1264, 247733, 4781368, 443
2136, 375817, 4941466, 445
3132, 3799272, 2391534, 477
468, 44310264, 2471633, 478
566, 44511136, 3751717, 494
634, 47712132, 37918272, 239
Table 5. Selected Vectors for the SVM-10L Scheme.
Table 5. Selected Vectors for the SVM-10L Scheme.
AngleVectorsAngleVectorsAngleVectors
0451120248−12031
20449140120−10015
40481160124−80271
6048018060−60263
80496−16062−40391
100240−14030−20387
Table 6. Selection of Carrier Waves for The CBPWM of the Analyzed PWM Schemes.
Table 6. Selection of Carrier Waves for The CBPWM of the Analyzed PWM Schemes.
Sector123456789101112131415161718
AZSaNPPPPPPPNNPPPPPPPN
bPNNPPPPPPPNNPPPPPP
cPPPNNPPPPPPPNNPPPP
dPPPPPNNPPPPPPPNNPP
ePPPPPPPNNPPPPPPPNN
fNNPPPPPPPNNPPPPPPP
gPPNNPPPPPPPNNPPPPP
hPPPPNNPPPPPPPNNPPP
iPPPPPPNNPPPPPPPNNP
SV-10LaPPPPPPPPPNNNNNNNNN
bNNPPPPPPPPPNNNNNNN
cNNNNPPPPPPPPPNNNNN
dNNNNNNPPPPPPPPPNNN
eNNNNNNNNPPPPPPPPPN
fPNNNNNNNNNPPPPPPPP
gPPPNNNNNNNNNPPPPPP
hPPPPPNNNNNNNNNPPPP
iPPPPPPPNNNNNNNNNPP
(P) letter denotes v t r i and the (N) letter denotes the opposite carrier of v t r i .
Table 7. Simulation Parameters.
Table 7. Simulation Parameters.
ParameterValueParameterValue
Rated power (hp)1.5No of the pole pairs2
Phase voltage (V)96Frequency (Hz)50
Rated speed (rpm)1430 R r 1 (Ω)1.06
R s (Ω)3.4 L r 1 (mH)5.8
L s (mH)5.8 L m 1 (mH)97
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Dabour, S.M.; Aboushady, A.A.; Elgenedy, M.A.; Gowaid, I.A.; Farrag, M.E.; Abdel-Khalik, A.S.; Massoud, A.M.; Ahmed, S. Symmetrical Nine-Phase Drives with a Single Neutral-Point: Common-Mode Voltage Analysis and Reduction. Appl. Sci. 2022, 12, 12553. https://doi.org/10.3390/app122412553

AMA Style

Dabour SM, Aboushady AA, Elgenedy MA, Gowaid IA, Farrag ME, Abdel-Khalik AS, Massoud AM, Ahmed S. Symmetrical Nine-Phase Drives with a Single Neutral-Point: Common-Mode Voltage Analysis and Reduction. Applied Sciences. 2022; 12(24):12553. https://doi.org/10.3390/app122412553

Chicago/Turabian Style

Dabour, Sherif M., Ahmed A. Aboushady, Mohamed A. Elgenedy, I. A. Gowaid, Mohamed Emad Farrag, Ayman S. Abdel-Khalik, Ahmed M. Massoud, and Shehab Ahmed. 2022. "Symmetrical Nine-Phase Drives with a Single Neutral-Point: Common-Mode Voltage Analysis and Reduction" Applied Sciences 12, no. 24: 12553. https://doi.org/10.3390/app122412553

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