Search Results (24)

In reconfigurable radio frequency (RF) microsystems, the interconnect structure critically affects high-frequency signal integrity, and the accuracy of electromagnetic (EM) modeling directly determines the overall system performance. Conventional neural network-based surrogate models mainly focus on minimizing numerical errors, while neglecting essential physical constraints, such as causality and passivity, thereby limiting their applicability in both time and frequency domains. This paper proposes a physics-constrained Neuro-Transfer surrogate model with a broadband output architecture to directly predict S-parameters over the 1–50 GHz range. Causality and passivity are enforced through dedicated regularization terms during training. Furthermore, a particle swarm optimization (PSO)-based multi-objective intelligent optimization framework is developed, incorporating fixed-weight normalization and a linearly decreasing inertia weight strategy to simultaneously optimize the S11, S21, and S22 performance of a quasi-coaxial TSV composite structure. Target values are set to −25 dB, −0.54 dB, and −24 dB, respectively. The optimized structural parameters yield prediction-to-simulation deviations below 1 dB, with an average prediction error of 2.11% on the test set. Full article

Advanced packaging represents a crucial technological evolution aimed at overcoming limitations posed by Moore’s Law, driving the semiconductor industry from two-dimensional toward three-dimensional integrated structures. The increasing complexity and miniaturization of electronic devices have significantly heightened the challenges associated with failure analysis during process development. The focused ion beam–scanning electron microscope (FIB-SEM), characterized by its high processing precision and exceptional imaging resolution, has emerged as a powerful solution for the fabrication, defect localization, and failure analysis of micro- and nano-scale devices. This paper systematically reviews the innovative applications of FIB-SEM in the research of core issues, such as through-silicon-via (TSV) defects, bond interfacial failures, and redistribution layer (RDL) electromigration. Additionally, the paper discusses multimodal integration strategies combining FIB-SEM with advanced analytical techniques, such as high-resolution three-dimensional X-ray microscopy (XRM), electron backscatter diffraction (EBSD), and spectroscopy. Finally, it provides a perspective on the emerging applications and potential of frontier technologies, such as femtosecond-laser-assisted FIB, in the field of advanced packaging analysis. Full article

Through-Silicon-Via (TSV) technology is of crucial importance in the process of defect-free copper filling in vias. In this study, the small molecule 2-mercapto-1-methylimidazole (SN2) is proposed as a new leveler. It enables bottom-up super-filling of blind vias without the need for inhibitors. Atomic force microscopy (AFM), X-ray diffraction (XRD), and XPS were employed to characterize the surface morphology, crystal structure, and adsorption properties of copper crystals in these systems. Meanwhile, by means of electrochemical measurements, the inhibitory effect of the leveler SN2 on copper ion deposition and the synergistic effect between SN2 molecules and other additives were investigated. The LSV test indicated that additive SN2 inhibited copper electrodeposition after being added to the plating solution, and this inhibitory effect enhanced with increasing SN2 concentration. In the actual plating wafer test (1 ASD plating for 1 min, 5 ASD plating for 5 min, and 10 ASD plating for 1 h), the best plating effect was achieved at 3 ppm, which verified the conjecture of the galvanostatic measurements. Moreover, XPS and computer simulations revealed that SN2 could be adsorbed onto the copper surfaces. This work will inspire the discovery of new effective levelers in the future. Full article

The thermal through-silicon-via (TTSV) has a serious thermal stress problem due to the mismatch of the coefficient of thermal expansion between the Si substrate and filler metal. At present, the thermal stress characteristics and strain mechanism of TTSV are mainly concerned with increases in temperature, and its temperature range is concentrated between 173 and 573 K. By employing finite element analysis and a device simulation method based on temperature-dependent material properties, the impact of TTSV thermal stress on metal-oxide-semiconductor field-effect transistor (MOSFET) properties is investigated under cooling down from room temperature to the ultra-low temperature (20 mK), where the magnitude of thermal stress in TTSV is closely associated with the TTSV diameter and results in significant tension near the Cu-Si interface and consequently increasing the likelihood of delamination and cracking. Considering the piezoresistive effect of the Si substrate, both the TTSV diameter and the distance between TTSV and MOSFET are found to have more pronounced effects on electron mobility along [100] crystal orientation and hole mobility along [110] crystal orientation. Applying a gate voltage of 3 V, the saturation current for the 45 nm-NMOS transistor oriented along channel [100] experiences a variation as high as 34.3%. Moreover, the TTSV with a diameter of 25 μm generates a change in MOSFET threshold voltage up to −56.65 mV at a distance as short as 20 μm. The influences exerted by the diameter and distance are consistent across carrier mobility, saturation current, and threshold voltage parameters. Full article

A wafer-scale process for fabricating monolithically suspended nano-perforated membranes (NPMs) with integrated support structures into silicon is developed. Existing fabrication methods are suitable for many desired geometries, but face challenges related to mechanical robustness and fabrication complexity. We demonstrate a process that utilizes the cyclic deposit, remove, etch, and multi-step (DREM) process for directional etching of high-aspect-ratio (HAR) 300 nm in diameter nano-pores of 700 nm pitch. Subsequently, a buried cavity beneath the nano-pores is formed by switching to an isotropic etch, which effectively yields a thick NPM. Due to this architecture’s flexibility and process robustness, structural parameters such as membrane thickness, diameter, integrated support structures, and cavity height can be adjusted, allowing a wide range of NPM geometries. This work presents NPMs with final thicknesses of 4.5 µm, 6.5 µm, and 12 µm. Detailed steps of this new approach are discussed, including the etching of a through-silicon-via to establish the connection of the NPM to the macro-world. Our approach to fabricating NPMs within single-crystal silicon overcomes some of the limitations of previous methods. Owing to its monolithic design, this NPM architecture permits further enhancements through material deposition, pore size reduction, and surface functionalization, broadening its application potential for corrosive environments, purification and separation processes, and numerous other advanced applications. Full article

The main challenges in 3D metrology involve measuring TSVs etched with very high aspect ratios, where the via depth to diameter ratio approaches 10:1–20:1. In this paper, we introduce an innovative approach to enhance our in-house spectroscopic reflectometer module by integrating aperture technology, resulting in a substantial amplification of interference signals. Our system offers the flexibility to conduct measurements on an average number of TSVs, individual TSVs, or specific periodic arrays of TSVs. Additionally, we demonstrate the utility of the spectroscopic reflectometer as a non-destructive, high-speed metrology solution for in-line monitoring of TSV etch uniformity. Through a series of experimental trials in a reactive ion etch (RIE) process, we show that leveraging feedback data from the reflectometer leads to marked improvements in etch depth uniformity. Full article

Three-dimensional (3D) integration based on through-silicon-via (TSV) technology provides a solution to the miniaturization of electronic systems. In this paper, novel integrated passive devices (IPDs) including capacitor, inductor, and bandpass filter are designed by employing TSV structures. For lower manufacturing costs, polyimide (PI) liners are used in the TSVs. The influences of structural parameters of TSVs on the electrical performance of the TSV-based capacitor and inductor are individually evaluated. Moreover, with the topologies of capacitor and inductor elements, a compact third-order Butterworth bandpass filter with a central frequency of 2.4 GHz is developed, and the footprint is only 0.814 mm × 0.444 mm. The simulated 3-dB bandwidth of the filter is 410 MHz, and the fraction bandwidth (FBW) is 17%. Besides, the in-band insertion loss is less than 2.63 dB, and the return loss in the passband is better than 11.4 dB, showing good RF performance. Furthermore, as the filter is fully formed by identical TSVs, it not only features a simple architecture and low cost, but also provides a promising idea for facilitating the system integration and layout camouflaging of radio frequency (RF) devices. Full article

Micro-electro-mechanical system (MEMS) pressure sensors play a significant role in pulse wave acquisition. However, existing MEMS pulse pressure sensors bound with a flexible substrate by gold wire are vulnerable to crush fractures, leading to sensor failure. Additionally, establishing an effective mapping between the array sensor signal and pulse width remains a challenge. To solve the above problems, we propose a 24-channel pulse signal acquisition system based on a novel MEMS pressure sensor with a through-silicon-via (TSV) structure, which connects directly to a flexible substrate without gold wire bonding. Firstly, based on the MEMS sensor, we designed a 24-channel pressure sensor flexible array to collect the pulse waves and static pressure. Secondly, we developed a customized pulse preprocessing chip to process the signals. Finally, we built an algorithm to reconstruct the three-dimensional pulse wave from the array signal and calculate the pulse width. The experiments verify the high sensitivity and effectiveness of the sensor array. In particular, the measurement results of pulse width are highly positively correlated with those obtained via infrared images. The small-size sensor and custom-designed acquisition chip meet the needs of wearability and portability, meaning that it has significant research value and commercial prospects. Full article

Through-silicon-via (TSV)-based coaxial line techniques can reduce the high-frequency loss due to the low resistivity in the silicon substrate and thus can improve the efficiency of vertical signal transmission. Moreover, a TSV-based coaxial structure allows easily realizing the impedance matching in RF/microwave systems for excellent electrical performance. However, due to the limitations of existing available dielectric materials and the difficulties and challenges in the manufacturing process, ideal coaxial TSVs are not easy to obtain, and thus, the achieved electrical performance might be unexpected. In order to increase the flexibility of designing and manufacturing TSV-based coaxial structures and to better evaluate the fabricated devices, modeling and analysis theories of the corresponding high-frequency electrical performance are proposed in the paper. The theories are finally well validated using the finite-element simulation results, hereby providing guiding rules for selecting materials and improving manufacturing techniques in the practical process, so as to optimize the high-frequency performance of the TSV structures. Full article

Along with deep scaling transistors and complex electronics information exchange networks, very-large-scale-integrated (VLSI) circuits require high performance and ultra-low power consumption. In order to meet the demand of data-abundant workloads and their energy efficiency, improving only the transistor performance would not be sufficient. Super high-speed microprocessors are useless if the capacity of the data lines is not increased accordingly. Meanwhile, traditional on-chip copper interconnects reach their physical limitation of resistivity and reliability and may no longer be able to keep pace with a processor’s data throughput. As one of the potential alternatives, carbon nanotubes (CNTs) have attracted important attention to become the future emerging on-chip interconnects with possible explorations of new development directions. In this paper, we focus on the electrical, thermal, and process compatibility issues of current on-chip interconnects. We review the advantages, recent developments, and dilemmas of CNT-based interconnects from the perspective of different interconnect lengths and through-silicon-via (TSV) applications. Full article

Bumpless Build Cube (BBCube) using Wafer-on-Wafer (WOW) and Chip-on-Wafer (COW) for Tera-Scale Three-Dimensional Integration (3DI) is discussed. Bumpless interconnects between wafers and between chips and wafers are a second-generation alternative to the use of micro-bumps for WOW and COW technologies. WOW and COW technologies for BBCube can be used for homogeneous and heterogeneous 3DI, respectively. Ultra-thinning of wafers down to 4 μm offers the advantage of a small form factor, not only in terms of the total volume of 3D ICs, but also the aspect ratio of Through-Silicon-Vias (TSVs). Bumpless interconnect technology can increase the number of TSVs per chip due to the finer TSV pitch and the lower impedance of bumpless TSV interconnects. In addition, high-density TSV interconnects with a short length provide the highest thermal dissipation from high-temperature devices such as CPUs and GPUs. This paper describes the process platform for BBCube WOW and COW technologies and BBCube DRAMs with high speed and low IO buffer power by enhancing parallelism and increasing yield by using a vertically replaceable memory block architecture, and also presents a comparison of thermal characteristics in 3D structures constructed with micro-bumps and BBCube. Full article

As thermal management in 3DIC integration becomes increasingly important in advanced semiconductor node processes, novel experimental and modeling approaches are in great demand to reveal the critical material issues involving multiscale microstructures that govern the behavior of through-silicon-via (TSV) protrusion. Here, a coarse-grained phase-field crystal model properly coupled with mechanics through the atomic density field is used to simulate the formation of polycrystalline structures and protrusion of nano-TSVs from the atomic scale. TSVs with different grain structures are directly loaded, and protrusion/intrusion profiles are obtained along with displacement, stress, and strain fields. Thermodynamic driving forces from external loadings and the mismatch of Young’s modulus between adjoining grains as well as detailed displacement and strain distributions are ascribed to control the complex deformation in TSVs. TSVs with sizes up to around 30 nm and an aspect ratio of 4 are successfully investigated, and a further increase in the size and aspect ratio to cover the micrometer range is feasible, which lays down a solid basis toward a multiscale material database for simulation inputs to the design of TSV-based 3DIC integration and relevant electronic design automation (EDA) tools. Full article

Tuning fork gyroscopes (TFGs) are promising for potential high-precision applications. This work proposes and experimentally demonstrates a novel high-Q dual-mass tuning fork microelectromechanical system (MEMS) gyroscope utilizing three-dimensional (3D) packaging techniques. Except for two symmetrically decoupled proof masses (PM) with synchronization structures, a symmetrically decoupled lever structure is designed to force the antiparallel, antiphase drive mode motion and eliminate low frequency spurious modes. Thermoelastic damping (TED) and anchor loss are greatly reduced by the linearly coupled, momentum- and torque-balanced antiphase sense mode. Moreover, a novel 3D packaging technique is used to realize high Q-factors. A composite substrate encapsulation cap, fabricated by through-silicon-via (TSV) and glass-in-silicon (GIS) reflow processes, is anodically bonded to the wafer-scale sensing structures. A self-developed control circuit is adopted to realize loop control and characterize gyroscope performances. It is shown that a high-reliability electrical connection, together with a high air impermeability package, can be fulfilled with this 3D packaging technique. Furthermore, the Q-factors of the drive and sense modes reach up to 51,947 and 49,249, respectively. This TFG realizes a wide measurement range of ±1800 °/s and a high resolution of 0.1°/s with a scale factor nonlinearity of 720 ppm after automatic mode matching. In addition, long-term zero-rate output (ZRO) drift can be effectively suppressed by temperature compensation, inducing a small angle random walk (ARW) of 0.923°/√h and a low bias instability (BI) of 9.270°/h. Full article

This paper provides an overview of 3D detectors fabrication technology developed in the clean room of the Microelectronics Institute of Barcelona (IMB-CNM). Emphasis is put on manufacturability, especially on stress and bow issues. Some of the technological solutions proposed at IMB-CNM to improve manufacturability are presented. Results and solutions from other research institutes are also mentioned. Analogy with through-silicon-via technology is drawn. This article aims at giving hints of the technology improvements implemented to upgrade from a R&D process to a mature technology. Full article

For performance-driven systems such as space-based applications, it is important to maximize the gain of radio-frequency amplifiers (RFAs) with a certain tolerance against radiation, temperature effects, and small form factor. In this work, we present a K-band, compact high-gain RFA using an f_T-doubler topology in a silicon-germanium (SiGe) heterojunction bipolar transistors (HBTs) technology platform. The through-silicon vias (TSVs), typically used for small-size chip packaging purposes, have been effectively utilized as an adjustable matching element for input impedance, reducing the overall area of the chip. The proposed RFA, fabricated in a modest 0.35 µm SiGe technology, achieves a gain of 14.1 dB at 20 GHz center frequency, and a noise figure (NF) of 11.2 dB at the same frequency, with a power consumption of 3.3 mW. The proposed design methodology can be used for achieving high gain, avoiding a complex multi-stage amplifier design approach. Full article