Search Results (8)

With the advancement of the semiconductor industry into the sub-10 nm regime, high-performance, low-energy transistors have become important, and gate-all-around junctionless field-effect transistors (GAA-JLFETs) have been developed to meet the demands. Silicon (Si) is still the dominant semiconductor material, but other potential alternatives, such as gallium arsenide (GaAs), provide much higher electron mobility, improving the drive current and switching speed. In this study, our contributions include a comparative analysis of Si and GaAs-based cylindrical GAA-JLFETs, using threshold voltage behavior, electrostatic control, short channel effects, subthreshold slope, drain-induced barrier lowering, and leakage current as the metrics for performance evaluation. A comprehensive analytical modeling approach is employed, solving Poisson’s equation and utilizing numerical simulations to assess device characteristics using the ATLAS SILVACO tool under varying channel lengths and gate biases. Comparisons between Si and GaAs-based devices show what trade-offs exist and what the material engineering strategies are to use the advantages of GaAs while minimizing some disadvantages. The results of the study are a valuable contribution to the design and optimization of next-generation FET architectures, pointing the direction for enabling next-generation beyond CMOS technology. Full article

The surge in demand for 3D MOSFETs, such as FinFETs, driven by recent technological advances, is explored in this review. FinFETs, positioned as promising alternatives to bulk CMOS, exhibit favorable electrostatic characteristics and offer power/performance benefits, scalability, and control over short-channel effects. Simulations provide insights into functionality and leakage, addressing off-current issues common in narrow band-gap materials within a CMOS-compatible process. Multiple structures have been introduced for FinFETs. Moreover, some studies on the fabrication of FinFETs using different materials have been discussed. Despite their potential, challenges like corner effects, quantum effects, width quantization, layout dependencies, and parasitics have been acknowledged. In the post-planar CMOS landscape, FinFETs show potential for scalability in nanoscale CMOS, which leads to novel structures for them. Finally, recent developments in FinFET-based sensors are discussed. In a general view, this comprehensive review delves into the intricacies of FinFET fabrication, exploring historical development, classifications, and cutting-edge ideas for the used materials and FinFET application, i.e., sensing. Full article

Electroosmotic flow (EOF) is of utmost significance due to its numerous practical uses in controlling flow at micro/nanoscales. In the present study, the time–periodic EOF of a viscoelastic fluid is statistically analyzed using a short 10:1 constriction microfluidic channel joining two reservoirs on either side. The flow is modeled using the Oldroyd-B (OB) model and the Poisson–Boltzmann model. The EOF of a highly concentrated polyacrylamide (PAA) aqueous solution is investigated under the combined effects of an alternating current (AC) electric field and a direct current (DC) electric field. Power-law degradation is visible in the energy spectra of the velocity fluctuations over a wide frequency range, pointing to the presence of elastic instabilities in the EOF. The energy-spectra curves of the velocity fluctuations under a DC electric field exhibit peaks primarily beneath 20 Hz, with the greatest peak being observed close to 6 Hz. When under both DC and AC electric fields, the energy spectra of the velocity fluctuations exhibit a peak at the same frequency as the AC electric field, and the highest peak is obtained when the frequency of the AC electric field is near 6 Hz. Additionally, the frequency of the AC electric field affects how quickly the viscoelastic EOF flows. Higher flow rates are obtained at relatively low frequencies compared to under the DC electric field, and the greatest flow rate is found close to 6 Hz. But as the frequency rises further, the flow rate falls. The flow rate falls to a level below the DC electric field when the frequency is sufficiently high. Full article

Systems-on-Chip’s (SoC) design complexity demands a high-performance linear regulator architecture to maintain a stable operation for the efficient power management of today’s devices. Over the decades, the low-dropout (LDO) voltage regulator design has gained attention due to its design scalability with better performance in various application domains. Industry professionals as well as academia have put forward their innovations such as event-driven explicit time-coding, exponential-ratio array, switched RC bandgap reference circuit, etc., to make a trade-off between several performance parameters such as die area, ripple rejection, supply voltage range, and current efficiency. However, current LDO architectures in micro and nanometer complementary metal–oxide–semiconductor (CMOS) technology face some challenges, such as short channel effects, gate leakage, fabrication difficulty, and sensitivity to process variations at nanoscale. This review presents the LDO architectures, optimization techniques, and performance comparisons in different LDO design domains such as digital, analog, and hybrid. In this review, various state-of-the-art circuit topologies, deployed for the betterment of LDO performance and focusing on the specific parameter up-gradation to the overall improvement of the functionality, are framed, which will serve as a comparative study and reference for researchers. Full article

Ever increasing demands of data traffic makes the transition to 6G communications in the 300 GHz band inevitable. Short-channel field-effect transistors (FETs) have demonstrated excellent potential for detection and generation of terahertz (THz) and sub-THz radiation. Such transistors (often referred to as TeraFETs) include short-channel silicon complementary metal oxide (CMOS). The ballistic and quasi-ballistic electron transport in the TeraFET channels determine the TeraFET response at the sub-THz and THz frequencies. TeraFET arrays could form plasmonic crystals with nanoscale unit cells smaller or comparable to the electron mean free path but with the overall dimensions comparable with the radiation wavelength. Such plasmonic crystals have a potential of supporting the transition to 6G communications. The oscillations of the electron density (plasma waves) in the FET channels determine the phase relations between the unit cells of a FET plasmonic crystal. Excited by the impinging radiation and rectified by the device nonlinearities, the plasma waves could detect both the radiation intensity and the phase enabling the line-of-sight terahertz (THz) detection, spectrometry, amplification, and generation for 6G communication. Full article

The current electronics industry has used the aggressive miniaturization of solid-state devices to meet future technological demands. The downscaling of characteristic device dimensions into the sub-10 nm regime causes them to fall below the electron–phonon scattering length, thereby resulting in a transition from quasi-ballistic to ballistic carrier transport. In this study, a well-established Monte Carlo model is employed to systematically investigate the effects of various parameters such as applied voltage, channel length, electrode lengths, electrode doping and initial temperature on the performance of nanoscale silicon devices. Interestingly, from the obtained results, the short channel devices are found to exhibit smaller heat generation, with a 2 nm channel device having roughly two-thirds the heat generation rate observed in an 8 nm channel device, which is attributed to reduced carrier scattering in the ballistic transport regime. Furthermore, the drain contacts of the devices are identified as critical design areas to ensure safe and efficient performance. The heat generation rate is observed to increase linearly with an increase in the applied electric field strength but does not change significantly with an increase in the initial temperature, despite a marked reduction in the electric current flowing through the device. Full article

With the development of new designs and materials for nano-scale transistors, vertical Gate-All-Around Field Effect Transistors (vGAAFETs) with germanium as channel materials have emerged as excellent choices. The driving forces for this choice are the full control of the short channel effect and the high carrier mobility in the channel region. In this work, a novel process to form the structure for a VGAA transistor with a Ge channel is presented. The structure consists of multilayers of Si_0.2Ge_0.8/Ge grown on a Ge buffer layer grown by the reduced pressure chemical vapor deposition technique. The Ge buffer layer growth consists of low-temperature growth at 400 °C and high-temperature growth at 650 °C. The impact of the epitaxial quality of the Ge buffer on the defect density in the Si_0.2Ge_0.8/Ge stack has been studied. In this part, different thicknesses (0.6, 1.2 and 2.0 µm) of the Ge buffer on the quality of the Si_0.2Ge_0.8/Ge stack structure have been investigated. The thicker Ge buffer layer can improve surface roughness. A high-quality and atomically smooth surface with RMS 0.73 nm of the Si_0.2Ge_0.8/Ge stack structure can be successfully realized on the 1.2 µm Ge buffer layer. After the epitaxy step, the multilayer is vertically dry-etched to form a fin where the Ge channel is selectively released to SiGe by using wet-etching in HNO₃ and H₂O₂ solution at room temperature. It has been found that the solution concentration has a great effect on the etch rate. The relative etching depth of Ge is linearly dependent on the etching time in H₂O₂ solution. The results of this study emphasize the selective etching of germanium and provide the experimental basis for the release of germanium channels in the future. Full article

Among multi-gate field effect transistor (FET) structures, FinFET has better short channel control and ease of manufacturability when compared to other conventional bulk devices. The radio frequency (RF) performance of FinFET is affected by gate-controlled parameters such as transconductance, output conductance, and total gate capacitance. In recent years, high-k spacer dielectric materials for manufacturing nanoscale devices are being widely explored because of their better electrostatic control and being less affected by short channel effects (SCEs). In this paper, we aim to explore the potential benefits of using different Dual-k spacers on source and drain, respectively: (AsymD-kk) trigate FinFET structure to improve the analog/RF figure of merit (FOM) for low-power operation at 14 nm gate length. It has been observed from the results that the AsymD-kk FinFET structure improves the coupling of the gate fringe field to the underlap region towards the source and drain side, improving the transconductance (g_m) and output conductance (g_ds) at the cost of an increase in Miller capacitance. Furthermore, to reduce the drain field influence on the channel region, we also studied the effect of asymmetric drain extension length on a Dual-kk FinFET structure. It can be observed that the new asymmetric drain extension structures significantly improve the cutoff frequency (f_T) and maximum oscillation frequency (f_max) given the significant reduction of inner fringe capacitance towards drain side due to the shifting of the drain extension’s doping concentration away from the gate edge. Therefore, the asymmetric drain extension Dual-kk trigate FinFET (AsymD-kk_DE) is a new structure that combines different Dual-k spacers on the source and drain and asymmetric drain extension on a single silicon on insulator (SOI) platform to enhance the almost all analog/RF FOM. The proposed structure is verified by technology computer-aided design (TCAD) simulations with varying device physical parameters such as fin height, fin width, aspect ratio, spacer width, spacer material, etc. From comprehensive 3D device simulation, we have demonstrated that the proposed device is superior in performance to a conventional trigate FinFET and can be used to design low-power digital circuits. Full article