Search Results (29)

Passive components in integrated circuits occupy significant areas and increase production costs, driving the demand for compact alternatives. This study presents a generalized, electronically controllable positive/negative floating impedance multiplier implemented in TSMC 180 nm CMOS technology. To achieve a compact layout, the architecture utilizes custom-designed operational transconductance amplifiers (OTAs). The circuit operates on a lossless principle, scaling resistance, capacitance, and inductance values within a wide multiplication range of −100 to +100 using only a single base element. Comprehensive LTspice simulations including PVT, Monte Carlo, THD, and noise analyses verify the design’s stable operation, low distortion, and favorable noise characteristics across various filter configurations. Furthermore, practical feasibility is validated through SPICE simulations using commercial LM13700 OTA, confirming consistent behavior for real-world applications. The proposed active topology occupies a compact core area of only 5831 μm². By scaling down large passive components, this design decreases the overall system-level footprint, providing a versatile and area-efficient solution for tunable analog IC applications. It should be noted that the reported 5831 μm² corresponds to the active core only, while the effective system-level area benefit depends on the selected base impedance and the target application. Full article

In this paper, a low-cost manual micro- and nano-displacement adjustment mechanism is proposed, based on the principle of flexible hinge transmission and micro-displacement scaling. The manual micro- and nano-displacement platform consists of a micrometer input platform, a nano-output platform, a differential head, and a strain displacement sensor. Firstly, a micro-displacement reduction mechanism based on a flexible beam triangular mechanism and a compact asymmetric flexible beam guiding mechanism are proposed, and a theoretical model is established for static mechanical characteristics, such as the displacement reduction multiplier, guiding stiffness, maximum stress, etc., and this is analyzed and verified by finite element simulation. The software and hardware system of the strain displacement sensor is designed and developed, and the calibration experiments of the strain displacement sensor are completed. Finally, the micro-displacement reduction times, resolution, stability, repeat positioning accuracy, load capacity and travel of the manual micro–nano-displacement platform were analyzed and experimented. The results show that when the input range of the micrometer input platform is 0–1 mm, the travel of the nano-output platform is about 0–16 μm; when a differential head with a step resolution of 2 μm is used to input 2 μm micro-displacement, the minimum displacement output of the nano-output platform is about 35.4 nm; the theoretical and simulated values of the reduction multiple of the micro–nano-displacement are 57.29 and 56.69, respectively; the calibration experiment is performed by the self-developed strain sensors, and capacitive displacement sensors measured the reduction multiples of 57.74 and 62.67, respectively, with high consistency; the vibration range of the platform after the displacement adjustment is about ±30 nm, and the load of 0–300 g has less influence on the output characteristics of the platform. Full article

This paper presents a comprehensive comparative analysis of high-voltage, high-frequency pulse generation techniques for Pockels cell drivers. These drivers are critical in electro-optic systems for laser modulation, where nanosecond-scale voltage pulses with amplitudes of several kilovolts are required. The study reviews key design challenges, with particular emphasis on thermal management strategies, including air, liquid, solid-state, and phase-change cooling methods. Different high-voltage, high-frequency pulse generation architectures including vacuum tubes, voltage multipliers, Marx generators, Blumlein structures, pulse-forming networks, Tesla transformers, switching-mode power supplies, solid-state switches, and high-voltage operational amplifiers are systematically evaluated with respect to cost, complexity, stability, and their suitability for driving capacitive loads. The analysis highlights hybrid approaches that integrate solid-state switching with modular multipliers or pulse-forming circuits as offering the best balance of efficiency, compactness, and reliability. The findings provide practical guidelines for developing next-generation high-performance Pockels cell drivers optimized for advanced optical and laser applications. Full article

Hybrid-electric aircraft require a reliable power distribution architecture. The electrical drive system is connected to the power source via a DC-link composed mostly of capacitors—one of the faultiest power electronic components. In order to ensure the safe operation of the aircraft, DC-link capacitor condition monitoring is needed. The main requirements for such an algorithm are low data consumption and the possibility to use it in generator- or battery-powered systems. The proposed discharge-based repetitive recursive least squares (RRLS) method provides satisfactory estimates utilizing small data packages. Its execution during capacitor discharge makes it independent from the power source type. Based on the capacitor’s physical parameters, the computational complexity of the estimation process is reduced. Simulation validation and experimental tests were conducted. An analysis was carried out in a capacitance range between 705 μF and 1175 μF. The effective range of the algorithm is 881 μF–1044 μF, with an estimation error of less than 5%. Additionally, a range of changes in the time constant of the multiplier of 0.1–10 was tested in the simulation study. Full article

For data-intensive applications like edge AI and image processing, we present a new reconfigurable 8T SRAM-based in-memory computing (IMC) macro designed for high-performance and energy-efficient operation. This architecture mitigates von Neumann limitations through numerous major breakthroughs. We built a new architecture with an adjustable capacitance array to substantially increase the multiply-and-accumulate (MAC) engine’s accuracy. It achieves 10–20 TOPS/W and >95% accuracy for 4–10-bit operations and is robust across PVT changes. By supporting binary and ternary neural networks (BNN/TNN) with XNOR-and-accumulate logic, a dual-mode inference engine further expands capabilities. With sub-5 ns mode switching, it can achieve up to 30 TOPS/W efficiency and >97% accuracy. In-memory Hamming error correction is implemented directly using integrated XOR circuitry. This technique eliminates off-chip ECC with >99% error correction and >98% MAC accuracy. Machine learning-aided co-optimization ensures sense amplifier dependability. To ensure CMOS compatibility, the macro may perform Boolean logic operations using normal 8T SRAM cells. Comparative circuit-level simulations show a 31.54% energy efficiency boost and a 74.81% delay reduction over other SRAM-based IMC solutions. These improvements make our macro ideal for real-time AI acceleration, cryptography, and next-generation edge computing, enabling advanced compute-in-memory systems. Full article

The authors of this study suggest an improvement to their recently released quadruple-diode boost regulator (QDBC), which may be used in two configurations: without or with a voltage multiplier unit (VMU). This voltage multiplier unit consists of two switch capacitors diagonally connected across two diodes, or vice versa. During each operational cycle, energy can be stored and released through the switch capacitive filters and inductive chokes, increasing voltage gain and decreasing output fluctuation. ANSOFT/SIMPLORER 7, PLECS 4.9.5, and SIMULINK 2021a are further used to simulate the proposed regulator’s linearized version to investigate its frequency response and stability. Hence, to improve the harmonic performance of the proposed regulator, the authors of this study used a delta modulation current regulator (DMCR), sometimes referred to as a variable bandwidth delta modulation current regulator. The findings show that the QDBC has, when using the DMCR, a voltage gain of $1+D/{(1-D)}^2$, an efficiency of 97%, and a shorter settling time of 0.04 s when compared to other DC-DC regulators (SEPIC, boost, and quadratic boost). Finally, to validate the theoretical analysis and simulation results of the proposed QDBC structure, a 250 W regulator prototype was built utilizing similar design exercise requirements. Full article

This article presents a power-efficient DC-DC converter based on a switched-capacitor (SC) cell in power management systems supplied for fully integrated photovoltaic (PV) modules. These modules shall provide high-performance point-of-load voltage regulation. The primary objective of this study is to better utilize capacitance and switches by selecting a proper SC topology in order to improve the power efficiency of SC converters. A general steady-state performance model is investigated to optimize and compare a variety of SC DC-DC topologies. The investigation method relies on a charge-multiplier approach and considers the impact of area constraint on capacitors. To identify the most suitable topology for a given conversion ratio, the performance-limit metrics of SC converters are calculated. The analysis provides framework to determine optimum switch size and switching frequency for a two-phase 3:1 series–parallel converter for a target load current of 10 mA implemented on a 22 nm process technology. The results shows that a minimum of 250 MHz switching frequency is desirable for achieving a target efficiency greater than 85% while maintaining the minimum output voltage of 0.34 V. The analysis results are verified through MATLAB and PSpice-based simulations. Full article

The capacitated multi-item lot-sizing problem, referred to as the CLSP, is to determine the lot sizes of products in each period in a given planning horizon of finite periods, meeting the product demands and resource limits in each period, and to minimize the total cost, consisting of the production, inventory holding, and setup costs. CLSPs are often encountered in industry production settings and they are considered NP-hard. In this paper, we propose a Lagrange relaxation (LR) approach for their solution. This approach relaxes the capacity constraints to the objective function and thus decomposes the CLSP into several uncapacitated single-item problems, each of which can be easily solved by dynamic programming. Feasible solutions are achieved by solving the resulting transportation problems and a fixup heuristic. The Lagrange multipliers in the relaxed problem are updated by using subgradient optimization. The experimental results show that the LR approach explores high-quality solutions and has better applicability compared with other commonly used solution approaches in the literature. Full article

In recent years, the variability in the composition of cement raw materials has increasingly impacted the quality of cement products. However, there has been relatively little research on the homogenization effects of equipment in the cement production process. Existing studies mainly focus on the primary functions of equipment, such as the grinding efficiency of ball mills, the thermal decomposition in cyclone preheaters, and the thermal decomposition in rotary kilns. This study selected four typical pieces of equipment with significant homogenization functions for an in-depth investigation: ball mills, pneumatic homogenizing silos, cyclone preheaters, and rotary kilns. To assess the homogenization efficacy of each apparatus, scaled-down models of these devices were constructed and subjected to simulated experiments. To improve experimental efficiency and realistically simulate actual production conditions in a laboratory setting, this study used the uniformity of the electrical capacitance of mixed powders instead of compositional uniformity to analyze homogenization effects. The test material in the experiment consisted of a mixture of raw meal from a cement factory with a high dielectric constant and Fe₃O₄ powder. The parallel plate capacitance method was employed to ascertain the capacitance value of the mixed powder prior to and subsequent to treatment by each equipment model. The fluctuation of the input and output curves was analyzed, and the standard deviation (S), coefficient of variation (R), and homogenization multiplier (H) were calculated in order to evaluate the homogenization effect of each equipment model on the raw meal. The findings of the study indicated that the pneumatic homogenizer exhibited an exemplary homogenization effect, followed by the ball mill. For the ball mill, a higher proportion of small balls in the gradation can significantly enhance the homogenization effect without considering the grinding efficiency. The five-stage cyclone preheater also has a better homogenization effect, while the rotary kiln has a less significant homogenization effect on raw meal. Finally, the raw meal processed by each equipment model was used for clinker calcination and the preparation of cement mortar samples. After curing for three days, the compressive and flexural strengths of the samples were tested, thereby indirectly verifying the homogenization effect of each equipment model on the raw meal. This study helps to understand the homogenization process of raw materials by equipment in cement production and provides certain reference and data support for equipment selection, operation optimization, and quality control in the cement production process. Full article

In this paper, a new negative lossless grounded capacitance multiplier (GCM) circuit based on a Current Feedback Operational Amplifier (CFOA) is presented. The proposed circuit includes a single CFOA, four resistors, and a grounded capacitor. In order to reduce the power consumption, the internal structure of the CFOA is realized with dynamic threshold-voltage MOSFET (DTMOS) transistors. The effects of parasitic components on the operating frequency range of the proposed circuit are investigated. The simulation results were obtained with the SPICE program using 0.13 µm IBM CMOS technology parameters. The total power consumption of the circuit was 1.6 mW. The functionality of the circuit is provided by the capacitance cancellation circuit. PVT (Process, Voltage, Temperature) analyses were performed to verify the robustness of the proposed circuit. An experimental study is provided to verify the operability of the proposed negative lossless GCM using commercially available integrated circuits (ICs). Full article

Two-dimensional nanomaterials hold great promise as electrode materials for the construction of excellent electrochemical energy storage and transformation apparatuses. In the study, metallic layered cobalt sulfide was, firstly, applied to the area of energy storage as a supercapacitor electrode. By a facile and scalable method for cathodic electrochemical exfoliation, metallic layered cobalt sulfide bulk can be exfoliated into high-quality and few-layered nanosheets with size distributions in the micrometer scale range and thickness in the order of several nanometers. With a two-dimensional thin sheet structure of metallic cobalt sulfide nanosheets, not only was a larger active surface area created, but also, the insertion/extraction of ions in the procedure of charge and discharge were enhanced. The exfoliated cobalt sulfide was applied as a supercapacitor electrode with obvious improvement compared with the original sample, and the specific capacitance increased from 307 F∙g⁻¹ to 450 F∙g⁻¹ at the current density of 1 A∙g⁻¹. The capacitance retention rate of exfoliated cobalt sulfide enlarged to 84.7% from the original 81.9% of unexfoliated samples while the current density multiplied by 5 times. Moreover, a button-type asymmetric supercapacitor assembled using exfoliated cobalt sulfide as the positive electrode exhibits a maximum specific energy of 9.4 Wh∙kg⁻¹ at the specific power of 1520 W∙kg⁻¹. Full article

This paper presents a fast lock-in time clock frequency multiplier without using traditional clock generation circuits such as PLLs and DLLs. We propose a novel technique based on capacitive finite impulse response (FIR) filters to generate clock phases while reducing the input clock phase noise at the same time. A new delay line circuit is also proposed for improving power supply rejection. In addition, to improve the matching quality as well as the end-effects tolerance of the on-chip capacitors, a single-value series/parallel algorithm is proposed. Designed in a 0.18 $\mathsf{\mu }$m digital CMOS process, with a 20 MHz input clock frequency, the multiplier achieves a multiplication factor of 5 with a lock-in time of less than 4 clock cycles. The input clock jitter is reduced from 7ns RMS to 153 ps RMS after frequency multiplication. Full article

Due to having a number of advantages, Marx generators are still the most widely used devices for generating high-voltage pulses in many fields of science and technology. To ensure their proper operation, especially when the generation of many frequent, highly repetitive pulses is required, a highly efficient high-voltage power supply is needed. The paper describes a specially developed power supply (input voltage 48 V DC, output voltage up to 50 kV) based on the conventional Full Bridge topology with two high-frequency high-voltage transformers and a 6-stage voltage multiplier. In order to avoid many problems caused by low coupling between primary and secondary windings of the transformers and the large parasitic capacitances of the secondary windings, a special quasi-resonant zero-current switching transistor control algorithm with variable switching frequency (dependent on output load) was developed. In the described method, the energy is supplied to the transformer in short pulses, when a pair of diagonal transistors of the full-bridge converter were turned on. Then, the freewheeling state is maintained until all of the energy stored in the leakage inductance of the transformer has been transferred to the secondary side, which means that the current in the primary windings drops to zero. This approach reduces energy losses, electromagnetic disturbances and prevents current distortion in primary winding. Full article

In this paper, we provide a thorough analysis and enhancement techniques of the linearity between the input voltage and output current in charge storage field effect transistor (FET) cells for a vector–matrix multiplier array in neural networks. A planar floating gate FET cell revealed superior linearity, because of boosting the floating gate using a drain voltage through capacitive coupling. If the coupling capacitance is extended by up to half of the gate capacitance, the coefficient of determination for linear regression is easily greater than 99.5%. However, the linearity of the charge trap FET, which keeps electrons in the insulating gate dielectric, must be compensated by either boosting the drain voltage, using a non-linear input driver, or supplying a quadratic current through an auxiliary path in the cell. Drain voltage boosting is limitedly effective over a small input range, while the auxiliary current path shows a coefficient of determination greater than 99.5% over a 500 mV input range. If the cell area matters, the charge trap FET with a diode connected FET as an auxiliary current path revealed the best performance, with an effective number of bits of 5.67, in a 21.3 F² cell area. Full article

Electrical treeing is one of the main causes of crosslinked polyethylene (XLPE) cable failure. The current methods for locating electrical trees are mainly based on the partial discharge (PD) signal. However, PD signals are easily attenuated in the long cable and the PD test voltage may cause damage to the insulation. This work proposes an improved broadband impedance spectrum (BIS) method to locate electrical trees in XLPE cable. A mathematical model of a long cable containing local electrical tree degradation is established. The Gaussian signal is chosen as the simulated incident signal to reduce the spectral leakage. The location spectrum is obtained by multiplying the frequency domain function of the single-ended reflection coefficient and the Gaussian pulse. It has been found that the location spectrum of the local capacitance change can be characterized as a typical double-peak waveform and the spectrum of the local conductance change can be regarded as a typical single-peak waveform. Electrical tree experiments at different temperatures were carried out to initiate different types of electrical trees. A vector network analyzer (VNA) was used to test the high frequency capacitance characteristics in the treeing process. The location spectra of the 20 m long cable containing different types of electrical trees was calculated by the improved location algorithm. The results show that the location error of local electrical tree degradation is less than 3%. The capacitance of the sliced sample decreases with treeing time. The effect of the bush-pine tree on capacitance parameters is greater than that of the branch-pine tree. A typical double-peak is found in the bush-pine tree location spectrum and a single-peak is found in the branch-pine tree spectrum. Full article