Sign in to use this feature.

Years

Between: -

Subjects

remove_circle_outline
remove_circle_outline
remove_circle_outline
remove_circle_outline
remove_circle_outline
remove_circle_outline
remove_circle_outline
remove_circle_outline
remove_circle_outline

Journals

remove_circle_outline
remove_circle_outline
remove_circle_outline
remove_circle_outline
remove_circle_outline

Article Types

Countries / Regions

remove_circle_outline
remove_circle_outline
remove_circle_outline
remove_circle_outline
remove_circle_outline
remove_circle_outline

Search Results (2,254)

Search Parameters:
Keywords = DC high voltage

Order results
Result details
Results per page
Select all
Export citation of selected articles as:
24 pages, 2208 KB  
Article
Model-Based Control Assessment of PFC Systems with High-Conversion-Ratio DC–DC Converters
by Christopher J. Rodriguez-Cortes, Panfilo R. Martinez-Rodriguez, Diego Langarica-Cordoba, Gerardo Vazquez-Guzman, Juan A. Villanueva-Loredo and Jose M. Sosa
Technologies 2026, 14(6), 314; https://doi.org/10.3390/technologies14060314 (registering DOI) - 23 May 2026
Abstract
This paper presents a model-based control strategy for a power factor correction system that employs a high conversion-ratio DC–DC converter. The proposed system consists of two stages. In the first stage, a full-bridge diode rectifier is connected to the grid through a passive [...] Read more.
This paper presents a model-based control strategy for a power factor correction system that employs a high conversion-ratio DC–DC converter. The proposed system consists of two stages. In the first stage, a full-bridge diode rectifier is connected to the grid through a passive filter to improve the quality of the injected current. Two passive AC input filters, namely L and LCL configurations, are evaluated to analyze their impact on grid current quality and overall system performance. The second stage is a high-step-up DC–DC converter based on the switched-inductor technique, which provides a high voltage conversion ratio. A model-based approach is employed to derive the control design from the averaged system model. The resulting control structure consists of a current tracking loop and a voltage regulation loop. A proportional-resonant controller is used to ensure current tracking and achieve a near-unity power factor, while a proportional-integral controller regulates the output voltage. Experimental validation is carried out using a low-power laboratory-scale prototype to assess the effectiveness of the proposed approach. The results demonstrate adequate current tracking and satisfactory dynamic performance within the tested operating conditions. Full article
(This article belongs to the Special Issue Modeling, Design, and Control of Power Converters)
Show Figures

Figure 1

18 pages, 5986 KB  
Article
A Backside-Electrode-Free Lateral 4H-SiC JFET with Three-Terminal Dual-Gate Design for Stable DC Operation at 500 °C
by Yuting Tang, Qian Luo, Jiang Zhu, Hezhi Zhang, Yuchun Chang and Hongwei Liang
Micromachines 2026, 17(6), 642; https://doi.org/10.3390/mi17060642 - 22 May 2026
Abstract
To address the urgent need for electronics operable in extremely high-temperature environments, this paper presents a novel three-terminal, dual-gate, lateral 4H-SiC n-channel depletion-mode junction field effect transistor (JFET) without a backside electrode. Featuring a fully planar electrode layout, the device eliminates the back-gate [...] Read more.
To address the urgent need for electronics operable in extremely high-temperature environments, this paper presents a novel three-terminal, dual-gate, lateral 4H-SiC n-channel depletion-mode junction field effect transistor (JFET) without a backside electrode. Featuring a fully planar electrode layout, the device eliminates the back-gate effect and significantly improves integration compatibility. Experimental results demonstrate stable DC operation up to 500 °C, with an intrinsic gain of 9.79 at room temperature and 6.01 at 500 °C. Comparison with TCAD simulations confirms excellent agreement in the key physical trends of threshold voltage drift and mobility degradation, though quantitative discrepancies are observed and attributed to process-induced parasitic effects such as non-ideal ohmic contacts and interface states. Analysis shows that the new structure broadens the channel depletion layer by optimizing the depletion profile, thereby suppressing channel-length modulation and improving both output resistance and gate control. This work not only provides an effective device platform for high-temperature 4H-SiC analog integrated circuits (ICs) but also deepens the understanding of process-performance correlations, offering clear guidance for process-oriented device optimization. The proposed structure serves as a foundation for developing fully planar, high-temperature 4H-SiC analog ICs with promising potential in aerospace, automotive, and energy exploration systems. Full article
(This article belongs to the Section D1: Semiconductor Devices)
25 pages, 5566 KB  
Article
Optimal Wavelet Selection for DC Fault Detection in Multi-Terminal VSC-HVDC Grids: A Performance Comparison with HIL Validation
by Akash Sovis, Manilka Jayasooriya, Muhammad Naveed Iqbal, Kamran Daniel, Hadi Ashraf Raja, Rana Arslan Qadar and Noman Shabbir
Appl. Sci. 2026, 16(11), 5186; https://doi.org/10.3390/app16115186 - 22 May 2026
Abstract
Rapid and reliable DC fault detection is critical to the safe operation of Voltage Source Converter High Voltage Direct Current (VSC-HVDC) multi-terminal grids, where low system impedance causes fault currents to rise within milliseconds, demanding detection within 1 ms. Discrete Wavelet Transform (DWT) [...] Read more.
Rapid and reliable DC fault detection is critical to the safe operation of Voltage Source Converter High Voltage Direct Current (VSC-HVDC) multi-terminal grids, where low system impedance causes fault currents to rise within milliseconds, demanding detection within 1 ms. Discrete Wavelet Transform (DWT) has emerged as a leading signal processing technique for this purpose. However, no comprehensive performance study exists comparing the principal mother wavelets Daubechies (db), Symlets (sym), and Coiflets (coif) across the key operational variables of noise environment, cable length, and grid topology. This paper presents a systematic comparative evaluation of six wavelets (db4, db8, sym3, sym5, coif3, coif5) for DC fault detection in both three-terminal and four-terminal VSC-HVDC grids, assessing performance against four metrics: detection delay, accuracy, noise tolerance, and computational efficiency. Internal close-up and internal remote DC faults were simulated under no-noise conditions and white Gaussian noise levels of 30 dB, 20 dB, and 10 dB, with additional tests at cable lengths of 50 km and 400 km. Results demonstrate that db4 consistently achieves the lowest detection delay with high accuracy for four-terminal configurations under varying noise conditions, while sym3 proves most adaptable across both topologies for multiple cable lengths owing to its consistent detection delay. Real-time validation using an OPAL-RT hardware-in-the-loop (HIL) platform confirms the simulation findings, reinforcing the suitability of sym3 for multi-terminal grid deployment. These results provide actionable guidance for the selection of mother wavelets in DWT-based protection algorithms for modern VSC-HVDC systems. Full article
Show Figures

Figure 1

23 pages, 16803 KB  
Article
Design and Implementation of a High-Power-Density DC Power Supply Based on a Novel Integration of Z-Source and Isolated Full-Bridge DC–DC Converter Topologies
by Mehmet Akif Ozdemir, Ali Shan, Emrullah Aydin, Bulent Dag, Bunyamin Tamyurek and Mehmet Timur Aydemir
Energies 2026, 19(11), 2494; https://doi.org/10.3390/en19112494 - 22 May 2026
Abstract
High-voltage DC (HVDC) power supplies are essential for several advanced applications, including medical imaging, aerospace systems, and additive manufacturing. Traditional HVDC supplies often suffer from performance limitations due to high transformer turn ratios, which increased stray capacitance and degraded inverter performance. This paper [...] Read more.
High-voltage DC (HVDC) power supplies are essential for several advanced applications, including medical imaging, aerospace systems, and additive manufacturing. Traditional HVDC supplies often suffer from performance limitations due to high transformer turn ratios, which increased stray capacitance and degraded inverter performance. This paper proposes a novel two-stage HVDC power supply architecture that addresses these challenges by combining a Z-source converter with a full-bridge inverter, both enabled by high-performance Silicon Carbide (SiC) devices. The first stage boosts the rectified line voltage to 2 kV using a Z-source topology and inverts it at high frequency, while the second stage employs a high-voltage, high-frequency (HVHF) transformer and a voltage doubler to achieve a regulated 10 kV DC output. Simulation results using PLECS and experimental validation demonstrate the effectiveness of the proposed design in minimizing the reflected capacitance, enabling constant-frequency operation at the boundary of continuous conduction mode for improved efficiency, and providing high power density and compactness. This approach offers a promising solution for high-efficiency, high-voltage applications. Full article
16 pages, 11013 KB  
Article
Atmospheric-Pressure Plasma Polymerization of Fluorosilane Coatings for Suppressing DC Surface Flashover on Polystyrene
by Tianran Zhang, Zexi Gao, Penghao Zhang, Chengguo Yao and Shoulong Dong
Coatings 2026, 16(5), 627; https://doi.org/10.3390/coatings16050627 - 21 May 2026
Viewed by 93
Abstract
Direct current (DC) surface flashover on polystyrene (PS) remains a critical bottleneck that impedes its reliable application in high-voltage insulation apparatus. To circumvent the protracted processing durations and stringent film-forming conditions inherent in conventional surface modification techniques, this study proposes a novel “liquid-film-assisted [...] Read more.
Direct current (DC) surface flashover on polystyrene (PS) remains a critical bottleneck that impedes its reliable application in high-voltage insulation apparatus. To circumvent the protracted processing durations and stringent film-forming conditions inherent in conventional surface modification techniques, this study proposes a novel “liquid-film-assisted in situ rapid plasma curing” strategy. By harnessing atmospheric-pressure dielectric barrier discharge (DBD) technology within an argon ambient, the rapid (<6 min) and efficient deposition of a fluorosilane (FAS-13) functional coating onto the substrate was achieved. Microscopic characterizations coupled with isothermal surface potential decay (SPD) measurements reveal that this coating substantially mitigates the detrapping and surface migration of charge carriers. Macroscopic DC flashover testing corroborates that, under the optimal modification ratio, the surface breakdown voltage of PS is elevated to 14.04 kV, yielding an insulation gain of 26.94%. To elucidate the underlying physical mechanisms, density functional theory (DFT) calculations were conducted, revealing that the energy band misalignment between the wide-bandgap fluorinated layer and the substrate facilitates the construction of a high-density deep trap network (with a depth of ~0.8 eV) at the coating–substrate interface. By robustly anchoring primary electrons and inducing the formation of a homopolar space charge shielding layer, these deep traps physically arrest the evolution of the secondary electron emission avalanche (SEEA). Consequently, this work not only establishes a viable engineering framework for the rapid, large-scale surface reinforcement of DC insulation equipment but also provides profound quantum chemical insights into interfacial trap regulation within all-organic dielectrics. Full article
(This article belongs to the Section Functional Polymer Coatings and Films)
Show Figures

Figure 1

37 pages, 4241 KB  
Article
Boosting Energy Quality in Hybrid Power Systems Through Fractional-Order Adaptive Fuzzy Logic–Based Direct Power Control of SAPF
by Khaoula Nermine Khallouf, Habib Benbouhenni and Nicu Bizon
Algorithms 2026, 19(5), 418; https://doi.org/10.3390/a19050418 - 21 May 2026
Viewed by 186
Abstract
The intermittent nature of renewable power sources, nonlinear load effects, and harmonic distortions induced by power electronic converters complicate the maintenance of high energy quality in microgrid-connected hybrid renewable power systems. In a range of operating conditions, conventional strategies-including fractional-order proportional-integral (FOPI) controllers-frequently [...] Read more.
The intermittent nature of renewable power sources, nonlinear load effects, and harmonic distortions induced by power electronic converters complicate the maintenance of high energy quality in microgrid-connected hybrid renewable power systems. In a range of operating conditions, conventional strategies-including fractional-order proportional-integral (FOPI) controllers-frequently prove ineffective in delivering both robust harmonic mitigation and expeditious dynamic response. To surmount these constraints, the present paper puts forth an intelligent control solution that is predicated on a fractional-order fuzzy logic (FOFL). The FOFL is integrated into a multi-converter HRPS, comprising a photovoltaic generator, a lithium-ion battery power storage system, and a wind turbine equipped with a permanent magnet synchronous generator. A multifunctional voltage source inverter has been developed to control these parts, which are interfaced via a common DC bus. Through the implementation of MATLAB 2021 simulation studies, the efficacy of the suggested algorithm is verified and evaluated in comparison to the FOPI. The findings indicate that the FOFL enhances system efficacy by minimizing harmonic distortion, improving energy quality, and achieving a faster dynamic response under various circumstances. In the context of grid-connected microgrid environments, the FOFL has been demonstrated to offer superior overall energy management, robustness, and adaptability when compared to other evaluated strategies. Full article
Show Figures

Figure 1

15 pages, 8067 KB  
Article
Large-Signal Equivalent Circuit Model for HighPower Laser Diode Mini-Array
by Lei Ling, Tao Duan, Shunhua Wu, Jiachen Liu, Junyue Zhang, Weizhou Huang, Qingkai Meng, Lang Chen, Jiachen Zhang, Te Li and Zhenfu Wang
Electronics 2026, 15(10), 2215; https://doi.org/10.3390/electronics15102215 - 21 May 2026
Viewed by 125
Abstract
High-power laser diodes are extensively utilized in advanced optoelectronic systems. These devices typically operate under high-current injection conditions, under which intrinsic parasitic parameters become non-negligible and exert a substantial influence on their electro-optical response characteristics. Furthermore, when multiple single emitters are monolithically integrated [...] Read more.
High-power laser diodes are extensively utilized in advanced optoelectronic systems. These devices typically operate under high-current injection conditions, under which intrinsic parasitic parameters become non-negligible and exert a substantial influence on their electro-optical response characteristics. Furthermore, when multiple single emitters are monolithically integrated into a linear array along the epitaxial-layer direction on a single substrate, additional parasitic elements are inevitably introduced. These parameters are critical for characterizing the output performance of high-power laser diodes. This paper presents the implementation of an equivalent circuit model for large-signal laser-diode operation within the Advanced Design System (ADS) computer-aided environment. The proposed model enables accurate simulation of the device’s operating-voltage waveform and optical-output-power response under both DC steady-state and pulsed-transient driving conditions, thereby achieving a coupled representation of electrical behavior and optical emission. Sensitivity analysis of various parasitic elements is performed to systematically evaluate their influence on output characteristics and device reliability. The results provide theoretical guidance for structural optimization and packaging design, offering new insights into future modeling and reliability assessment of high-power laser diodes. Full article
(This article belongs to the Section Optoelectronics)
Show Figures

Figure 1

9 pages, 2366 KB  
Proceeding Paper
Liquid-Based Semiconductor Rheostat for DC Arc Fault Suppression
by Kagiso Ndlhovu, Temosho Mathabatha and James Braid
Eng. Proc. 2026, 140(1), 26; https://doi.org/10.3390/engproc2026140026 - 20 May 2026
Viewed by 70
Abstract
Validation testing of a liquid-based rheostat confirmed its efficacy in mitigating DC arc faults in photovoltaic systems by exceeding critical resistance and voltage–current thresholds. Experimental characterization of electrode immersion depth, separation, and electrolyte concentration identified zinc-galvanized steel to copper in NaHCO3 as [...] Read more.
Validation testing of a liquid-based rheostat confirmed its efficacy in mitigating DC arc faults in photovoltaic systems by exceeding critical resistance and voltage–current thresholds. Experimental characterization of electrode immersion depth, separation, and electrolyte concentration identified zinc-galvanized steel to copper in NaHCO3 as the optimal configuration, achieving a dynamic range factor of 39.10. Further analysis prioritized high minimum resistance (RMIN) for arc extinction, favouring stable electrode pairs like copper to brass with a 10 g solute concentration. A unified piecewise resistance model validated arc suppression through a load line analysis, demonstrating non-intersection with the Mayr extinction boundary. These findings support scaling the device to a 5 kW, 250 VDC rating for electric geysers, utilizing 200 mm × 50 mm electrodes and increased electrolyte volume to ensure operational stability. Full article
Show Figures

Figure 1

19 pages, 6403 KB  
Article
Research on a Dead-Time-Compensated DC-Link Current Estimation Algorithm for PMSM
by Xiaoyu Chen, Jie Zhang and Jie Hong
Appl. Sci. 2026, 16(10), 5087; https://doi.org/10.3390/app16105087 - 20 May 2026
Viewed by 141
Abstract
The DC-link current in PMSM drive systems is a critical variable for indicating DC-side power level and enabling efficiency optimization. However, existing sensorless current estimation methods are significantly affected by dead-time effects, resulting in limited estimation accuracy. To address this issue, a quantitative [...] Read more.
The DC-link current in PMSM drive systems is a critical variable for indicating DC-side power level and enabling efficiency optimization. However, existing sensorless current estimation methods are significantly affected by dead-time effects, resulting in limited estimation accuracy. To address this issue, a quantitative analysis of the impact of dead time on three-phase current reconstruction is conducted, and a mathematical model describing the relationship between estimation error and key influencing factors is established. Based on this, a unified framework integrating dead-time voltage compensation with DC-link current estimation is proposed. By real-time identification of stator current polarity, the dead-time-induced voltage error is accurately calculated, and a feedforward voltage compensation is implemented in the αβ stationary reference frame to effectively mitigate voltage deviation and waveform distortion. The reference voltage is subsequently incorporated into the DC-link current reconstruction process, enabling high-accuracy current estimation. The effectiveness of the proposed method is validated through both simulation and prototype experiments, demonstrating that the algorithm can accurately estimate the DC-link current of PMSM drive systems under various operating conditions, with an estimation error of approximately ±2%. Full article
(This article belongs to the Section Electrical, Electronics and Communications Engineering)
Show Figures

Figure 1

16 pages, 4094 KB  
Proceeding Paper
Integrated Linear Transformer-Based Diode Bridge Rectifier for Improved Power Quality in Electric Vehicle Charging Stations
by Sugunakar Mamidala and Yellapragada Venkata Pavan Kumar
Eng. Proc. 2026, 124(1), 117; https://doi.org/10.3390/engproc2026124117 - 20 May 2026
Viewed by 102
Abstract
As electric vehicle (EV) charging stations are increasingly common, the front-end rectifier stage of the charging infrastructure tends to degrade grid power quality by introducing high input current harmonics, poor power factor, and voltage distortion. Despite their simplicity and low cost, the conventional [...] Read more.
As electric vehicle (EV) charging stations are increasingly common, the front-end rectifier stage of the charging infrastructure tends to degrade grid power quality by introducing high input current harmonics, poor power factor, and voltage distortion. Despite their simplicity and low cost, the conventional diode bridge rectifiers (DBR) usually have a total harmonic distortion (THD) of over 25% and have power factors of below 0.80. These issues have been handled with the active power factor correction (PFC) techniques, which increase system complexity, the cost of the system, and the increased sophistication of the control algorithm. This article proposes an integrated linear transformer (LT) based diode-bridge rectifier (DBR) that is intended to enhance the quality of power of the EV charging stations without invoking active control mechanisms. The suggested arrangement combines a linear transformer, a passive filter network, and a diode bridge to obtain multipurpose voltage step-down (galvanic isolation) and harmonic mitigation in a single structure. The system provides improved voltage regulation, flux balancing, and filter resonance, and reduced current distortion. The proposed system is validated with MATLAB/Simulink R2021a, and the results show that the proposed system has a THD of 4.32% that complies with the IEEE 519 harmonic standards, and also the input power factor is increased to 0.98. It also decreases DC output voltage ripple by 4.8% to 0.7% and improves its voltage regulation by 9.1%, as well as increases its system efficiency to 96.3%. The findings make integrated LT + DBR an affordable, robust, and less massive implementation of the next-generation EV charging infrastructure, specially designed to meet the needs of smart grid deployment and integration in Tier-2 and Tier-3 cities, where simplicity and power quality compliance remain a priority. Full article
(This article belongs to the Proceedings of The 6th International Electronic Conference on Applied Sciences)
Show Figures

Figure 1

11 pages, 1018 KB  
Proceeding Paper
The Effect of Pitch-Bearing Fatigue on Wind Turbine Electrical Traces
by Tumelo Molato, Goodness Ayanda Zamile Dlamini and Pitshou Ntambu Bokoro
Eng. Proc. 2026, 140(1), 25; https://doi.org/10.3390/engproc2026140025 - 18 May 2026
Viewed by 89
Abstract
This paper investigates whether event-level pitch-bearing fatigue damage can be estimated directly from turbine measurements, and whether these mechanical damage metrics leave measurable fingerprints in the generator DC-link voltage and current. To achieve this, a case study was performed using SCADA and structural [...] Read more.
This paper investigates whether event-level pitch-bearing fatigue damage can be estimated directly from turbine measurements, and whether these mechanical damage metrics leave measurable fingerprints in the generator DC-link voltage and current. To achieve this, a case study was performed using SCADA and structural load data from the 45 kW Chalmers (Björkö) research turbine. This data was segmented into 223 park-run-park pitch events. For each event, blade-root flapwise and edgewise bending moments were converted into radial and axial loads at the pitch bearing; an equivalent dynamic bearing load Peqt was reconstructed using SKF and DG03 formulations; and rainflow counting with an S–N curve and Palmgren–Miner’s rule was used to compute event-level damage indices compatible with the International Standard Organization basic rating life concepts. In parallel, DC-link voltage and current were summarized into time-domain features, combined with operating-condition descriptors, and clustered using PCA-based k-means. The resulting clusters captured distinct electrical regimes that, across several event batches, corresponded to different levels of accumulated fatigue damage: regimes with sustained high DC-link voltage and longer duration tended to exhibit higher mean damage indices than lower, steadier DC regimes, indicating an electromechanical link. The results show that physics-based lifetime estimation and unsupervised analysis of existing electrical traces can be combined into a hybrid workflow for pitch-bearing condition assessment without additional sensors. Full article
Show Figures

Figure 1

18 pages, 6617 KB  
Article
Modeling of SiC MOSFETs and Analysis of Turn-Off Overvoltage Mechanism in Low-Voltage DC Solid-State Circuit Breaker Applications
by Qingguang Xia, Jin Wu, Xueyan Zhang, Nan Wu, Zheng Fu and Qiyong Zhou
Electronics 2026, 15(10), 2175; https://doi.org/10.3390/electronics15102175 - 18 May 2026
Viewed by 125
Abstract
To address the turn-off overvoltage challenge arising from the rapid interruption of Low Voltage DC Solid-State Circuit Breakers (SSCBs), this paper proposes a high-precision behavioral modeling method for domestic SiC MOSFETs. The model is constructed based on the physical structure of the device, [...] Read more.
To address the turn-off overvoltage challenge arising from the rapid interruption of Low Voltage DC Solid-State Circuit Breakers (SSCBs), this paper proposes a high-precision behavioral modeling method for domestic SiC MOSFETs. The model is constructed based on the physical structure of the device, integrating a modified EKV-based static current model and a voltage-dependent nonlinear parasitic capacitance model described by piecewise functions. Model parameters are efficiently extracted from datasheets and measurement data using a composite optimization strategy combining the Genetic Algorithm and the Levenberg–Marquardt algorithm. The model is implemented in LTspice, and its accuracy in both static and dynamic characteristics is validated by comparing the simulation waveforms with experimental results. Based on the validated model, the turn-off process is subdivided into four distinct stages, with an equivalent circuit established for each. A systematic analysis reveals the intrinsic physical mechanism of the voltage spike and oscillation, which results from interaction among the drive circuit parameters, system parameters, and the nonlinear capacitances of the device. The research outcomes provide effective theoretical guidance and a design tool for simulation modeling, turn-off stress assessment, and snubber circuit optimization for SSCBs utilizing SiC MOSFETs. Full article
Show Figures

Figure 1

21 pages, 3999 KB  
Article
Model-Free Predictive Synthesis Performance Optimization of DAB Converters Based on an Ultra-Local Model
by Luan Wang, Guoqiang Qiu, Bowen Chi, Dejun Liu and Yanming Cheng
Energies 2026, 19(10), 2421; https://doi.org/10.3390/en19102421 - 18 May 2026
Viewed by 105
Abstract
The dual-active-bridge (DAB) converter is the core component of the DC micro-grid system; it has the advantages of topological structure symmetry, high efficiency, and high-power density. Model predictive control (MPC) is often employed to improve the dynamic response characteristics of the system, but [...] Read more.
The dual-active-bridge (DAB) converter is the core component of the DC micro-grid system; it has the advantages of topological structure symmetry, high efficiency, and high-power density. Model predictive control (MPC) is often employed to improve the dynamic response characteristics of the system, but its strong parameter dependence is a key factor limiting the development of MPC. Therefore, a model-free predictive control (MFPC) method combining an ultra-local model with model predictive control is proposed to solve the problem of strong dependence of traditional MPC on system model parameters. Firstly, establish the ultra-local mathematical model of the DAB converter. The system’s lumped disturbances are identified using the residual prediction method and substituted into the discrete model of the system at the next time step to achieve model-free prediction. Secondly, a minimum back-flow power constraint is added to the cost function to improve the steady-state performance of the converter. Thirdly, in the extended phase shift modulation, the Lagrange multiplier method (LMM) is proposed to reduce the current stress, ultimately achieving the collaborative optimization of the comprehensive performance of the DAB. Finally, a simulation model is built using MATLAB/Simulink, and compared with traditional control methods, the voltage ripple has been reduced by 51.3%, 89.1%, and 85.1%, respectively; the current stress significantly decreases both when the output voltage reference value changes and when the load resistance changes abruptly, and both can basically achieve zero back-flow power operation. The validity and superiority of the proposed strategy have been verified. Full article
(This article belongs to the Special Issue Advances in Power Converters and Inverters)
Show Figures

Figure 1

10 pages, 5124 KB  
Proceeding Paper
Predictive Maintenance of High-Voltage Railway Equipment Using Machine Learning: A Case Study on Pantograph and Auxiliary Converter Units in a 3 kV DC Rail System
by Mavhungu Mathalise, Elisha Markus and Malusi Sibiya
Eng. Proc. 2026, 140(1), 23; https://doi.org/10.3390/engproc2026140023 - 18 May 2026
Viewed by 108
Abstract
In 3 kV DC systems, the pantograph–catenary interface and auxiliary converter unit (ACU) are among the critical high-voltage subsystems, where electrical transients and thermal overload conditions frequently lead to service disruptions. This paper presents a case study on the application of machine-learning-based predictive [...] Read more.
In 3 kV DC systems, the pantograph–catenary interface and auxiliary converter unit (ACU) are among the critical high-voltage subsystems, where electrical transients and thermal overload conditions frequently lead to service disruptions. This paper presents a case study on the application of machine-learning-based predictive maintenance to a 3 kV DC electric train, with a specific focus on the pantograph and ACU. A 2-year period of operational data collected from a passenger rail fleet was analysed using a hybrid data sampling strategy to capture both operational conditions and events associated with failures. Logistic Regression (LR), and Random Forest (RF) were trained and evaluated using standard performance metrics. The RF model achieved superior predictive performance, with an accuracy of approximately 93%, a precision of 0.91, a recall of 0.88, and an F1-score of 0.89, outperforming the baseline across all metrics. The analyses demonstrated that anomalies in electrical arcing, line voltage, and ACU current and temperature frequently preceded recorded fault events, confirming that failures arise from subsystems interactions and that it is critical for such parameters to be monitored. The results demonstrate the technical feasibility and practical value of integrating machine learning into EMU maintenance practice, enabling earlier detection of degradation, more targeted interventions, and a transition towards condition-based maintenance. Full article
Show Figures

Figure 1

34 pages, 2651 KB  
Article
Observer-Assisted Stability-Margin-Driven Prescribed-Time Distributed Control for Islanded DC Microgrids: Enhancing System Stability Under Large-Signal CPL Disturbances
by Haoran Zhang, Chuanyu Jiang and Xinyu Xu
Mathematics 2026, 14(10), 1682; https://doi.org/10.3390/math14101682 - 14 May 2026
Viewed by 95
Abstract
Although secondary control of direct current (DC) microgrids has been widely studied, traditional static current sharing may still cause severe voltage sag under large-signal constant power load (CPL) steps, and many distributed schemes rely on global topology information while showing limited transient disturbance [...] Read more.
Although secondary control of direct current (DC) microgrids has been widely studied, traditional static current sharing may still cause severe voltage sag under large-signal constant power load (CPL) steps, and many distributed schemes rely on global topology information while showing limited transient disturbance rejection. To address these issues, this paper proposes an observer-assisted, stability-margin-driven prescribed-time distributed secondary control strategy for islanded DC microgrids. A dynamic CPL risk evaluation function updates current-sharing ratios according to converter operating margins, while a distributed prescribed-time observer estimates disturbance envelopes and alleviates high-frequency chattering. Local adaptive gains remove the explicit dependence of controller tuning on global Laplacian eigenvalue information. MATLAB R2024a-based numerical studies show that, under a 6000 W CPL stress scenario, the proposed method limits the maximum voltage drop to 3.37 V, compared with 24.60 V for the conventional virtual current derivative (VCD) method. Under heterogeneous line impedances and a non-ideal digital benchmark, the proposed method yields a normalized current-sharing error of 0.72%, whereas the VCD method exhibits milder voltage transients. These results support the algorithmic effectiveness and numerical robustness of the proposed strategy within the adopted validation environment. Full article
Show Figures

Figure 1

Back to TopTop