Analog doi: 10.3390/analog1010005

Authors: Manlius C. T. S. Rocha Carlos A. B. Reyna Flávio Buiochi

This article presents a low-cost, high-voltage excitation circuit (EC) for capacitive ultra-sonic transducers (CUTs) based on a dual-path architecture. The proposed design comprises two independent AC excitation channels (AC-branch) that share a regulated DC-bias voltage (DC-branch). The circuit was developed to satisfy a fundamental operational requirement of CUTs: simultaneous application of a static bias voltage and a time-varying drive voltage. Because the electrostatic force depends nonlinearly on the applied voltage, efficient first-harmonic actuation requires the superposition of DC and AC voltage components. To reach this objective, the circuit and the transducer must be treated as a coupled electrical, electrostatic, mechanical, and acoustic system. In the proposed implementation, the DC-branch uses a TL494-PWM controller, a TIP50 switching transistor, a step-up transformer, and a rectifier-filter stage to generate the high-voltage bias of up to 200 VDC. Each AC-channel employs an LM3886TF amplifier followed by a 1:15 step-up transformer, enabling the generation of excitation signals of up 180 Vpeak. A key feature of the proposed architecture is the electrical independence of the two AC-channels, which allows for distinct excitation frequencies with minimal mutual interference. Experimental validation, performed with and without ultrasonic loads, demonstrates the relation between excitation conditions and the acoustic performance of the CUTs.

Analog doi: 10.3390/analog1010004

Authors: Erick Iván Barros de la Cruz María Teresa Sanz-Pascual

This paper presents a highly linear second-order, tunable bandpass filter (BPF) based on low-Gm operational transconductance amplifiers (OTAs) to be used in a single-frequency bioimpedance analysis (SFBIA) system. The center frequency of the proposed BPF can be set at the target center frequency fc = 1 kHz through a tuning current IC, thus compensating for process variations and temperature changes after fabrication. A low quality factor is established to let the input signal pass through without significant phase shift or gain fluctuation, while reducing the out-of-band noise contribution to the readout circuit. The proposed BPF was implemented in a 0.18 μm CMOS process and consumes 2.6 μW from a 1.8 V supply. The Gm reduction technique enables precise control of the OTA’s transconductance, and therefore of the center frequency of the BPF. For IC ranging from 28 nA to 138 nA, the measured fc varies from 690 Hz to 3 kHz, with a constant Q factor of approximately 0.4. The proposed BPF can handle input signals as high as 132 mVpp with a maximum 1% total harmonic distortion.

Analog doi: 10.3390/analog1010003

Authors: Jiayue Xie Haohua Que Mingkai Liu Haojia Gao Qian Zhang Hongyi Xu Fei Qiao

Low-power CMOS image sensors increasingly rely on approximate analog front-end designs, including reduced ADC precision, relaxed voltage swing, and noise-tolerant readout circuits, to reduce energy consumption in always-on edge vision systems. However, the acceptable degradation boundary of such analog front-ends remains unclear when sensor outputs are consumed by downstream spatial perception workloads rather than conventional image-quality metrics. This paper presents a task-aware system-level evaluation framework for approximate CMOS image-sensor analog front-ends. We parameterize key circuit-level non-idealities, including ADC bit-depth reduction, temporal read noise, gain and offset variation, fixed-pattern noise, and dynamic-range clipping, and we evaluate how these impairments propagate through semantic, geometric, mapping, and spatial decision workloads. Across 10,500 end-to-end evaluations and 1996 geometric mapping trials, we identify a strong non-linear error cascade: semantic free-space extraction remains tolerant to aggressive quantization, whereas monocular depth and visual odometry impose much stricter analog front-end requirements. The results show that read noise and offset errors are the dominant failure sources for geometric perception, while controlled voltage swing clipping at 0.8 V can reduce front-end energy without degrading, and in some cases slightly improving, downstream reliability by suppressing high-intensity outliers. The analysis provides quantitative design boundaries for low-power CMOS image-sensor front-ends, including task-specific ADC precision, read-noise tolerance, voltage swing, PGA bypass, and offset calibration requirements.

Analog doi: 10.3390/analog1010002

Authors: Euzeli C. dos Santos Josinaldo L. Araujo Isaac S. de Freitas

Analog electronics, i.e., circuits that process continuously varying signals, have quietly powered the backbone of agricultural automation long before the advent of modern digital technologies. Yet, the accelerating focus on digitalization, IoT, and AI in precision agriculture has largely overshadowed the enduring, indispensable role of analog components in sensing, signal conditioning, power conversion, and actuation. This paper provides a comprehensive state-of-the-art review of analog electronics applied to agricultural systems. It revisits historical milestones, from early electroculture and soil-moisture instrumentation to modern analog front-ends for biosensing and analog electronics for alternatives source of energy and weed control. Emphasis is placed on how analog electronics enable real-time, low-latency, and energy-efficient interfacing with the physical world, a necessity in farming contexts where ruggedness, simplicity, and autonomy prevail. By mapping the trajectory from electroculture experiments of the 18th-century to 21st-century transimpedance amplifiers, analog sensor nodes, and low-noise instrumentation amplifiers in agri-robots, this work argues that the true technological revolution in agriculture is not purely digital but lies in the symbiosis of analog physics and biological processes.

Analog doi: 10.3390/analog1010001

Authors: Andres Ayes Eby G. Friedman

Reliable timing is a crucial issue in all synchronous systems. Delay locked loops are capable of dynamically synchronizing clock signals; the increasing speed of deeply scaled technologies however leads to long and complex delay lines. In this paper, a sawtooth-based delay locked loop is proposed to address the increasing difficulty of delay generation in high speed systems. The proposed architecture replaces a conventional delay line with a sawtooth waveform-based mechanism for delay generation, reducing the need for numerous delay elements. The timing offset is mapped to a voltage level on the sawtooth waveform, where the required delay is the time to cross this voltage level. The architecture, evaluated using a 7 nm device model, achieves a locking speed as low as four cycles for a 1 GHz clock signal. The DLL achieves a full period locking range, lowers the clock skew to 16 ps at room temperature, and exhibits 65 ps clock skew variations over extreme temperature corners.