J. Low Power Electron. Appl.2015, 5(3), 183-215; doi:10.3390/jlpea5030183 - published 11 September 2015 Show/Hide Abstract
Abstract: As digital circuit design continues to evolve due to progress of semiconductor processes well into the sub 100 nm range, clocked architectures face limitations in a number of cases where clockless asynchronous architectures generate less noise and produce less electro-magnetic interference (EMI). This paper develops the Delay-Insensitive Ternary Logic (DITL) asynchronous design paradigm that combines design aspects of similar dual-rail asynchronous paradigms and Boolean logic to create a single wire per bit, three voltage signaling and logic scheme. DITL is compared with other delay insensitive paradigms, such as Pre-Charge Half-Buffers (PCHB) and NULL Convention Logic (NCL) on which it is based. An application of DITL is discussed in designing secure digital circuits resistant to side channel attacks based on measurement of timing, power, and EMI signatures. A Secure DITL Adder circuit is designed at the transistor level, and several variance parameters are measured to validate the efficiency of DITL in resisting side channel attacks. The DITL design methodology is then applied to design a secure 8051 ALU.
J. Low Power Electron. Appl.2015, 5(3), 165-182; doi:10.3390/jlpea5030165 - published 11 August 2015 Show/Hide Abstract
Abstract: This paper presents a cross-layer framework in order to design and optimize energy-efficient cache memories made of deeply-scaled FinFET devices. The proposed design framework spans device, circuit and architecture levels and considers both super- and near-threshold modes of operation. Initially, at the device-level, seven FinFET devices on a 7-nm process technology are designed in which only one geometry-related parameter (e.g., fin width, gate length, gate underlap) is changed per device. Next, at the circuit-level, standard 6T and 8T SRAM cells made of these 7-nm FinFET devices are characterized and compared in terms of static noise margin, access latency, leakage power consumption, etc. Finally, cache memories with all different combinations of devices and SRAM cells are evaluated at the architecture-level using a modified version of the CACTI tool with FinFET support and other considerations for deeply-scaled technologies. Using this design framework, it is observed that L1 cache memory made of longer channel FinFET devices operating at the near-threshold regime achieves the minimum energy operation point.
J. Low Power Electron. Appl.2015, 5(3), 151-164; doi:10.3390/jlpea5030151 - published 25 June 2015 Show/Hide Abstract
Abstract: This paper proposes a review of several circuits for communication and wireless sensing applications implemented on cellulose-based materials. These circuits have been developed during the last years exploiting the adhesive copper laminate method. Such a technique relies on a copper adhesive tape that is shaped by a photo-lithographic process and then transferred to the hosting substrate (i.e., paper) by means of a sacrificial layer. The presented circuits span from UHF oscillators to a mixer working at 24 GHz and constitute an almost complete set of building blocks that can be applied to a huge variety communication apparatuses. Each circuit is validated experimentally showing performance comparable with the state-of-the-art. This paper demonstrates that circuits on cellulose are capable of operating at record frequencies and that ultra- low cost, green i.e., recyclable and biodegradable) materials can be a viable solution to realize high frequency hardware for the upcoming Internet of Things (IoT) era.
J. Low Power Electron. Appl.2015, 5(2), 130-150; doi:10.3390/jlpea5020130 - published 23 June 2015 Show/Hide Abstract
Abstract: The pursuit of continuous scaling of electronic devices in the semiconductor industry has led to two unintended but significant outcomes: a rapid increase in susceptibility to radiation induced errors, and an overall rise in power consumption. Operating under low voltage to reduce power only aggravates radiation related reliability issues. The proposed “SEU Hardening Incorporating Extreme Low Power Bitcell Design” (SHIELD) addresses these two major concerns simultaneously. It is based on the concept of gating the conventional cross-coupled inverters while introducing a novel “cut-off” network. This creates redundant storage nodes and eliminates the internal feedback loop during radiation particle impact. The SHIELD bitcell tolerates upsets with charge deposits over 1 pC. Simulations confirm its advantages in terms of leakage power, with more than twofold lower leakage currents than previous solutions when operated at a 700mV supply voltage in a 65 nm process. To validate the bitcell’s robustness, several test cases and special concerns, including multiple node upsets (MNU) and half-select, are examined.
J. Low Power Electron. Appl.2015, 5(2), 116-129; doi:10.3390/jlpea5020116 - published 25 May 2015 Show/Hide Abstract
Abstract: In this study, we demonstrate near-0.1 V minimum operating voltage of a low-variability Silicon on Thin Buried Oxide (SOTB) process for one million logic gates on silicon. Low process variability is required to obtain higher energy efficiency during ultra-low-voltage operation with steeper subthreshold slope transistors. In this study, we verify the decrease in operating voltage of logic circuits via a variability-suppressed SOTB process. In our measurement results with test chips fabricated in 65-nm SOTB and bulk processes, the operating voltage at which the first failure is observed was lowered from 0.2 to 0.125 V by introducing a low-variability SOTB process. Even at 0.115 V, over 40% yield can be expected as per our measurement results on SOTB test chips.
J. Low Power Electron. Appl.2015, 5(2), 101-115; doi:10.3390/jlpea5020101 - published 21 May 2015 Show/Hide Abstract
Abstract: In this paper, we analyze the variability of III-V homojunction tunnel FET (TFET) and FinFET devices and 32-bit carry-lookahead adder (CLA) circuit operating in near-threshold region. The impacts of the most severe intrinsic device variations including work function variation (WFV) and fin line-edge roughness (fin LER) on TFET and FinFET device Ion, Ioff, Cg, 32-bit CLA delay and power-delay product (PDP) are investigated and compared using 3D atomistic TCAD mixed-mode Monte-Carlo simulations and HSPICE simulations with look-up table based Verilog-A models calibrated with TCAD simulation results. The results indicate that WFV and fin LER have different impacts on device Ion and Ioff. Besides, at low operating voltage (<0.3 V), the CLA circuit delay and power-delay product (PDP) of TFET are significantly better than FinFET due to its better Ion and Cg,ave and their smaller variability. However, the leakage power of TFET CLA is larger than FinFET CLA due to the worse Ioff variability of TFET devices.