J. Low Power Electron. Appl.2015, 5(2), 57-68; doi:10.3390/jlpea5020057 - published 17 April 2015 Show/Hide Abstract
Abstract: To minimize energy consumption of a digital circuit, logic can be operated at sub- or near-threshold voltage. Operation at this region is challenging due to device and environment variations, and resulting performance may not be adequate to all applications. This article presents two variants of a 32-bit RISC CPU targeted for near-threshold voltage. Both CPUs are placed on the same die and manufactured in 28 nm CMOS process. They employ timing-error prevention with clock stretching to enable operation with minimal safety margins while maximizing performance and energy efficiency at a given operating point. Measurements show minimum energy of 3.15 pJ/cyc at 400 mV, which corresponds to 39% energy saving compared to operation based on static signoff timing.
J. Low Power Electron. Appl.2015, 5(2), 38-56; doi:10.3390/jlpea5020038 - published 27 March 2015 Show/Hide Abstract
Abstract: Modern systems-on-chip (SoCs) today contain hundreds of cores, and this number is predicted to reach the thousands by the year 2020. As the number of communicating elements increases, there is a need for an efficient, scalable and reliable communication infrastructure. As technology geometries shrink to the deep submicron regime, however, the communication delay and power consumption of global interconnections become the major bottleneck. The network-on-chip (NoC) design paradigm, based on a modular packet-switched mechanism, can address many of the on-chip communication issues, such as the performance limitations of long interconnects and integration of large number of cores on a chip. Recently, new communication technologies based on the NoC concept have emerged with the aim of improving the scalability limitations of conventional NoC-based architectures. Among them, wireless NoCs (WiNoCs) use the radio medium for reducing the performance and energy penalties of long-range and multi-hop communications. As the radio medium can be accessed by a single transmitter at a time, a radio access control mechanism (RACM) is needed. In this paper, we present a novel RACM, which allows one to improve both the performance and energy figures of the WiNoC. Experiments, carried out on both synthetic and real traffic scenarios, have shown the effectiveness of the proposed RACM. On average, a 30% reduction in communication delay and a 25% energy savings have been observed when the proposed RACM is applied to a known WiNoC architecture.
J. Low Power Electron. Appl.2015, 5(1), 3-37; doi:10.3390/jlpea5010003 - published 13 March 2015 Show/Hide Abstract
Abstract: This paper considers the problem of how to efficiently measure a large and complex information field with optimally few observations. Specifically, we investigate how to stochastically estimate modular criticality values in a large-scale digital circuit with a very limited number of measurements in order to minimize the total measurement efforts and time. We prove that, through sparsity-promoting transform domain regularization and by strategically integrating compressive sensing with Bayesian learning, more than 98% of the overall measurement accuracy can be achieved with fewer than 10% of measurements as required in a conventional approach that uses exhaustive measurements. Furthermore, we illustrate that the obtained criticality results can be utilized to selectively fortify large-scale digital circuits for operation with narrow voltage headrooms and in the presence of soft-errors rising at near threshold voltage levels, without excessive hardware overheads. Our numerical simulation results have shown that, by optimally allocating only 10% circuit redundancy, for some large-scale benchmark circuits, we can achieve more than a three-times reduction in its overall error probability, whereas if randomly distributing such 10% hardware resource, less than 2% improvements in the target circuit’s overall robustness will be observed. Finally, we conjecture that our proposed approach can be readily applied to estimate other essential properties of digital circuits that are critical to designing and analyzing them, such as the observability measure in reliability analysis and the path delay estimation in stochastic timing analysis. The only key requirement of our proposed methodology is that these global information fields exhibit a certain degree of smoothness, which is universally true for almost any physical phenomenon.
J. Low Power Electron. Appl.2014, 4(4), 304-316; doi:10.3390/jlpea4040304 - published 9 December 2014 Show/Hide Abstract
Abstract: Thermal sensors (TS) are essential for achieving optimized performance and reliability in the era of nanoscale microprocessor and system on chip (SoC). Compiling with the low-power and small die area of the mobile computing, the presented TS supports a wide range of sampling frequencies with an optimized power envelope. The TS supports up to 45 K samples/s, low average power consumption, as low as 20 μW, and small core Si area of 0.013 mm2. Advanced circuit techniques are used in order to overcome process variability, ensuring inaccuracy lower than ±2 °C without any calibration. All this makes the presented thermal sensor a cost-effective, low-power solution for 22 nm nanoscale digital process technology.
J. Low Power Electron. Appl.2014, 4(4), 292-303; doi:10.3390/jlpea4040292 - published 26 November 2014 Show/Hide Abstract
Abstract: An ultra-low voltage sixth-order low pass filter topology, suitable for sensing the T-wave signal in an electrocardiogram (ECG), is presented in this paper. This is realized using a cascade connection of second-order building blocks constructed from a sinh-domain two-integrator loop. The performance of the filter has been evaluated using the Cadence Analog Design Environment and the design kit provided by the Austria Mikro Systeme (AMS) 0.35-µm CMOS process. The power consumption of filters was 7.21 nW, while a total harmonic distortion (THD) level of 4% was observed for an input signal of 220 pA. The RMS value of the input referred noise was 0.43 pA, and the simulated value of the dynamic range (DR) was 51.1 dB. A comparison with already published counterparts shows that the proposed topology offers the benefits of 0.5-V supply voltage operation and significantly improved power efficiency.