Reprint
Miniaturized Transistors
Edited by
June 2019
202 pages
- ISBN978-3-03921-010-7 (Paperback)
- ISBN978-3-03921-011-4 (PDF)
This book is a reprint of the Special Issue Miniaturized Transistors that was published in
Chemistry & Materials Science
Engineering
Physical Sciences
Summary
What is the future of CMOS? Sustaining increased transistor densities along the path of Moore's Law has become increasingly challenging with limited power budgets, interconnect bandwidths, and fabrication capabilities. In the last decade alone, transistors have undergone significant design makeovers; from planar transistors of ten years ago, technological advancements have accelerated to today's FinFETs, which hardly resemble their bulky ancestors. FinFETs could potentially take us to the 5-nm node, but what comes after it? From gate-all-around devices to single electron transistors and two-dimensional semiconductors, a torrent of research is being carried out in order to design the next transistor generation, engineer the optimal materials, improve the fabrication technology, and properly model future devices. We invite insight from investigators and scientists in the field to showcase their work in this Special Issue with research papers, short communications, and review articles that focus on trends in micro- and nanotechnology from fundamental research to applications.
Format
- Paperback
License
© 2019 by the authors; CC BY-NC-ND license
Keywords
flux calculation; etching simulation; process simulation; topography simulation; CMOS; field-effect transistor; ferroelectrics; MOS devices; negative-capacitance; piezoelectrics; power consumption; thin-film transistors (TFTs); compact model; surface potential; technology computer-aided design (TCAD); metal oxide semiconductor field effect transistor (MOSFET); topography simulation; metal gate stack; level set; high-k; fin field effect transistor (FinFET); line edge roughness; metal gate granularity; nanowire; non-equilibrium Green’s function; random discrete dopants; SiGe; variability; band-to-band tunneling (BTBT); electrostatic discharge (ESD); tunnel field-effect transistor (TFET); Silicon-Germanium source/drain (SiGe S/D); technology computer aided design (TCAD); bulk NMOS devices; radiation hardened by design (RHBD); total ionizing dose (TID); Sentaurus TCAD; layout; two-dimensional material; field effect transistor; indium selenide; phonon scattering; mobility; high-κ dielectric; low-frequency noise; silicon-on-insulator; MOSFET; inversion channel; buried channel; subthreshold bias range; low voltage; low energy; theoretical model; process simulation; device simulation; compact models; process variations; systematic variations; statistical variations; FinFETs; nanowires; nanosheets; semi-floating gate; synaptic transistor; neuromorphic system; spike-timing-dependent plasticity (STDP); highly miniaturized transistor structure; low power consumption; drain engineered; tunnel field effect transistor (TFET); polarization; ambipolar; subthreshold; ON-state; doping incorporation; plasma-aided molecular beam epitaxy (MBE); segregation; silicon nanowire; n/a