A 0.5-V Four-Stage Amplifier Using Cross-Feedforward Positive Feedback Frequency Compensation

: This paper presents a low-voltage CMOS four-stage amplifier operating in the subthresh-old region. The first design technique includes the cross-feedforward positive feedback frequency compensation (CFPFC) for obtaining better bandwidth efficiency in a low-voltage multi-stage amplifier. The second design technique incorporates both the bulk-drain-driven input stage topology in conjunction with a low-voltage attenuator to permit operation at a low voltage, and improves the input common-mode range (ICMR). The proposed circuit is implemented using TSMC-40 nm process technology. It consumes 0.866 µ W at a supply voltage of 0.5 V. With a capacitive load of 50 pF, this four-stage amplifier can achieve 84.59 dB in gain, 161.00 kHz in unity-gain bandwidth, 96 deg in phase margin, and 5.7 dB in gain margin whilst offering an input-referred noise of 213.63 nV/ √ Hz @1 kHz, small-signal power-bandwidth FoM ss of 9.31 (MHz · pF/ µ W), and noise-power per bandwidth-based FoM npb of 1.15 × 10 − 6 (( µ V/ √ Hz) · µ W/Hz). Compared to the conventional bulk-driven input stage design technique, it offers improved multi-parameter performance metrics in terms of noise, power, and bandwidth at a compromising tradeoff on ICMR with respect to bulk-driven amplifier design. Compared with conventional gate-source input stage design, it offers improved ICMR. The amplifier is useful for low-voltage analog signal-processing applications.


Introduction
With the trend of integration as well as low-voltage low-power implementations, highgain, high-swing circuits are important building blocks in integrated circuits and systems.These are particularly useful for applications in the Internet-of-Things [1][2][3] or energyharvesting circuits [4] that produce the usual low-voltage supply sources.Not only do these high-gain and high-swing circuits enhance weak signals in the amplification process under low-voltage environment, they also provide compatibility with other low-voltage circuit blocks.As such, good quality analog signal processing is maintained.
The bulk-driven configuration is frequently employed as the input stage in rail-to-rail circuits due to its ability to enhance the common mode range under very-low-voltage designs.However, the bulk-driven approach exhibits a reduced transconductance (g m ), narrower bandwidth, and higher level of leakage current and noise, which may degrade the circuit's performance as the design tradeoff.
For low-voltage design, many multi-stage amplifier topologies [5][6][7][8][9] are well reported.However, in the context of amplifiers realized by advanced technology nodes, the usual gain factor in an amplification stage becomes ineffective due to the problem of output resistance encountered by MOS devices.As such, the increase in the number of stages is unavoidable to meet high gain purposes.This leads to increased complexity in frequency compensation.The price paid for this may be a large tradeoff in the performance metrics pertaining to power consumption and gain bandwidth.The first motivation of this work

Review of Frequency Compensation in Three-Stage Amplifier Topologies
Nested Miller compensation (NMC) [6,8] is a popular scheme for high gain amplifier design with good stability with respect to single Miller compensation (SMC) [6]. Figure 1 depicts the NMC configuration for a three-stage amplifier.In principle, NMC can be expanded to an infinite number of stages.However, with more than three stages, the bandwidth is significantly jeopardized.In order to eliminate the peak effect of high-order complex poles, the polynomial is approximated by the Butterworth expression [9].This is given as follows: Relating the Butterworth expression  () and the NMC expression  (), we obtain Referring to Figure 1, g m1-3 are the transconductance of the three-stage amplifier.g o1-3 are the output conductance of the amplifier.C o1-3 are the output capacitance of the amplifier, and C m1 and C m2 are the two compensation capacitors of the NMC amplifier.Assuming g m3 >> g m1 ,g m2 , the transfer function for a three-stage NMC amplifier is obtained as g m2 g m3 ) (1 + sC m1 g m2 g m3 g o1 g o2 g o3 ) 1 + s C m2 g m2 + s 2 C L C m2 g m2 g m3 (1) In order to eliminate the peak effect of high-order complex poles, the polynomial is approximated by the Butterworth expression [9].This is given as follows: (2) Relating the Butterworth expression A butterworth (s) and the NMC expression A N MC (s), we obtain Then the unity-gain bandwidth (UGB) and phase margin PM become Alternatively, Positive Feedback Compensation (PFC) [10] can be used to provide control of the damping ratio of the complex poles, which is achieved through capacitor C m2 .This capacitor, considerably smaller than C m1 , does not cause the significant slew rate (SR) reduction associated with the first stage whilst additionally generating a LHP zero to enhance the PM.The PFC topology is depicted in Figure 2. Of particular note, g m1-3 are the transconductance of the three-stage amplifier.g o1-3 are the output conductance of the amplifier.C o1-3 are the output capacitance of the amplifier, and C m1 and C m2 are the two compensation capacitors of the PFC amplifier.
Chips 2024, 3, 1 3 of 31 Then the unity-gain bandwidth (UGB) and phase margin PM become Alternatively, Positive Feedback Compensation (PFC) [10] can be used to provide control of the damping ratio of the complex poles, which is achieved through capacitor Cm2.This capacitor, considerably smaller than Cm1, does not cause the significant slew rate (SR) reduction associated with the first stage whilst additionally generating a LHP zero to enhance the PM.The PFC topology is depicted in Figure 2. Of particular note, gm1-3 are the transconductance of the three-stage amplifier.go1-3 are the output conductance of the amplifier.Co1-3 are the output capacitance of the amplifier, and Cm1 and Cm2 are the two compensation capacitors of the PFC amplifier.
In order for all poles to be located in the left half plane, each term in the denominator must be greater than 0. This leads to the following design relationship: Thus, the GBW is obtained as follows: −  (10) and the PM becomes Another ASMIHF compensation topology [11] is depicted in Figure 3.It employs an active single-Miller capacitor and an inner half-feedforward stage so that it facilitates the stabilization of a three-stage amplifier that is able to drive substantial capacitive loads.The transfer function of the PFC amplifier is given as follows: In order for all poles to be located in the left half plane, each term in the denominator must be greater than 0. This leads to the following design relationship: Thus, the GBW is obtained as follows: and the PM becomes Another ASMIHF compensation topology [11] is depicted in Figure 3.It employs an active single-Miller capacitor and an inner half-feedforward stage so that it facilitates the stabilization of a three-stage amplifier that is able to drive substantial capacitive loads.This is accomplished through the incorporation of a small feedback compensation capacitor and the utilization of two left LHP zeros.ASMIHF contributes to reduced silicon die area occupation, streamlined design complexity, and enhanced small and large signal performance metrics.In addition, two supplementary and cost-effective feedforward stages, with transconductances g mf1 and g mf2 , are employed to enhance stability and achieve a dual-active push-pull operation.g mc1 is the active feedback stage.In conjunction with the gain A v2 of the second stage, it relates ω o and Q in the complex equation.This may affect the circuit stability if not properly designed.
This is accomplished through the incorporation of a small feedback compensation capacitor and the utilization of two left LHP zeros.ASMIHF contributes to reduced silicon die area occupation, streamlined design complexity, and enhanced small and large signal performance metrics.In addition, two supplementary and cost-effective feedforward stages, with transconductances gmf1 and gmf2, are employed to enhance stability and achieve a dualactive push-pull operation.gmc1 is the active feedback stage.In conjunction with the gain Av2 of the second stage, it relates ωo and Q in the complex equation.This may affect the circuit stability if not properly designed.The transfer function of the ASMIHF amplifier is given as follows: where  = and Q =  .To obtain a smooth characteristic curve similar to Butterworth's third-order response, Q is assumed to be √ as an example.This gives  = 2g ,  =  , and  = , respectively, and the GBW is .Due to the existence of gmc1 and gmc2, this combination with the load transistor will inevitably form a cascode structure.Therefore, the structure is not suitable for working at a low supply voltage.

Review of Frequency Compensation in Four-Stage Amplifier Topologies
Similar to the three-stage op-amp topology, multiple nested Miller compensation [12] is a traditional frequency compensation method in four-stage op-amp design.The multiple nested Miller compensation topology is depicted in Figure 4.The transfer function of the ASMIHF amplifier is given as follows: where . To obtain a smooth characteristic curve similar to Butterworth's third-order response, Q is assumed to be √ 3 2 as an example.This gives g mc1 = 2g m1 , g mc2 = 3  2 g m1 , and , respectively, and the GBW is . Due to the existence of g mc1 and g mc2 , this combination with the load transistor will inevitably form a cascode structure.Therefore, the structure is not suitable for working at a low supply voltage.

Review of Frequency Compensation in Four-Stage Amplifier Topologies
Similar to the three-stage op-amp topology, multiple nested Miller compensation [12] is a traditional frequency compensation method in four-stage op-amp design.The multiple nested Miller compensation topology is depicted in Figure 4.
This is accomplished through the incorporation of a small feedback compensation capacitor and the utilization of two left LHP zeros.ASMIHF contributes to reduced silicon die area occupation, streamlined design complexity, and enhanced small and large signal performance metrics.In addition, two supplementary and cost-effective feedforward stages, with transconductances gmf1 and gmf2, are employed to enhance stability and achieve a dualactive push-pull operation.gmc1 is the active feedback stage.In conjunction with the gain Av2 of the second stage, it relates ωo and Q in the complex equation.This may affect the circuit stability if not properly designed.The transfer function of the ASMIHF amplifier is given as follows: where  = and Q =  .To obtain a smooth characteristic curve similar to Butterworth's third-order response, Q is assumed to be √ as an example.This gives  = 2g ,  =  , and  = , respectively, and the GBW is .Due to the existence of gmc1 and gmc2, this combination with the load transistor will inevitably form a cascode structure.Therefore, the structure is not suitable for working at a low supply voltage.

Review of Frequency Compensation in Four-Stage Amplifier Topologies
Similar to the three-stage op-amp topology, multiple nested Miller compensation [12] is a traditional frequency compensation method in four-stage op-amp design.The multiple nested Miller compensation topology is depicted in Figure 4.  Regarding the topology, g m1-4 are the transconductances of the four-stage amplifier.g o1-4 are the output conductances of the amplifier, C o1-4 are the output capacitances of the amplifier, and C m1 , C m2 and C m3 are the three compensation capacitors of the multiple NMC amplifier.When dealing with a multi-stage operational amplifier, determining the precise location of nondominant poles can be tedious calculation.Without specific precautions, these poles may interact.Thus, they lead to complex pairs which cause stability issues.The basic rules for this amplifier design are given as follows: where G mi and C i are the transconductance and compensation capacitor of the ith stage, respectively.The first stability condition, expressed in (14), requires that each nondominant pole be positioned at a frequency at least two times of the preceding one.The output of the first stage is assumed to contribute the dominant pole, while the outputs of the subsequent n -1 stages produce the nondominant poles.Nevertheless, the fulfillment of ( 14) requires considerable constraint on the overall bandwidth of an amplifier when the number of stages increases.In the design of power operational amplifiers, ( 15) is readily fulfilled.This is attributed to the condition that the transconductance of the final stage must be larger than that of the preceding stages to effectively drive substantial loads.Alternatively, the hybrid nested Miller compensation (HNMC) structure [13] or the hybrid cascode frequency compensation structure [14] can be used to further improve the achievable bandwidth of a four-stage op-amp.The hybrid nested Miller compensation (HNMC) structure, which is illustrated in Figure 5, has the feedback capacitors across their respective local inverting stages as well as across inverting multi-stages.
Chips 2024, 3, 1 Regarding the topology, gm1-4 are the transconductances of the four-stage am go1-4 are the output conductances of the amplifier, Co1-4 are the output capacitances amplifier, and Cm1, Cm2 and Cm3 are the three compensation capacitors of the multiple amplifier.When dealing with a multi-stage operational amplifier, determining the p location of nondominant poles can be tedious calculation.Without specific precau these poles may interact.Thus, they lead to complex pairs which cause stability The basic rules for this amplifier design are given as follows: where Gmi and Ci are the transconductance and compensation capacitor of the ith respectively.The first stability condition, expressed in (14), requires that each non nant pole be positioned at a frequency at least two times of the preceding one.The o of the first stage is assumed to contribute the dominant pole, while the outputs subsequent n -1 stages produce the nondominant poles.Nevertheless, the fulfillm ( 14) requires considerable constraint on the overall bandwidth of an amplifier wh number of stages increases.In the design of power operational amplifiers, ( 15) is r fulfilled.This is attributed to the condition that the transconductance of the fina must be larger than that of the preceding stages to effectively drive substantial load Alternatively, the hybrid nested Miller compensation (HNMC) structure [13] hybrid cascode frequency compensation structure [14] can be used to further impro achievable bandwidth of a four-stage op-amp.The hybrid nested Miller compen (HNMC) structure, which is illustrated in Figure 5, has the feedback capacitors acros respective local inverting stages as well as across inverting multi-stages.As can be seen in Figure 5, two Miller loops involving Cm2 and Cm3 operate same nesting level.Cm1 is also a compensation capacitor within the negative feedbac gm1-4 are the transconductances of the four-stage amplifier.go1-4 are the output conduc of the amplifier.Co1-4 are the output capacitances of the amplifier.An exemplary freq compensation condition is achieved as follows: where CL is the load capacitor.At this juncture, according to (14), the unity-gain freq of the op-amp can be obtained as follows:

𝑔 𝐶
where  is the unity-gain frequency of op-amp.Compared with the  = gle Miller compensation (SMC), HNMC has only two nested levels, and th As can be seen in Figure 5, two Miller loops involving C m2 and C m3 operate on the same nesting level.C m1 is also a compensation capacitor within the negative feedback loop.g m1-4 are the transconductances of the four-stage amplifier.g o1-4 are the output conductances of the amplifier.C o1-4 are the output capacitances of the amplifier.An exemplary frequency compensation condition is achieved as follows: where C L is the load capacitor.At this juncture, according to (14), the unity-gain frequency of the op-amp can be obtained as follows: where ω t is the unity-gain frequency of op-amp.Compared with the ω t = 1 2 g m4 C L of single Miller compensation (SMC), HNMC has only two nested levels, and thus the bandwidth is reduced by half.If multiple nested Miller compensation is used, since it has three nested levels, its bandwidth will be reduced to a quarter of SMC.
Chips 2024, 3 6 Another typology, nested transconductance-capacitance compensation (NGCC) [15], is another way to improve the bandwidth of a four-stage op-amp.The NGCC is depicted in Figure 6.
bandwidth is reduced by half.If multiple nested Miller compensation is used, since it has three nested levels, its bandwidth will be reduced to a quarter of SMC.
Another typology, nested transconductance-capacitance compensation (NGCC) [15], is another way to improve the bandwidth of a four-stage op-amp.The NGCC is depicted in Figure 6.In general, the i-th module comprises a transconductor gmi, a feed-forward trans-conductor gmfi, an output conductance goi, and a compensation capacitor Coi.The DC voltage gain of the amplifier, as shown in Figure 6, is governed by the combined gain of the n + 1 cascaded stages (gm1, gm2, ..., gmn, gmn+1).At high frequencies, when the gain of these stages decreases, the feed-forward transconductance gmf bypasses all stages from (i + 1) to n, effectively extending the overall amplifier bandwidth.When gmi = gmfi, the transfer function of the NGCC amplifier can be obtained as follows: where  = ∏ and  = .The stability conditions for the NGCC-based topology are determined by applying the Routh stability criterion to the unity-gain closed-loop transfer function.This yields the following stability criteria: On the contrary, the stability conditions for multistage NMC amplifiers introduces complexity to the design process.On the other hand, when designing a stable multistage NGCC amplifier, it is more straightforward.
By comparing the bandwidth of a four-stage NGCC amplifier with that of an NMC amplifier and taking frequency normalization with respect to the gain bandwidth (GBW), the following can be obtained: In general, the i-th module comprises a transconductor g mi , a feed-forward transconductor g mfi , an output conductance g oi , and a compensation capacitor C oi .The DC voltage gain of the amplifier, as shown in Figure 6, is governed by the combined gain of the n + 1 cascaded stages (g m1 , g m2 , . .., g mn , g mn+1 ).At high frequencies, when the gain of these stages decreases, the feed-forward transconductance g mf bypasses all stages from (i + 1) to n, effectively extending the overall amplifier bandwidth.When g mi = g mfi , the transfer function of the NGCC amplifier can be obtained as follows: where . The stability conditions for the NGCC-based topology are determined by applying the Routh stability criterion to the unity-gain closed-loop transfer function.This yields the following stability criteria: On the contrary, the stability conditions for multistage NMC amplifiers introduces complexity to the design process.On the other hand, when designing a stable multistage NGCC amplifier, it is more straightforward.
By comparing the bandwidth of a four-stage NGCC amplifier with that of an NMC amplifier and taking frequency normalization with respect to the gain bandwidth (GBW), the following can be obtained: where f 4 and GBW are the cut-off frequency and gain-bandwidth product of final stage of NGCC amplifier, respectively, whereas f ′ 2 , f ′ 3 , f ′ 4 and GBW ′ are the cut-off frequencies of the 2, 3, 4 stages and gain-bandwidth product of the final stage of the four-stage NGCC amplifier, respectively.Equation (20) implies that GBW ′ , which means the GBW of NGCC, is greater than that of NMC for the same power ( f 4 = f ′ 4 ).However, all feedforward paths of NGCC are connected to the output of the last stage, which leads to an increase in power consumption.
where  and GBW are the cut-off frequency and gain-bandwidth product of final stage of NGCC amplifier, respectively, whereas  ,  ,  and  are the cut-off frequencies of the 2, 3, 4 stages and gain-bandwidth product of the final stage of the four-stage NGCC amplifier, respectively.Equation (20) implies that < , which means the GBW of NGCC, is greater than that of NMC for the same power ( =  ).However, all feedforward paths of NGCC are connected to the output of the last stage, which leads to an increase in power consumption.
where It is noted that g mi , R oi , and C oi represent the transconductance, output resistance, and capacitance of the nth stage, respectively.The feedforward stage is denoted by g mf .R L and C L indicate the load resistance and capacitance, including the output resistance and capacitance of the final stage.The compensation capacitors are C m1 and C m2 , while the nulling resistors are R m1 and R m2 .C m1 and R m1 together form the primary Miller compensation signal path for the entire amplifier.A secondary Miller compensation signal path is established by C m2 and R m2 .The transfer function of the four-Stage SMF amplifier is obtained as follows: where To enhance push-pull behavior, the nulling resistor should be selected by the following design criteria.They are given as Then the GBW and PM can be obtained as follows: Separating the nested Miller compensation into two independent Miller compensation networks can improve the power efficiency of the op-amp.However, the compensation scheme may face design challenges in controlling the stability.This stems from the fact that it can only determine the position between the two poles, but not the position between the four poles.As a result, there may be overlap between multiple poles.When multiple poles coincide, there will be a stability problem and the bandwidth will be limited.In the case of ultra-low power design constraints, the extension of higher bandwidth becomes an issue.
In brief, multiple nested Miller compensation is one of the common frequency compensation methods.Because of its many nested levels and excessive capacitance, the bandwidth of the four-stage op-amp will be greatly limited and consume a larger area.According to (14), HNMC designed on the basis of multiple nested Miller compensation has fewer nested levels.By comparing this with SMC, the bandwidth attenuation that it brings is 1   2   of the bandwidth attenuation by multiple nested Miller compensation.Furthermore, the realizable bandwidth of a four-stage HNMC amplifier can be designed the same as that of the three-stage NMC op-amp [15].NGCC introduces a feedforward circuit and a Miller capacitor to work together for frequency compensation.It can be seen from ( 19) that NGCC can significantly increase the bandwidth, but this is at the expense of increased power consumption.Based on the review of these frequency compensation schemes, it is important to devise an effective frequency compensation that is suitable for an ultra-low-voltage four-stage amplifier design.

Review of Low-Voltage Rail-to-Rail Amplifier Circuits
The bulk-driven technique is widely used in low-voltage rail-to-rail circuit design, and the ICMR can offer 0-V dd range.The two-stage bulk-driven rail-to-rail amplifier, which is realized in differential difference amplifier (DDA) [19] topology, is shown in Figure 8. Transistors M 1A -M 1B and M 3A -M 3B are the input differential pairs while the biasing circuit comprises the biasing transistor pairs M 2A -M 2A , M 5A -M 5B , M 4A -M 4B , and M 6A -M 6B .The cross-coupled transistors M 7A and M 7B , in association with the diode-connected transistors M 8A and M 8B , enhance the gain through partial positive feedback by introducing negative transconductance (−g m7 ).Transistors M 9A , M 9B , M 10A , and M 10B form the differential to single-ended conversion for the first-stage gain.Transistors The gain of bulk-driven DDA is where The GBW is For bulk-driven circuits, gmbs replaces gm as the transconductance of the circuit.Since gmbs is very small, the gain of the bulk-driven circuit is very small.The same goes for the gain-bandwidth product.As such, the thermal noise performance metric will be worse due to small transconductance in the front-end stage.
The traditional complementary gate-source input stage amplifier [20] is shown in Figure 9.It is regarded as one of the economical circuit techniques by utilizing a 1-to-3 current mirror.The design operates in the saturation region, with a supply voltage of 3.3V.M1-4 are the input differential input pairs which are composed of complementary PMOS and NMOS transistors for rail-to-rail design.M5-6, 7-8 are the cascode transistors and M15-16 are the current source transistors.M10-11, 13-14 are used to implement current mirrors with a 1-to-3 ratio for approximated constant gm design.The gain of bulk-driven DDA is where The GBW is For bulk-driven circuits, g mbs replaces g m as the transconductance of the circuit.Since g mbs is very small, the gain of the bulk-driven circuit is very small.The same goes for the gain-bandwidth product.As such, the thermal noise performance metric will be worse due to small transconductance in the front-end stage.
The traditional complementary gate-source input stage amplifier [20] is shown in Figure 9.It is regarded as one of the economical circuit techniques by utilizing a 1-to-3 current mirror.The design operates in the saturation region, with a supply voltage of 3.3V.M 1-4 are the input differential input pairs which are composed of complementary PMOS and NMOS transistors for rail-to-rail design.M 5-6, 7-8 are the cascode transistors and M 15-16 are the current source transistors.M 10-11, 13-14 are used to implement current mirrors with a 1-to-3 ratio for approximated constant g m design.The overall transconductance of input stage is defined as where Iref1,2 are the bias currents of the NMOS pair and PMOS pair, respectively.For complementary circuits without gmi smoothing, the combined gmi of the input stage under either the lower or upper part of common-mode range is half of the overall value.This will be double in value in the middle range.The same goes for unity-gain bandwidth.There are many ways to make the approximated constant gmi.Alternatively, it can be achieved through the level shift approach [21], which relies on the input transistor pairs to operate in the saturation region.Similarly, it also offers less sensitivity on gmi variation against the change of input signal.Unfortunately, when pushing for lower supply, the available signal headroom in conjunction with unavoidable output spikes through the variation of gmi will be reduced.In poor conditions, the rail-to-rail circuit will be jeopardized in operation, and this will be particularly pronounced when the rail-to-rail complementary input pairs are biased in the sub-threshold region for obtaining low power purpose.

Proposed Four-Stage Amplifier with Cross-Feedforward Positive Frequency Compensation (CFPFC)
Figure 10 shows the circuit of the proposed four-stage amplifier in TSMC 40 nm process technology.The amplifier consists of a bias circuit, a bulk-drain transistor input stage, an attenuation stage, and a high-gain stage.The bias circuit consists of a supply-independent topology and a start-up network (MB1-6, CB1-2).For the input stage, it consists of the complementary topology which is embedded with the bulk-drain differential pairs (Mp1-2, Mn1-2) and the respective load transistors (M3-6).This is then followed by the attenuation stage (Mna1-Mna4, M7, 8) in a source-follower-like topology, comprising two native transistors and one low-threshold transistor in each output of the first stage.
As mentioned before, the rail-to-rail input circuits, under a low supply voltage and a subthreshold operation region, can influence subsequent amplification stages through large variations in the first stage's output spike under high fluctuations of gmi.Moreover, under limited supply, the IMCR becomes ineffective in the gate-source biased differential pairs despite the gmi obtained from a gate-source biased transistor being relatively higher than that of a bulk-driven transistor.
Regarding the bulk-driven input stage, this has high ICMR capability through the use of gmb as the main transconductance.However, its gain and driving capabilities are low.For this reason, the bulk-drain-driven [22] differential pairs are introduced to obtain the design tradeoff between the gate-source or bulk-driven techniques.This can offer an improved IMCR with respect to that of the gate-source driven technique, whilst the The overall transconductance of input stage is defined as where I ref1,2 are the bias currents of the NMOS pair and PMOS pair, respectively.For complementary circuits without g mi smoothing, the combined g mi of the input stage under either the lower or upper part of common-mode range is half of the overall value.This will be double in value in the middle range.The same goes for unity-gain bandwidth.There are many ways to make the approximated constant g mi .Alternatively, it can be achieved through the level shift approach [21], which relies on the input transistor pairs to operate in the saturation region.Similarly, it also offers less sensitivity on g mi variation against the change of input signal.Unfortunately, when pushing for lower supply, the available signal headroom in conjunction with unavoidable output spikes through the variation of g mi will be reduced.In poor conditions, the rail-to-rail circuit will be jeopardized in operation, and this will be particularly pronounced when the rail-to-rail complementary input pairs are biased in the sub-threshold region for obtaining low power purpose.

Proposed Four-Stage Amplifier with Cross-Feedforward Positive Frequency Compensation (CFPFC)
Figure 10 shows the circuit of the proposed four-stage amplifier in TSMC 40 nm process technology.The amplifier consists of a bias circuit, a bulk-drain transistor input stage, an attenuation stage, and a high-gain stage.The bias circuit consists of a supplyindependent topology and a start-up network (M B1-6 , C B1-2 ).For the input stage, it consists of the complementary topology which is embedded with the bulk-drain differential pairs (M p1-2 , M n1-2 ) and the respective load transistors (M 3-6 ).This is then followed by the attenuation stage (M na1 -M na4 , M 7, 8 ) in a source-follower-like topology, comprising two native transistors and one low-threshold transistor in each output of the first stage.
As mentioned before, the rail-to-rail input circuits, under a low supply voltage and a subthreshold operation region, can influence subsequent amplification stages through large variations in the first stage's output spike under high fluctuations of g mi .Moreover, under limited supply, the IMCR becomes ineffective in the gate-source biased differential pairs despite the g mi obtained from a gate-source biased transistor being relatively higher than that of a bulk-driven transistor.
bandwidth as well as the stability of the PFC amplifier.Furthermore, introducing a positive feedback loop effectively governs the damping ratio of the complex poles.This can be achieved by fulfilling the design equations for the compensation capacitors in subsequent transfer function analysis.By properly sizing the compensation capacitors, the usual RHP poles can be moved to LHP for stability.Furthermore, both FF and PFC yield LHP zeros to ensure stability in multi-stage amplifier design.
where Regarding the bulk-driven input stage, this has high ICMR capability through the use of g mb as the main transconductance.However, its gain and driving capabilities are low.For this reason, the bulk-drain-driven [22] differential pairs are introduced to obtain the design tradeoff between the gate-source or bulk-driven techniques.This can offer an improved IMCR with respect to that of the gate-source driven technique, whilst the transconductance is not reduced significantly due to weak degeneration arising from bulk-drain transistor topology.As a result of this weak degeneration, the amplifier's parameters such as noise, gain, and bandwidth are still higher than that of bulk-driven circuits.Furthermore, in comparison with bulk-drain-driven circuits, the temperature effect of bulk-driven is less obvious [22].As a result, the bulk-drain-driven circuit can provide a compromising design solution among the transconductance and signal swing in low-voltage design.
The use of native transistors (with negative threshold voltage) ensures low-voltage operation.As such, the use of diode-based transistors permits attenuation of any spike [22] that appears through the transition change of transconductance from the complementary differential pairs.This reduced spike will not overdrive the subsequent stage, thus does not jeopardize the amplification in the next circuit stage.In this way, it is economical to remove the conventional transconductance smoothing circuits [23][24][25].This is particularly useful because it offers simplicity whilst reducing the power consumption and complexity as well as avoiding a higher supply in conventional methods.
After the low-voltage attenuator, it is the high-gain stage that drives the 50 pF capacitive load.This gain stage (M 9-20 ) contains two non-inverting amplifiers, one push-pull stage, three feed-forward paths, and the capacitors (C m1-2 ) dedicated to the positive frequency compensation.
The cross-feedforward paths, with which to bypass the respective stage, enhance the bandwidth as well as the stability of the PFC amplifier.Furthermore, introducing a positive feedback loop effectively governs the damping ratio of the complex poles.This can be achieved by fulfilling the design equations for the compensation capacitors in subsequent transfer function analysis.By properly sizing the compensation capacitors, the usual RHP poles can be moved to LHP for stability.Furthermore, both FF and PFC yield LHP zeros to ensure stability in multi-stage amplifier design.
Figure 11 depicts the block diagram of the proposed four-stage amplifier.Assuming that the parasitic capacitances in each stage are neglectable, the open-loop transfer function of the amplifier is obtained as follows: where As a result, within the bandwidth, there is no peak effect caused by high-order complex poles.Since gm2 is derived from the attenuation buffer output (source output), its resistance R2 is very small and so is the time constant R2C2.From (41), p4 is (1/I) and p5 is (1/H).These are high-frequency poles when compared with other poles.At this juncture, considering the main pole ω0 and the secondary poles ω2,3, the expression can be obtained as follows: Incorporating the effect of higher frequency zero, z1, the PM becomes Figure 12 shows the pole-zero location of CFPFC op-amp.p0 is the dominant pol, p2, p3 are complex poles, and p4, p5 are the high-frequency poles produced by H and I in For positive feedback compensation, the most important thing is to consider the instability which comes from two aspects: 1.
There may be a RHP pole that causes oscillation; 2.
The peak introduced by the existence of high-order complex polynomial.
In order to tackle the first issue, all the poles must be located in LHP.This requires each coefficient of the denominator to be greater than 0. Thus, we have This yields the need for a larger C m2 and a smaller C m1 .At this juncture, due to the introduction of the feedforward path, the compensation capacitor C m2 in the CFPFC amplifier can be made smaller than that in the PFC amplifier without a feedforward design.As a result, this achieves increased bandwidth while keeping a small area arising from the capacitors.Regarding the peak effect caused by the high-order complex pole equation, it is necessary to choose the damping ratio by controlling the ratio between C m1 and C m2 so as to permit the loop gain curve to be as smooth as possible.According to Butterworth Equations ( 2) and (3), it is necessary to arrange the higher-order complex pole equation into a similar form.Assuming C L ≫ C m2 ≫ C m1 , the transfer function becomes By replacing E, F, G with ω 0 and ω n , we get where ω 0 is the dominant pole, ω n is the non-damped frequency.Therefore, the secondary poles are 2 , we can obtain the following relationship. 2 1 By solving the above equations, we have obtained the design equations for the compensation capacitors and the dominant pole.They are given as follows: As a result, within the bandwidth, there is no peak effect caused by high-order complex poles.Since g m2 is derived from the attenuation buffer output (source output), its resistance R 2 is very small and so is the time constant R 2 C 2 .From (41), p 4 is (1/I) and p 5 is (1/H).These are high-frequency poles when compared with other poles.At this juncture, considering the main pole ω 0 and the secondary poles ω 2,3 , the expression can be obtained as follows: Incorporating the effect of higher frequency zero, z 1 , the PM becomes Figure 12 shows the pole-zero location of CFPFC op-amp.p 0 is the dominant pol, p 2, p 3 are complex poles, and p 4 , p 5 are the high-frequency poles produced by H and I in Equation (41).Of particular note, z 1 , z 2 , z 3 are the high-frequency LHP zeros caused by the feedforward paths and PFC.Through the stated design criteria for the compensation capacitors, the complex poles p 2, p 3 are now moved to the LHP.The dimensions of each device are listed in Table 1.
Equation (41).Of particular note, z1, z2, z3 are the high-frequency LHP zeros caused by the feedforward paths and PFC.Through the stated design criteria for the compensation capacitors, the complex poles p2, p3 are now moved to the LHP.The dimensions of each device are listed in Table 1.

Results and Discussion
The four-stage op-amp is designed and implemented using TSMC 40 nm CMOS process technology.The circuit operates at 0.5 V supply and drives the capacitive load of 50 pF.
Figure 13 shows the simulated DC gain, gain bandwidth (GBW), phase margin (PM), and gain margin (GM) of the proposed amplifier at different corners.At the tt corner, the corresponding values are 84.588dB, 161 kHz, 96 degrees, and 5.7 dB.At the ss corner, the respective values are 88.2 dB, 65.9 kHz, 76.11 degrees, and 8.23 dB.At the ff corner, the respective values are 75.37 dB, 247.9 kHz, 101.66 degrees, and 11.94 dB.It can be observed

Results and Discussion
The four-stage op-amp is designed and implemented using TSMC 40 nm CMOS process technology.The circuit operates at 0.5 V supply and drives the capacitive load of 50 pF.
Figure 13 shows the simulated DC gain, gain bandwidth (GBW), phase margin (PM), and gain margin (GM) of the proposed amplifier at different corners.At the tt corner, the corresponding values are 84.588dB, 161 kHz, 96 degrees, and 5.7 dB.At the ss corner, the respective values are 88.2 dB, 65.9 kHz, 76.11 degrees, and 8.23 dB.At the ff corner, the respective values are 75.37 dB, 247.9 kHz, 101.66 degrees, and 11.94 dB.It can be observed that the amplifier is stable at all corners and maintains high gain despite some deviations in gain-bandwidth across the corners.
that the amplifier is stable at all corners and maintains high gain despite some deviations in gain-bandwidth across the corners.Figure 14 depicts the power-supply gain of the proposed amplifier.These are obtained as −56.02 dB at tt, −61.35 dB at ss, and −43.37 dB at ff, respectively.Regarding the power supply rejection ratio (PSRR), the obtained values are 56.02dB at tt, 61.35 dB at ss, and 43.37 dB at ff, respectively.Figure 15 depicts the common-mode gain of the proposed amplifier.These are −57.11dB at tt, −66.76 dB at ss, and −42.61 dB at ff, respectively.These yield the common-mode rejection ratio (CMRR) of 57.11 dB at tt, 66.76 dB at ss, and 42.61 dB at ff, respectively.Due to the high differential-mode gain at low frequency, the obtained PSRR and CMRR values are high.Figure 17 shows the plot of output swing (y-axis) against the input range (x-ax This is based on the unity-gain configuration with different input stage designs with/wi out a low-voltage attenuator in the amplifier at tt condition.The input voltage Vg of input transistors is kept at 250 mV while the supply voltage Vdd is kept at 500 mV and t drain current ID is kept at 150 nA.The simulation results are shown in Figure 17.The fi curve refers to the proposed bulk-drain-driven input topology with the embedded atte uator, and the obtained ICMR is 194 mV (116 mV to 310 mV).The second curve refers the bulk-drain-driven input topology but without an attenuator, and the obtained ICM is 105 mV (227 mV to 332 mV).The third curve denotes the gate-source driven input pology together with an attenuator, and the obtained ICMR is 147 mV (126 mV to 2 mV).The fourth curve denotes the gate-source driven input topology without an atten ator, and the obtained ICMR is 70 mV (224 mV to 294 mV).It can be confirmed that t proposed bulk-drain-driven input topology with an attenuator can effectively impro ICMR with respect to that gate-source driven topology with and without an attenuator Figure 17 shows the plot of output swing (y-axis) against the input range (x-axis).This is based on the unity-gain configuration with different input stage designs with/without a low-voltage attenuator in the amplifier at tt condition.The input voltage V g of all input transistors is kept at 250 mV while the supply voltage V dd is kept at 500 mV and the drain current I D is kept at 150 nA.The simulation results are shown in Figure 17.The first curve refers to the proposed bulk-drain-driven input topology with the embedded attenuator, and the obtained ICMR is 194 mV (116 mV to 310 mV).The second curve refers to the bulk-drain-driven input topology but without an attenuator, and the obtained ICMR is 105 mV (227 mV to 332 mV).The third curve denotes the gate-source driven input topology together with an attenuator, and the obtained ICMR is 147 mV (126 mV to 273 mV).The fourth curve denotes the gate-source driven input topology without an attenuator, and the obtained ICMR is 70 mV (224 mV to 294 mV).It can be confirmed that the proposed bulk-drain-driven input topology with an attenuator can effectively improve ICMR with respect to that gate-source driven topology with and without an attenuator.Figure 18 shows the plot of output swing (y-axis) of a proposed amplifier against the input range (x-axis).This is based on the unity-gain configuration driving a 50 pF load at different corners.As observed, the input range is from 116.3 mV to 310 mV at the tt condition, 90.0 mV to 370 mV at the ss condition, and from 160 mV to 310 mV at the ff condition.From the results, at supply of 0.5 V, the bulk-drain-driven input topology in conjunction with the low-voltage attenuator in amplifier's architectural design permits a swing of up to 40% of Vdd. Figure 18 shows the plot of output swing (y-axis) of a proposed amplifier against the input range (x-axis).This is based on the unity-gain configuration driving a 50 pF load at different corners.As observed, the input range is from 116.3 mV to 310 mV at the tt condition, 90.0 mV to 370 mV at the ss condition, and from 160 mV to 310 mV at the ff condition.From the results, at supply of 0.5 V, the bulk-drain-driven input topology in conjunction with the low-voltage attenuator in amplifier's architectural design permits a swing of up to 40% of V dd .The transient responses of the proposed amplifier are shown in Figure 19.The period of the input square wave is 5 ms, and the rise time and fall time are 1 µs, respectively.It can be seen that the obtained slew rates are 0.064 V/µs and 0.017 V/µs at tt, 0.005 V/µs and 0.0025 V/µs at ss, and 0.005 V/µs and 0.006 V/µs at ff, respectively.In addition, the settling time is 72.49µs at tt, 116.58 µs at ss, and 58.35 µs at ff, respectively.Due to the low-power design, the SR is limited but it can be improved through the use of a SR enhancement circuit or an increase in power consumption.The transient responses of the proposed amplifier are shown in Figure 19.The period of the input square wave is 5 ms, and the rise time and fall time are 1 µs, respectively.It can be seen that the obtained slew rates are 0.064 V/µs and 0.017 V/µs at tt, 0.005 V/µs and 0.0025 V/µs at ss, and 0.005 V/µs and 0.006 V/µs at ff, respectively.In addition, the settling time is 72.49µs at tt, 116.58 µs at ss, and 58.35 µs at ff, respectively.Due to the low-power design, the SR is limited but it can be improved through the use of a SR enhancement circuit or an increase in power consumption.The input-referred noise simulation results are shown in Figure 20.At 1 kHz, the input-referred noise can be obtained as 213.63 nV/√Hz at tt, 343.96 nV/√Hz at ss, and 214.91 nV/√Hz at ff, respectively.Due to relatively higher gmi being obtained from the rail-to-rail bulk-drain-driven topology, the noise performance metrics are better when compared to the bulk-driven input stage design.This also proves that the degeneration effect from the bulk-drain transistor is not significant.Therefore, it is not of concern.√ Hz at ff, respectively.Due to relatively higher g mi being obtained from the rail-to-rail bulk-drain-driven topology, the noise performance metrics are better when compared to the bulk-driven input stage design.This also proves that the degeneration effect from the bulk-drain transistor is not significant.Therefore, it is not of concern.The simulation results pertaining to the variation of input stage transconductan gmi, against the input voltage with and without a low-voltage attenuator are shown Figure 21.It can be observed that due to the complementary circuit, gmi will exhibit obvious spike at the first output stage.Nevertheless, this spike is significantly suppres after passing through the attenuator.This has demonstrated the effectiveness of using attenuator to tackle the gmi variation.Although the attenuator will attenuate the sig gain, the overall gain will be compensated by the subsequent high-gain stage.The simulation results pertaining to the variation of input stage transconductance, g mi , against the input voltage with and without a low-voltage attenuator are shown in Figure 21.It can be observed that due to the complementary circuit, g mi will exhibit an obvious spike at the first output stage.Nevertheless, this spike is significantly suppressed after passing through the attenuator.This has demonstrated the effectiveness of using an attenuator to tackle the g mi variation.Although the attenuator will attenuate the signal gain, the overall gain will be compensated by the subsequent high-gain stage.the mean PM and GM are 79.39 deg and 4.7 dB, respectively.Despite some reduction in PM and GM, these are still acceptable after taking into account parasitic effects, as PM is still maintained at a high rate.As seen in Figures 26 and 27, the mean CMRR and PSRR are 49.3 dB and 49.1 dB, respectively.There is no significant difference when taking the parasitic effect into account.The mean noise is obtained as 205.47 nV/√Hz, which shows that the op-amp's noise is still low when including the parasitic effect according to Figure 28. Figure 29 shows that the mean power consumption is 0.95 µW.These suggest that the op-amp exhibits good performance in the context of process variation and parasitic effects.the mean PM and GM are 79.39 deg and 4.7 dB, respectively.Despite some reduction in PM and GM, these are still acceptable after taking into account parasitic effects, as PM is still maintained at a high rate.As seen in Figures 26 and 27, the mean CMRR and PSRR are 49.3 dB and 49.1 dB, respectively.There is no significant difference when taking the parasitic effect into account.The mean noise is obtained as 205.47 nV/ √ Hz, which shows that the op-amp's noise is still low when including the parasitic effect according to Figure 28. Figure 29 shows that the mean power consumption is 0.95 µW.These suggest that the op-amp exhibits good performance in the context of process variation and parasitic effects.the mean PM and GM are 79.39 deg and 4.7 dB, respectively.Despite some reduction in PM and GM, these are still acceptable after taking into account parasitic effects, as PM is still maintained at a high rate.As seen in Figures 26 and 27, the mean CMRR and PSRR are 49.3 dB and 49.1 dB, respectively.There is no significant difference when taking the parasitic effect into account.The mean noise is obtained as 205.47 nV/√Hz, which shows that the op-amp's noise is still low when including the parasitic effect according to Figure 28. Figure 29 shows that the mean power consumption is 0.95 µW.These suggest that the op-amp exhibits good performance in the context of process variation and parasitic effects.The total current of the entire circuit is 1.73 µA, and the power consumption of the amplifier is only 0.865 µW at 0.5 V.In order compare the performance of amplifiers, different Figure-of-Merits are introduced.FoMss [23] and IFoMss [16] are used to quantify the performance of amplifiers under small-signal conditions.They are defined as follows: where UGB is the unity-gain bandwidth, CL is the load capacitor, Pw is the power consumption, Id is the total current consumption, PM is the phase margin, and Ts is the settling time.Higher values of FoMss and IFoMss indicate better performance metrics.Furthermore, FoMls [23] and IFoMls [16] are used to quantify the large-signal performance of amplifier.They are defined as follows: where SR is slew rate.Similarly, higher values of FoMls, and IFoMls indicate better performance metrics.Finally, in order to compare the effectiveness of amplifiers among the tradeoff performance metrics which involve multiple parameters such as noise, power consumption, and unity-gain bandwidth, a FoMnpb (FoMnoise-power per bandwidth) is used for the evaluation.It is given as follows: FoMnpb =Pw× Input-referred Noise@ 1kHz /UGB (58) The lower the value of FoMnpb, the better the tradeoff performance.
The simulation results of the proposed amplifier show that FoMss and FoMls are 9.31 MHz•pF/µW and 2.34 (V•pF)/(µs•µW), respectively, while FoMnpb is 1.15 × 10 −6 ((µV/√Hz)•µW/Hz).IFoMss and IFoMls are 4.65 (MHz•pF/µA) and 1.17 ((V•pF)/(µs•uA)), respectively.The simulation parameters of each process corner at 27 °C are shown in Table 2.The total current of the entire circuit is 1.73 µA, and the power consumption of the amplifier is only 0.865 µW at 0.5 V.In order compare the performance of amplifiers, different Figure-of-Merits are introduced.FoM ss [23] and IFoM ss [16] are used to quantify the performance of amplifiers under small-signal conditions.They are defined as follows: where UGB is the unity-gain bandwidth, C L is the load capacitor, P w is the power consumption, I d is the total current consumption, PM is the phase margin, and T s is the settling time.Higher values of FoM ss and IFoM ss indicate better performance metrics.Furthermore, FoM ls [23] and IFoM ls [16] are used to quantify the large-signal performance of amplifier.They are defined as follows: FoM ls = SR × C L P w (55) where SR is slew rate.Similarly, higher values of FoM ls , and IFoM ls indicate better performance metrics.Finally, in order to compare the effectiveness of amplifiers among the tradeoff performance metrics which involve multiple parameters such as noise, power consumption, and unity-gain bandwidth, a FoM npb (FoM noise-power per bandwidth ) is used for the evaluation.It is given as follows: FoM npb =P w × Input-referred Noise@1 kHz/UGB (57) The lower the value of FoM npb , the better the tradeoff performance.
The simulation results of the proposed amplifier show that FoM ss and FoM ls are 9.31 MHz•pF/µW and 2.34 (V•pF)/(µs•µW), respectively, while FoM npb is 1.15 × 10 −6 ((µV/ √ Hz)•µW/Hz).IFoM ss and IFoM ls are 4.65 (MHz•pF/µA) and 1.17 ((V•pF)/(µs•uA)), respectively.The simulation parameters of each process corner at 27 • C are shown in Table 2.In order to compare the Cadence Spectre simulation results, an analytical MATLAB model on the basis of Equation ( 41) is developed.This aims at achieving an in-depth understanding of parameters that influence the transfer function.In Figure 30, the blue dotted line is the tt corner simulation data derived from Cadence Spectre, whereas the red solid line is the transmission function illustrated by MATLAB.The left side is the gain and the right side is the phase.It can be seen that the errors among the curves are small (less than 10%).Compared with the results of Spectre, the error is 0.1% (84.05 dB/84.588dB) in DC gain, 1.9% (5.185 Hz/5.284Hz) in dominant pole and 8.70% (175 kHz/161 kHz) in UGB.This validates the analytical Equation (41) from theory.

Conclusions
This paper presents a new 0.5 V four-stage amplifier design that operates at low voltage and low power consumption.Using the bulk-drain-driven input stage allows the op-amp to obtain moderately good g mi while achieving an improved input common-mode range with respect to the complementary rail-to-rail input circuit.This maintains the benefits of low noise and good bandwidth even under low bias current when compared with that of a bulk-driven input stage design.More importantly, the use of a low-voltage attenuator in its architectural design reduces the impact of the output spikes caused by fluctuation of g mi against input signal, thus sustaining the operation of the circuit at very low supply voltages.Furthermore, through the use of cross-feedforward positive feedback compensation, the circuit is verified to have good stability even when the amplifier is realized in a four-stage design.As a result, when the amplifier is compared with prior works, it exhibits good small-signal power-bandwidth FoM ss and good multi-parameter FoM npb with reference to those of bulk-driven designs.This has demonstrated the usefulness of amplifier architecture

Figure 1 .
Figure 1.Topology of a three-stage NMC amplifier.Referring to Figure 1, gm1-3 are the transconductance of the three-stage amplifier.go1-3 are the output conductance of the amplifier.Co1-3 are the output capacitance of the amplifier, and Cm1 and Cm2 are the two compensation capacitors of the NMC amplifier.Assuming gm3 >> gm1,gm2, the transfer function for a three-stage NMC amplifier is obtained as  () = A (1 −    −   ( +  )   ) (1 +       ) 1 +    +

Figure 1 .
Figure 1.Topology of a three-stage NMC amplifier.

Figure 2 .
Figure 2. Topology of a three-stage PFC amplifier.

Figure 4 .
Figure 4. Topology of a four-stage multiple nested Miller compensation amplifier.

Figure 4 .
Figure 4. Topology of a four-stage multiple nested Miller compensation amplifier.Figure 4. Topology of a four-stage multiple nested Miller compensation amplifier.

Figure 4 .
Figure 4. Topology of a four-stage multiple nested Miller compensation amplifier.Figure 4. Topology of a four-stage multiple nested Miller compensation amplifier.

Figure 7 .
Figure 7. Topology of a four-stage SMF amplifier.

Figure 7 .
Figure 7. Topology of a four-stage SMF amplifier.

Figure 10 .
Figure 10. Circuit of the proposed amplifier.

Figure 11 depicts
Figure 11 depicts the block diagram of the proposed four-stage amplifier.Assuming that the parasitic capacitances in each stage are neglectable, the open-loop transfer function of the amplifier is obtained as follows:

Figure 10 .
Figure 10. Circuit of the proposed amplifier.

Figure 11 .
Figure 11.Block diagram of proposed amplifier.

Figure 11 .
Figure 11.Block diagram of proposed amplifier.

Figure 13 .
Figure 13.Open-loop gain under 50 pF load.(a) Open-loop gain and phase at tt corner.(b) Openloop gain and phase at ss corner.(c) Open-loop gain and phase at ff corner.

Figure 14
Figure 14 depicts the power-supply gain of the proposed amplifier.These are obtained as −56.02 dB at tt, −61.35 dB at ss, and −43.37 dB at ff, respectively.Regarding the power supply rejection ratio (PSRR), the obtained values are 56.02dB at tt, 61.35 dB at ss, and 43.37 dB at ff, respectively.Figure 15 depicts the common-mode gain of the proposed amplifier.These are −57.11dB at tt, −66.76 dB at ss, and −42.61 dB at ff, respectively.These yield the common-mode rejection ratio (CMRR) of 57.11 dB at tt, 66.76 dB at ss, and 42.61 dB at ff, respectively.Due to the high differential-mode gain at low frequency, the obtained PSRR and CMRR values are high.

Figure 13 .
Figure 13.Open-loop gain under 50 pF load.(a) Open-loop gain and phase at tt corner.(b) Open-loop gain and phase at ss corner.(c) Open-loop gain and phase at ff corner.

Figure 16
Figure 16 illustrates 200 runs of Monte Carlo simulations pertaining to offset voltage.The mean offset voltage is 0.391 mV, which is less than 1 mV.This suggests that the op-amp exhibits low offset in the context of process variation.

Figure 16 .
Figure 16.Histogram of offset voltage under 200 runs of Monte Carlo simulations at 50 pF load.

Figure 16 .
Figure 16.Histogram of offset voltage under 200 runs of Monte Carlo simulations at 50 pF load.

Figure 17 .
Figure 17.Common mode range of input and output with different input topology designs with/without low-voltage attenuator.

Figure 17 .
Figure 17.Common mode range of input and output with different input topology designs with/without low-voltage attenuator.

Figure 18 .
Figure 18.Common mode range of input and output under 50 pF load.

Figure 18 .
Figure 18.Common mode range of input output under 50 pF load.

Figure 19 .
Figure 19.Transient response and slew rate of proposed amplifier.

Figure 19 .
Figure 19.Transient response and slew rate of proposed amplifier.The input-referred noise simulation results are shown in Figure 20.At 1 kHz, the input-referred noise can be obtained as 213.63 nV/ √ Hz at tt, 343.96 nV/ √ Hz at ss, and 214.91 nV/√ Hz at ff, respectively.Due to relatively higher g mi being obtained from the rail-to-rail bulk-drain-driven topology, the noise performance metrics are better when compared to the bulk-driven input stage design.This also proves that the degeneration effect from the bulk-drain transistor is not significant.Therefore, it is not of concern.

Figure 21 .
Figure 21.Simulation of gmi against different input common-mode voltages.

Figures 22 -
Figures 22-28 illustrate 200 runs of Monte Carlo simulations pertaining to DC gain, GBW, PM, GM, CMRR, PSRR, and noise with estimated layout parasitics, respectively.According to Figures 22 and 23, the mean DC gain and GBW are 84.01 dB and 153.8 kHz, respectively, which are close to the simulation results without considering the parasitic capacitances.Regarding Figures 24 and 25, the mean PM and GM are 79.39 deg and 4.7 dB, respectively.Despite some reduction in PM and GM, these are still acceptable after taking into account parasitic effects, as PM is still maintained at a high rate.As seen in Figures26 and 27, the mean CMRR and PSRR are 49.3 dB and 49.1 dB, respectively.There is no significant difference when taking the parasitic effect into account.The mean noise is obtained as 205.47 nV/√Hz, which shows that the op-amp's noise is still low when including the parasitic effect according to Figure28.Figure29shows that the mean power consumption is 0.95 µW.These suggest that the op-amp exhibits good performance in the context of process variation and parasitic effects.
Figures 22-28 illustrate 200 runs of Monte Carlo simulations pertaining to DC gain, GBW, PM, GM, CMRR, PSRR, and noise with estimated layout parasitics, respectively.According to Figures 22 and 23, the mean DC gain and GBW are 84.01 dB and 153.8 kHz, respectively, which are close to the simulation results without considering the parasitic capacitances.Regarding Figures 24 and 25, the mean PM and GM are 79.39 deg and 4.7 dB, respectively.Despite some reduction in PM and GM, these are still acceptable after taking into account parasitic effects, as PM is still maintained at a high rate.As seen in Figures26 and 27, the mean CMRR and PSRR are 49.3 dB and 49.1 dB, respectively.There is no significant difference when taking the parasitic effect into account.The mean noise is obtained as 205.47 nV/√Hz, which shows that the op-amp's noise is still low when including the parasitic effect according to Figure28.Figure29shows that the mean power consumption is 0.95 µW.These suggest that the op-amp exhibits good performance in the context of process variation and parasitic effects.

Figure 22 .
Figure 22.Histogram of DC gain under 200 runs of Monte Carlo simulations with estimated parasitics.

Figure 21 .
Figure 21.Simulation of g mi against different input common-mode voltages.

Figures 22 -
Figures 22-28 illustrate 200 runs of Monte Carlo simulations pertaining to DC gain, GBW, PM, GM, CMRR, PSRR, and noise with estimated layout parasitics, respectively.According to Figures 22 and 23, the mean DC gain and GBW are 84.01 dB and 153.8 kHz, respectively, which are close to the simulation results without considering the parasitic capacitances.Regarding Figures 24 and 25, the mean PM and GM are 79.39 deg and 4.7 dB, respectively.Despite some reduction in PM and GM, these are still acceptable after taking into account parasitic effects, as PM is still maintained at a high rate.As seen in Figures26 and 27, the mean CMRR and PSRR are 49.3 dB and 49.1 dB, respectively.There is no significant difference when taking the parasitic effect into account.The mean noise is obtained as 205.47 nV/ √ Hz, which shows that the op-amp's noise is still low when including the parasitic effect according to Figure28.Figure29shows that the mean power consumption is 0.95 µW.These suggest that the op-amp exhibits good performance in the context of process variation and parasitic effects.
Figures 22-28 illustrate 200 runs of Monte Carlo simulations pertaining to DC gain, GBW, PM, GM, CMRR, PSRR, and noise with estimated layout parasitics, respectively.According to Figures 22 and 23, the mean DC gain and GBW are 84.01 dB and 153.8 kHz, respectively, which are close to the simulation results without considering the parasitic capacitances.Regarding Figures 24 and 25, the mean PM and GM are 79.39 deg and 4.7 dB, respectively.Despite some reduction in PM and GM, these are still acceptable after taking into account parasitic effects, as PM is still maintained at a high rate.As seen in Figures26 and 27, the mean CMRR and PSRR are 49.3 dB and 49.1 dB, respectively.There is no significant difference when taking the parasitic effect into account.The mean noise is obtained as 205.47 nV/ √ Hz, which shows that the op-amp's noise is still low when including the parasitic effect according to Figure28.Figure29shows that the mean power consumption is 0.95 µW.These suggest that the op-amp exhibits good performance in the context of process variation and parasitic effects.

Figure 21 .
Figure 21.Simulation of gmi against different input common-mode voltages.

Figures 22 -
Figures 22-28 illustrate 200 runs of Monte Carlo simulations pertaining to DC gain, GBW, PM, GM, CMRR, PSRR, and noise with estimated layout parasitics, respectively.According to Figures 22 and 23, the mean DC gain and GBW are 84.01 dB and 153.8 kHz, respectively, which are close to the simulation results without considering the parasitic capacitances.Regarding Figures 24 and 25, the mean PM and GM are 79.39 deg and 4.7 dB, respectively.Despite some reduction in PM and GM, these are still acceptable after taking into account parasitic effects, as PM is still maintained at a high rate.As seen in Figures26 and 27, the mean CMRR and PSRR are 49.3 dB and 49.1 dB, respectively.There is no significant difference when taking the parasitic effect into account.The mean noise is obtained as 205.47 nV/√Hz, which shows that the op-amp's noise is still low when including the parasitic effect according to Figure28.Figure29shows that the mean power consumption is 0.95 µW.These suggest that the op-amp exhibits good performance in the context of process variation and parasitic effects.
Figures 22-28 illustrate 200 runs of Monte Carlo simulations pertaining to DC gain, GBW, PM, GM, CMRR, PSRR, and noise with estimated layout parasitics, respectively.According to Figures 22 and 23, the mean DC gain and GBW are 84.01 dB and 153.8 kHz, respectively, which are close to the simulation results without considering the parasitic capacitances.Regarding Figures 24 and 25, the mean PM and GM are 79.39 deg and 4.7 dB, respectively.Despite some reduction in PM and GM, these are still acceptable after taking into account parasitic effects, as PM is still maintained at a high rate.As seen in Figures26 and 27, the mean CMRR and PSRR are 49.3 dB and 49.1 dB, respectively.There is no significant difference when taking the parasitic effect into account.The mean noise is obtained as 205.47 nV/√Hz, which shows that the op-amp's noise is still low when including the parasitic effect according to Figure28.Figure29shows that the mean power consumption is 0.95 µW.These suggest that the op-amp exhibits good performance in the context of process variation and parasitic effects.

Figure 22 .
Figure 22.Histogram of DC gain under 200 runs of Monte Carlo simulations with estimated parasitics.Figure 22. Histogram of DC gain under 200 runs of Monte Carlo simulations with estimated parasitics.

Figure 22 .
Figure 22.Histogram of DC gain under 200 runs of Monte Carlo simulations with estimated parasitics.Figure 22. Histogram of DC gain under 200 runs of Monte Carlo simulations with estimated parasitics.

Figure 23 .
Figure 23.Histogram of GBW under 200 runs of Monte Carlo simulations with estimated parasitics.

Figure 24 .
Figure 24.Histogram of PM under 200 runs of Monte Carlo simulations with estimated parasitics.

Figure 25 .
Figure 25.Histogram of GM under 200 runs of Monte Carlo simulations with estimated parasitics.

Figure 23 .Figure 23 .
Figure 23.Histogram of GBW under 200 runs of Monte Carlo simulations with estimated parasitics.

Figure 24 .
Figure 24.Histogram of PM under 200 runs of Monte Carlo simulations with estimated parasitics.

Figure 25 .
Figure 25.Histogram of GM under 200 runs of Monte Carlo simulations with estimated parasitics.

Figure 24 .Figure 23 .
Figure 24.Histogram of PM under 200 runs of Monte Carlo simulations with estimated parasitics.

Figure 24 .
Figure 24.Histogram of PM under 200 runs of Monte Carlo simulations with estimated parasitics.

Figure 25 .
Figure 25.Histogram of GM under 200 runs of Monte Carlo simulations with estimated parasitics.Figure 25.Histogram of GM under 200 runs of Monte Carlo simulations with estimated parasitics.

Figure 25 .
Figure 25.Histogram of GM under 200 runs of Monte Carlo simulations with estimated parasitics.Figure 25.Histogram of GM under 200 runs of Monte Carlo simulations with estimated parasitics.

Figure 26 .
Figure 26.Histogram of CMRR under 200 runs of Monte Carlo simulations with estimated parasitics.

Figure 27 .
Figure 27.Histogram of PSRR under 200 runs of Monte Carlo simulations with estimated parasitics.

Figure 28 .
Figure 28.Histogram of noise under 200 runs of Monte Carlo simulations with estimated parasitics.

Figure 26 .Figure 26 .
Figure 26.Histogram of CMRR under 200 runs of Monte Carlo simulations with estimated parasitics.

Figure 27 .
Figure 27.Histogram of PSRR under 200 runs of Monte Carlo simulations with estimated parasitics.

Figure 28 .
Figure 28.Histogram of noise under 200 runs of Monte Carlo simulations with estimated parasitics.

Figure 27 .Figure 26 .
Figure 27.Histogram of PSRR under 200 runs of Monte Carlo simulations with estimated parasitics.

Figure 27 .
Figure 27.Histogram of PSRR under 200 runs of Monte Carlo simulations with estimated parasitics.

Figure 28 .
Figure 28.Histogram of noise under 200 runs of Monte Carlo simulations with estimated parasitics.Figure 28.Histogram of noise under 200 runs of Monte Carlo simulations with estimated parasitics.

Figure 28 .
Figure 28.Histogram of noise under 200 runs of Monte Carlo simulations with estimated parasitics.Figure 28.Histogram of noise under 200 runs of Monte Carlo simulations with estimated parasitics.

Figure 29 .
Figure 29.Histogram of Pw under 200 runs of Monte Carlo simulations with estimated parasitics.

Figure 29 .
Figure 29.Histogram of P w under 200 runs of Monte Carlo simulations with estimated parasitics.

Figure 30 .Table 5 .
Figure 30.Comparison of open-loop results between spectra simulation and MATLAB models at 50pF capacitive load.Table 5. Performance comparison of proposed amplifier with previously-reported low-voltage amplifiers.

Figure 30 .
Figure 30.Comparison of open-loop results between spectra simulation and MATLAB models at 50pF capacitive load.

Table 1 .
Device size of proposed amplifier.

Table 1 .
Device size of proposed amplifier.

Table 4 .
Simulation results of proposed amplifier under 200 runs of Monte Carlo simulations with estimated parasitics.