Bandpass Sigma–Delta Modulation: The Path toward RF-to-Digital Conversion in Software-Deﬁned Radio

: This paper reviews the state of the art on bandpass Σ∆ modulators (BP-Σ∆ Ms) intended to digitize radio frequency (RF) signals. A priori, this is the most direct way to implement software-deﬁned radio (SDR) systems since the analog/digital interface is placed closer to the antenna, thus reducing the analog circuitry and doing most of the signal processing in the digital domain. In spite of their higher programmability and scalability, RF BP-Σ∆ M analog-to-digital converters (ADCs) require more energy to operate in the GHz range as compared with their low-pass (LP) counterparts. This makes conventional direct conversion receivers (DCRs) the commonplace approach due to their overall smaller energy consumption. This paper surveys some circuits and systems techniques which can make RF ADCs and SDR-based transceivers more efﬁcient and feasible to be embedded in mobile terminals.


Introduction
The micro/nanoelectronics industry has exponentially grown over the last six decades according to Moore's law, yielding to the integration of dozen of billions of transistors with dimensions closer to a few atoms of silicon. Among other benefits, high levels of integration allow to embed more and more functionalities onto a single chip, including sensing interfaces, communication systems, memory and computing, among others. In addition to the reduced cost, technology downscaling has pervasively miniaturized the electronic devices, going from multi-chip components connected in printed circuit boards (PCBs) to chip sets encapsulated in system-in-packages (SiPs) to monolithic system-onchip (SoC) solutions. This pervasive miniaturization is making it possible for electronic devices and their derived technologies-such as artificial intelligence (AI), big data, robotics, Internet of Things (IoT), etc.-to be more and more present in our daily lives [1][2][3]. These technologies are accelerating their pace of penetration, transforming many of our social and economic activities from a physical to virtual format. Indeed, our natural environment is being surrounded with a set of digital layers, which allows us to iterate with virtual entities and objects in an augmented reality-also referred to as the metaverse [4].
Communication systems are essential parts of IoT nodes and end terminals. In the majority of cases, information is transmitted wirelessly over radio frequency (RF) bands of the electromagnetic spectrum, i.e., carried out by analog signals. This requires an important portion of wireless transceivers to perform their functions in the analog/RF domain to adapt and transform signals from/to the digital domain, where they are processed by the digital signal processor (DSP). Unfortunately, analog components do not scale as digital parts do. Indeed, deep nanometer mainstream CMOS technologies are more suited to integrate fast digital transistors rather than accurate analog circuits. This is one of the main reasons why every time a new communication protocol is developed, it usually requires dedicated RF chip sets. As a consequence, the celerity with which new functionalities are incorporated in i-devices exceeds the rate of package reduction, and the trend from multi-chip to SiPs and SoCs The analog/RF-to-digital interface of multi-mode/multi-standard SDR transceivers can be implemented in two ways as depicted in Figure 2. In both cases, all building blocks need to be reconfigurable/programmable in order to adapt their performance to the required specifications. The approach in Figure 2a, known as direct conversion transceiver (DCT), translates the analog/RF signal from/to the RF domain to the baseband by means of an analog downconverter (in the receiver side) and an upconverter (in the transmitter side). This way, an LP ADC can be used to digitize downconverted signals in the receiver. Analogously, an LP DAC transforms the baseband digital data before being upconverted to RF in the transmitter. By contrast, the approach in Figure 2b requires to implement the analog/digital interfaces in the RF domain, i.e., an RF ADC in the receiver and an RF DAC in the transmitter. The main benefit of this approach is the reduced analog content, and hence, it is less sensitive to analog circuit impairments due to I/Q down-mixing, flicker noise and DC offset. However, the price to pay is that the RF/digital interface requirements are more demanding, with the subsequent penalty in the power consumption-a key factor in wireless transceivers and portable devices [12][13][14][15][16].
This paper focuses on the receiver path of SDR transceivers, considering the RFdigitization approach in Figure 2b and the ADC as one of its key building blocks. Target specifications for such an RF ADC may involve digitizing signals with an 8-12 bit effective resolution within a programmable 30 kHz-300 MHz bandwidth with a tunable carrier frequency ranging from 0.4 GHz to 6 GHz. These specifications should be fulfilled with a reduced amount of power to maximize device autonomy. Moreover, a high degree of programmability is needed in order to adapt the ADC performance to the electromagnetic environment conditions, band occupancy, number of interferences, battery status, etc. The state of the art on ADCs for wireless communications is dominated by three techniques or a combination of them, namely: Sigma-Delta modulators (Σ∆Ms), noise-shaping (NS) SAR and Pipeline. Although wideband Nyquist-rate ADCs-such as SAR, Pipeline or hybrid SAR-Pipeline-are potentially more efficient than Σ∆Ms for digitizing wideband signals, bandpass (BP) Σ∆Ms are, a priori, a better choice for implementing an early RF digitization of the desired signal band/channel in Figure 2b, with a high degree of tunability and adaptability of its performance metrics [17]. Since their conception in 1989 [18,19], a number of BP-Σ∆M ADCs have been reported to implement RF digitizers [16,[20][21][22][23][24][25][26][27][28][29][30][31][32][33][34][35][36]. In spite of the promise of being the best solution for RF-to-digital conversion, performance metrics of BP-Σ∆Ms are less efficient than their low-pass (LP) counterparts. The reasons behind this will be analyzed in this paper through a review of the state of the art. The main BP-Σ∆M architectures and circuit techniques will be overviewed and compared in terms of their main performance metrics, namely, effective resolution, operating frequency, and power dissipation. Cutting-edge circuits and systems will be identified to help designers select the most suited BP-Σ∆M topology and circuit technique according to their target specifications.
Following this introduction, the paper is organized as follows. Section 2 revisits the fundamentals and basic concepts of BP-Σ∆Ms, putting emphasis on the discrete-time (DT) implementations. Section 3 overviews continuous-time (CT) BP-Σ∆Ms, focusing on their use in RF ADCs in SDR receivers. Section 4 analyzes the state of the art on BP-Σ∆Ms and compares their performance metrics with Σ∆Ms and other kinds of ADCs. Emerging circuits and systems techniques are identified as potential game changers to digitize RF signals in SDR systems. Finally, conclusions are drawn in Section 5. Figure 3 shows the conceptual block diagram of a Σ∆M, which consists of a loop filter and a B-bit quantizer connected in a feedback loop [37]. Assuming a linear additive white noise model for the quantizer as depicted in Figure 3, the Z-transform of the Σ∆M output, y, can be written as follows.

Bandpass Σ∆ Modulators: Fundamentals and Basic Concepts
where STF and NTF stand for the signal-and noise-transfer functions, respectively, given by with k q being the gain of the quantizer and H(z) being the transfer function of the loop filter. Considering an Lth-order loop filter, the dynamic range (DR) of a Σ∆M can be approximately written as DR ≈ 6.02 · B + 1.76dB + 10 log 10 [(2L where OSR ≡ f s /(2 · B w ) stands for the oversampling ratio, f s is the sampling frequency, and B w is the signal bandwidth. The effective number of bits (ENOB) of a Σ∆M can be obtained from Equation (3) as Hence, Σ∆Ms increase ENOB with OSR by approximately 3(2L + 1) dB/octave-second term in (3). The three key parameters, namely OSR, L and B, define the system-level performance of Σ∆Ms, and can be combined in many ways, giving rise to a huge number of Σ∆Ms-LP or BP; single-loop or cascade; single-bit or multi-bit; continuous-time (CT) or switched-capacitor (SC)-in order to achieve the maximum DR. In the case of BP-Σ∆Ms-the object of this paper-the zeroes of the NTF are placed around an arbitrary frequency, usually referred to as the notch frequency, f n . This frequency corresponds to the carrier frequency of incoming signals in RF receivers as illustrated in Figure 4. The quantization noise is reduced only in a narrow band (B w ) around f n , thus taking advantage of a high OSR to meet the required DR according to Equation (3) [37].

Quantization Noise Shaping in BP-Σ∆Ms
BP-Σ∆Ms can be implemented using either discrete-time (DT)-basically switched capacitor (SC)-or CT circuit techniques. The latter are mostly used in RF ADCs due to their higher operating frequencies-in the GHz range. Moreover, CT circuits merge better with other circuits of the SDR receiver and implement some RF functions, such as out-of-band blocker, image-rejection filtering, anti-aliasing, etc. [38]. However, as will be discussed later in this paper, CT BP-Σ∆Ms are usually synthesized from their equivalent DT counterparts. In the analysis that follows, a DT realization is assumed without loss of generality.
In the more general case, the loop-filter of BP-Σ∆Ms is a 2Lth-order BP filter composed of LC resonators-or biquad sections-with a transfer function given by [39]: where N(z) denotes the numerator polynomial and z n and z * n stand for conjugate-complex poles of H(z). Replacing Equation (5) in Equation (2) and assuming k q = 1, it can be shown that the NTF of BP-Σ∆Ms can be expressed as which has L zeros placed at z = z n and z = z * n . Assuming that z n = e j·(2·π· f n ·T s ), with T s = 1/ f s being the sampling period, and considering that N(z) is designed so that the denominator in Equation (6) is unity, the NTF of an 2Lth-order BP-Σ∆M can be written as Note that NTF has its zeroes placed on the Z-domain unit circle at complex-conjugate z n and z * n , i.e., f = f n and f = − f n . This means that a 2Lth-order BP-Σ∆M has L zeroes placed at the signal band, thus being equivalent to an Lth-order LP-Σ∆M. As illustrated in the simulations shown in Figure 5, the notch frequency, f n , can be programmed in order to make BP-Σ∆Ms tunable within the Nyquist band, i.e., from DC to f s /2. As will be discussed later, this feature is applied in wireless transceivers to increase the programmability of RF digitizers by reducing the quantization noise around the desired signal channel.
The power spectral density (PSD) of the quantization noise shaped by BP-Σ∆Ms can be calculated as (8) where ∆ is the quantization step, defined as ∆ ≡ X FS /(2 B − 1), with X FS being the full-scale (FS) range of the quantizer. The quantization in-band noise power, P Q , can be computed by integrating PSD Q ( f ) in the signal bandwidth as Knowing that DR| dB = 10log[(X FS /2) 2 /(2 · P Q )], it can be shown that in the case of BP-Σ∆Ms, DR is given by [39] DR| BP ≈ 6.02 · B + 1.76dB + 10 log 10 [(2L + 1) · OSR (2L+1) /[π · sin(2π · f n · T s )] 2L ] (10) Note that the above expression is equal to (3) if f n = f s /4. This notch location is the most common case as discussed below.

Notch Frequency Location and Basic Architectures
One of the most common choices for the notch frequency is f n = f s /4 since this passband location optimizes the trade-off between anti-aliasing filtering and image-rejection filtering in wireless transceivers based on BP-Σ∆Ms as that shown in Figure 2 [39]. The digital downconverter in Figure 2 can be notably simplified since the (digital) local oscillator (LO) signal is designed such that it generates a digital sinewave as which is a data series of +1 s, 0 s, and −1 s, easily implemented by simple digital logic. This makes it easier and simple the gate-level implementation of the digital mixer and the numerical controlled oscillator (NCO) in Figure 2. More importantly, assuming f n = f s /4 in (7), the NTF of a 2L-th order BP-Σ∆M yields which can be derived by applying a z → −z 2 transformation to the NTF of a Lth-order lowpass (LP) Σ∆M, given by (1 − z −1 ) L [37]. This way, any arbitrary BP-Σ∆M can be derived from an initial LP-Σ∆M by applying this Z-domain transformation. Figure 6 illustrates this transformation applied to a 2nd-order LP-Σ∆M, which becomes a 4th-order BP-Σ∆M, and loop-filter integrators are transformed into resonators. The z → −z 2 transformation also allows to place the input signal at 3 f s /4 [40] instead of f s /4 given that the spectrum is symmetrical with respect to f s /2. Making f IF = 3 f s /4 preserves the requirements of the anti-aliasing filter compared to the f IF = f s /4 case, but the image-rejection filter specifications can be relaxed. In addition, it allows for either the clock rate to be reduced to 1/3 or the signal processing to be three times faster. However, the OSR is also reduced by a factor of three with the subsequent penalty in DR loss.
Placing the signal band around f s /4 also has some disadvantages. On the one hand, in the presence of nonlinearities of the analog circuitry of the Σ∆M, any intermodulation distortion products resulting from the mixing of tones at f s /2 with the input signal will fall inside the modulator passband and will thus corrupt the signal information. On the other, for a given RF input, the clock rate demands are more restrictive than placing f n between f s /4 and f s /2. For instance, those wireless standards-such as some IEEE 802.11 standard-operating in the frequency band of 5 GHz would require a sampling frequency of 20 GHz, with the subsequent penalty in power dissipation [41].
Although placing the notch frequency at f s /4 is the most common approach, other alternative approaches have been reported to synthesize BP-Σ∆Ms and allocate the zeroes of the NTF. Some techniques are based on the use of complex BP filters in quadrature architectures [42,43] as illustrated in Figure 7a. The resulting NTF has complex zeroes that are not necessarily conditioned to be placed symmetrically around DC. This allows an L-th order BP-Σ∆ to place L zeroes at f n without having any zero at − f n . The solution is more energy efficient than conventional approaches since no power is dedicated to digitizing the negative (imaginary) frequency bands [44]. One of the main limitations of this approach is the mismatch between both real and imaginary paths, which causes signal image components to appear in the signal band, thus corrupting the information. This problem can be mitigated by placing some zeroes in the imaginary band-as illustrated in Figure 7b. However, this reduces the ratio between the number of NTF zeroes and the filter order-one of the main benefits of quadrature BP-Σ∆Ms. Another alternative to reduce the clock rate as compared to the f n = f s /4 approach is based on time-interleaved (TI) or P-path loop filters [45]. The idea of TI BP-Σ∆M consists of splitting a modulator clocked at f s in several TI BP-Σ∆M paths, each one operating at f s /P, with P being the number of paths, as illustrated in Figure 8. Similar to quadrature BP-Σ∆Ms, TI BP-Σ∆Ms are also limited by circuit impairments, such as offset, gain and timing mismatch, which causes spur tones to appear at the output spectrum, thus degrading the noise shaping [46]. Based on a similar idea, some authors proposed a polyphase decomposition of the NTF of BP-Σ∆Ms [47] as follows: where N j (z P ) stands for transfer functions of the j-th path BP-Σ∆M. For instance, let us assume a 2nd-order polyphase BP-Σ∆M with P = 2 and a NTF with zeros at z = e ±jα , given by In this case, the polyphase (P = 2) decomposition leads to N 0 (z −2 ) = 1 + z −2 and N 1 (z −2 ) = β, where β is a coefficient that changes the zeroes of NTF from z = 1 to z = −1, when it varies from β = −2 to β = 2. Assuming that β = −2 · cos(2π · f n · T s ), we obtain the expression of NTF given in Equation (7). It can be shown that the spur tones due to path mismatches fall out of the signal band at f s /P, with P being the number of paths used in the polyphase decomposition [47].

Continuous-Time BP-Σ∆Ms
The BP-Σ∆Ms described above assume a DT (usually SC) realization of the loop filter. However, CT BP-Σ∆Ms are more suited to digitize RF signals since GHz-range sampling rates are needed. CT loop filters can operate at higher frequencies than their SC counterparts, while consuming less power and implement an inherent anti-aliasing filtering. The loop-filter of CT BP-Σ∆Ms can be realized using either active (RC or Gm-C) resonators or passive LC resonators as conceptually depicted in Figure 9. RF BP-Σ∆Ms have two main design challenges. The first is to achieve a high-quality and accurate resonance frequency. The second is to target a wide tuning range of the carrier (or notch) frequency. LC tanks are a good approach from a power and linearity perspective, although they typically support only an octave of range, whereas active-(Gm-C/RC) resonators can be widely tunable but require amplifiers with strong requirements-high DC gain and gain bandwidth (GB) [48]. Single op amp resonators are a good alternative to reduce power consumption. Some authors propose the use of positive feedback-implemented by a passive RC network-to enhance the quality factor of resonators. Figure 9d illustrates this approach proposed by Chae et al. [49]. Regardless of the circuit technique used to implement CT BP-Σ∆Ms, it is difficult to keep the required specifications within a wide tuning range. For that reason, it is usual to set the notch frequency constant, usually located at f n = f s /4. For the analysis that follows, this approach will be considered and the problem of tuning f n will be discussed later. Figure 10 shows the block diagram of the two common approaches to implement CT BP-Σ∆Ms with multi-path feedback, based on ideal (LC) resonators with a transfer function,

LC-Based CT BP-Σ∆M Architectures
. Normalized values of s and ω o are considered with respect to f s so that s = 2π f / f s (with f standing for the frequency variable) and ω o = 2π f n / f s . A 4th-order loop filter made up of two resonators with f n = f s /4 is considered. The feedback loop is implemented in two main different ways. Figure 10a [50] uses two different DAC pulse shapes, return-to-zero (RZ) and half-delay return-to-zero (HRZ), while Figure 10b [51] includes a non-return-to-zero (NRZ) DAC with different delay for each path. For the sake of simplicity, the excess loop delay (ELD) compensation path is not considered. In both cases, multiple feedback paths with their scaling coefficients are required to increase the degrees of freedom in the synthesis process, correctly restoring NTF of the DT Z-domain counterpart.
The CT BP-Σ∆Ms shown in Figure 10 can be synthesized as follows. The Schreier's toolbox [52] is used to obtain the NTF which satisfies the required specifications in terms of DR and B w with an out-of-band gain (OBG) (usually 1.5), and the DT version of the loop filter transfer function can be easily derived as H(z) = 1 − 1/NTF(z). The DT version of the loop-filter transfer function, H(z), of the desired BP CT-Σ∆M is therefore derived from the well-known impulse-invariant transformation as where Z(·) and L(·) denote the Z-transform and L-transform symbols, respectively, and H DAC (s) is the transfer function of the DAC [37,53].

Widely Tunable CT BP-Σ∆Ms
As stated above, one of the challenges of RF ADCs is the high sampling frequency required. Using a fixed value of f n (normally f n = f s /4), forces the variation of f s in order to tune the desired carrier frequency of the RF signal. For instance, if the incoming RF signal is placed at f n = 5 GHz, the sampling frequency should be f s = 4 · f n = 20 GHz. Moreover, another important inconvenience of this approach is that a widely programmable PLLbased synthesizer is needed to vary f s according to the f n needed to place the in-coming RF signal within the passband of the modulator. For instance, if an RF ADC needs to digitize RF signals which are placed in the wireless commercial band, i.e., 0.4-6 GHz, this would require a PLL with a frequency tuning range from 1.6 GHz to 24 GHz! These limitations have motivated the interest for programmable CT BP-Σ∆Ms with tunable notch frequency [24,25]. In the majority of cases, tuning range of notch frequency is limited by stability of the modulator loop filter. This problem can be circumvented if the notch frequency is taken into account as a design parameter of the BP-Σ∆M. This approach, referred to as notch-aware systematic methodology [41], allows to increase the tunable notch-frequency range of LC-based BP-Σ∆Ms with respect to prior art, ranging from 0.1 f s to 0.4 f s , while keeping their performance in terms of noise shaping, stability and sensitivity to architecture-and circuit-level nonideal effects [41].
As an illustration, let us consider the Gm-LC BP-Σ∆M with 4-bit quantizer shown in Figure 11. This modulator was synthesized using the notch-aware synthesis methodology. First, the Schreier toolbox is used to obtain the DT version of the NTF. The next step consists of obtaining the open-loop transfer function-from the modulator output to the input of the quantizer, computed for the different feedback branches with gain c i in Figure 10b as follows: where · denotes the floor operator, v ≡ f s /(2 f n ) = π/ω, and H NRZ-DAC (s) stands for the transfer function of the NRZ DAC, respectively given by The resulted modulator loop filter can be implemented using Gm-LC resonators as shown in Figure 11a. This circuit implementation increases the programmability of the loopfilter coefficients, which are realized as switchable unitary transconductance elements, g mu as illustrated in Figure 11b. It can be shown that the block diagrams in Figures 10b and 11 are equivalent, if the following relationships are satisfied: (18) where V FS stands for the full-scale reference voltage, k 1,2 = k/s r1,2 and k 3 = 1/(s r1 · s r2 ) are scaling forward-path coefficients, and s r1,2 are the weight coefficients which scale the resonator gain, R gain = ω · s. This way, the notch frequency of the modulator can be tuned as illustrated in the simulated output spectra shown in Figure 11c.

State of the Art on BP-Σ∆Ms
Since the first BP-Σ∆M was reported in the beginning of the 1990s [55], a vast number of integrated circuits (ICs) using diverse technologies, architectures and circuit techniques have been proposed [37]. The most important specifications of any ADC are the signal bandwidth, B w , and the ENOB. In the case of BP-Σ∆Ms, the notch frequency, f n , should be also considered since it would affect the amount of energy (power) needed to digitize a signal placed on it. Tables 1 and 2 sum up the performance of the state-of-the-art BP-Σ∆M ICs considered in this survey. The data analyzed in this work are collected in a spreadsheet available at http://www.imse-cnm.csic.es/~jrosa/CMOS-SDMs-Survey-IMSE-JMdelaRosa_DEC2022.xlsx.

Low-Pass vs. Bandpass Σ∆Ms
The analysis that follows focuses on BP-Σ∆Ms, and hence, it is useful first to compare their performance with other types of Σ∆Ms, generically grouped here as LP-Σ∆Ms. Figure 12 represents the performance of cutting-edge Σ∆Ms in terms of their main design specifications, i.e., the signal bandwidth, B w and the resolution, characterized here by the ENOB. This plot-usually referred to as an aperture plot-shows also the state-of-the-art front, limited by the noise spectral density (NSD) given by NSD| dBFS/Hz ≡ (P nd /B w )| dBFS/Hz (19) where P nd is the noise-plus-distortion power referred to the full-scale (FS) range of the converter [48]. Note that the state-of-the-art front is dominated by LP-Σ∆Ms, which approaches NSD = −170 dBFS/Hz, although there are some BP-Σ∆Ms close to NSD = −160 dBFS/Hz, while digitizing signals with bandwidths over 100 MHz [36,88]. Apart from the main ADC specifications, ENOB and B w , it is common to compare the efficiency of (Σ∆) ADCs in terms of the amount of energy per converted sample-also referred to as conversion energy, E, defined as [94,95] where P stands for the power dissipated in Watts (W), and f snyq ≡ 2 · B w , is the effective Nyquist rate, measured in samples per second (S/s). Figure 13 plots the conversion energy versus ENOB-also known as an energy plot [94,96]. This picture represents graphically the trade-off between resolution and conversion energy such that the larger the resolution, the more conversion energy is needed. It is therefore convenient to express this trade-off in a figure of merit (FOM), which takes into account the main performance metrics of an ADC, i.e., ENOB, B w and P. The following two FOMs are the most used by the ADC designers community: FOMW ≡ E(J) 2 ENOB(bit) FOMS ≡ SNDR(dB) + 10 · log 10 [B w (Hz)/P(W)] (21) where SNDR is related to ENOB as SNDR(dB) = 10 · log 10 [(3/2) · 4 ENOB(bit) ] = 6.02 · ENOB(bit) + 1.76. FOMW, measured in J/conversion-step, was proposed by Walden [97], whereas FOMS is based on a FOM originally proposed by Rabii and Wooley [98], computed on a logarithmic scale, as suggested by Schreier and Temes in [99]. Note that FOMS can be also expressed in the following form: where P sig| dBFS denotes the input signal power computed in dB referred to the FS range of the converter. Therefore, the smaller the FOMW value and the larger the FOMS value, the "better" the ADC is. As a reference, FOMW and FOMS are also depicted in Figure 13, considering the following numerical values: FOMW =1 and 10 fJ/conv-step; FOMS = 175 dB and 185 dB. The resulted lines of constant FOMW and FOMS in Figure 13 can be respectively determined from Equation (21) as As shown, the most efficient designs are based on LP-Σ∆Ms-mostly implemented with CT circuits-some of them featuring a FOMS between 175 dB and 185 dB [100][101][102][103][104][105][106][107][108].
It is clear from Figure 13 that LP-Σ∆Ms obtain better performance in terms of conversion energy than BP-Σ∆Ms. However, it should be noted that the way in which such a conversion energy is computed-based on B w -might not be adequate for quantifying the efficiency of BP-Σ∆Ms because B w is not always representative of the operating frequency of the modulator in this case. For that reason, some authors propose alternative FOMs, such as the following one [109]: which takes into account not only B w but also the notch frequency, f n to measure the conversion energy (E). The reader can note that the use of FOM BP would increase the number of BP-Σ∆Ms placed at the cutting edge of the state of the art, although the comparison might be not so fair in this case for LP-Σ∆Ms. This is illustrated in Figure 14, which shows the conversion energy redefined as As will be discussed later, new generations of BP-Σ∆Ms are being developed in order to make RF digitizers more feasible. Thus, it is interesting to compare the performance of BP-Σ∆Ms in terms of different architectures, circuits and systems techniques. According to the discussion above, especial emphasis will be put not only on B w but also on f n .  Figure 15a compares the performance of SC and CT BP-Σ∆Ms by plotting ENOB vs. f n . As one may expect, the notch frequencies of CT BP-Σ∆Ms are higher than their SC counterparts. The f n of SC implementations ranges from 1 MHz to less than 50 MHz, whereas CT BP-Σ∆Ms digitize signals placed at carrier frequencies ranging from 100 kHz to 3 GHz [34]. The same happens if the digitized bandwidth, B w , is considered as depicted in Figure 15b. In this case, CT BP-Σ∆Ms also covers a wider range of B w , ranging from 3 kHz to almost 300 MHz [88], with 19.3-bit to 8.3-bit ENOB, respectively. More details about the performance metrics achieved by SC and CT BP-Σ∆Ms are shown in Tables 1 and 2, respectively. Under similar requirements, the energy consumed by CT BP-Σ∆Ms is less than that obtained by SC BP-Σ∆Ms as illustrated in the energy plot shown in Figure 15c. Figure 16 compares CT BP-Σ∆Ms in terms of the circuit techniques used to implement the loop filter (LF), namely, LC-based or inductorless, i.e., Gm-C, and active-RC. Although the highest notch frequencies are reached by LC-based BP-Σ∆Ms, there is not a clear advantage with respect to inductorless implementations as depicted in Figure 16a. In terms of energy, inductorless implementations are more efficient as illustrated in Figure 16b, reaching higher resolutions (over 12-bit ENOB). Contrary to what might be expected, LC-based BP-Σ∆Ms are not necessarily better to digitize RF signals when compared to BP-Σ∆Ms based on active-RC/Gm-C resonators.   Figure 17 shows the performance of CT BP-Σ∆Ms in terms of the loop-filter order, L, by comparing those architectures with a 2nd-order (L = 2) loop filter and those with L > 2. There is not a clear benefit in terms of frequency operation by increasing the order, as shown in Figure 17a, although the ENOB improves with L, as expected. However, if the target ENOB is less than 12-bit, 2nd-order loop filters are more energy efficient than high-order architectures as illustrated in Figure 17b. Figure 18 compares single-bit vs. multi-bit CT BP-Σ∆Ms. The vast majority of BP-Σ∆Ms uses a single-bit quantizer and dominates the state of the art, both in terms of frequency range, Figure 18a, and energy efficiency, Figure 18b. Multi-bit implementations are only advantageous if ENOB < 12 bit, although there are more single-bit BP-Σ∆Ms featuring higher resolutions in a wider tuning frequency range. This result is somehow logical since multi-bit quantization involves more complex dynamics in the loop filter, especially in the fast loop of CT BP-Σ∆Ms. This is especially limiting when GHz-range clock signals are required.

Lessons Learned from State-of-the-Art BP-Σ∆Ms
From the analysis of the state of the art described above, it can be concluded that low-order (L = 2, 4), single-bit CT BP-Σ∆Ms are the best architectures in terms of operating frequency ( f n ), ENOB and conversion energy. However, regardless of the architecture and circuit technique used, BP-Σ∆Ms are not competitive yet with their LP counterparts, which explains why direct-conversion receivers are the preferred choice in mobile terminals even though they are sensitive to analog impairments of I/Q downconversion. In order to make BP-Σ∆Ms more efficient for RF ADCs in SDR, it is needed to adopt circuit techniques which can increase the carrier (notch) frequency programmability, with reduced power consumption and (analog) hardware complexity.
Where the loop filter (LF) is concerned, highly programmable scaling-friendly amplifier stages, such as those based on inverter-based OTAs-originally proposed by Nauta [110]-are good candidates to implement both LC-based and active-(GmC) resonators. These circuits have been mostly used in LP-Σ∆Ms, but very little has been done in BP-Σ∆Ms [54]. Hybrid active/passive circuits, such as those used by Chae et al. [49], can be exploited to reduce the power dissipation of GHz-range BP-Σ∆Ms. Moreover, switchable passive RC networks are also suited to implement reconfigurable LFs as well as frequency interleaving [88] and N-path structures. The latter has been used in BP-Σ∆Ms, although limited to carrier frequencies in the range of hundreds of MHz [87]. However, N-path filters have demonstrated a widely tuning range in GHz filters [111]. This feature should be exploited in BP-Σ∆M RF ADCs.
Regarding the quantizer, a 1-bit ADC, i.e., a simple (regenerative latch) comparator, is the preferred choice by most state-of-the-art BP-Σ∆Ms. Multi-bit quantization increases hardware complexity and dynamic requirements in GHz-clocked BP-Σ∆Ms, as well as the linearity specifications of the feedback DAC. However, single-bit CT BP-Σ∆Ms are more sensitive to clock jitter, which becomes one of the main limiting factors in RF ADCs. This problem can be palliated by using a finite-impulse response (FIR) feedback DAC since it filters the FS comparator output such that a two-level data sequence is transformed into multi-level data. This reduces the height of steps in the DAC waveform, thus reducing the magnitude of the error signal exciting the LF of the BP-Σ∆M. FIR-DACs have been widely used in CT LP-Σ∆Ms, but their benefits have not been exploited yet in BP-Σ∆Ms.

Conclusions
An early digitization is desired in multi-mode/multi-standard wireless transceivers and SDR systems. This approach allows to move most of the signal processing from the analog to the digital domain, thus benefiting from technology downscaling and a higher programmability. BP-Σ∆Ms are a priori the best candidates to implement RF ADCs in SDRs since they directly digitize RF signals without the need for downmixing them to the baseband. In spite of these benefits, BP-Σ∆Ms are less efficient than LP-Σ∆Ms due to the demanding specifications required for the loop-filter circuit to operate at GHz carrier or notch frequencies. The lessons learned from the analysis of the state of the art on BP-Σ∆Ms carried out in this paper yield the following conclusions: • System-level: A more simple BP-Σ∆M architecture-based on a 2nd-or 4th-order loop filter and a 1-bit quantizer-achieves cutting-edge performance, being a good choice that balances performance and efficiency. • Circuit-level: There are some circuit strategies which can improve the performance of BP-Σ∆Ms in terms of power consumption, scaling and reconfigurability. Among others, the following techniques are good candidates: inverter-based OTAs, N-path filtering, FIR-filtered feedback DAC and embedded time/frequency-interleaving topologies.
The combination of the above circuits and systems strategies can enhance the efficiency of BP-Σ∆Ms to digitize RF signals with the specifications required for SDR transceivers: 8-to-12 bit effective resolution within a programmable 30 kHz-to-300 MHz bandwidth and a tunable carrier frequency ranging from 0.4 GHz to 6 GHz.
Thirty years after the first BP-Σ∆M chip was published, the path toward an efficient RF ADC might be closer to making SDR-based mobile handsets a reality.
Funding: This work was supported in part by Grant PID2019-103876RB-I00, funded by MCIN/AEI/ 10.13039/501100011033, by the European Union "ESF Investing in your future", and by "Junta de Andalucía" under contract P20-00599.
Institutional Review Board Statement: Not applicable.

Informed Consent Statement: Not applicable.
Data Availability Statement: Not applicable.

Conflicts of Interest:
The authors declare no conflict of interest.